Abstract: A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings.

Abstract: A method of forming a connection layer by filling an Al-based material wherein planarization of an entire surface of a substrate is achieved. 1 Al-based material 10 is deposited and filled in concave sections 4,8 formed in a substrate 1 under a high temperature, and then the surface of the Al-base material is polished with unwoven cloth or an etching liquid. 2 In a lithography process using an alignment mark for alignment on a substrate, an Al-based material is deposited and filled in a concave section in a portion other than the alignment mark for alignment under a high temperature, and then the surface of the Al-based material is polished. 3 In a process to deposit an Al-based material on a substrate and then planarize the surface of the Al-based material by polishing, an antireflection film is deposited on the Al-based material after the Al-based material is planarized.

Abstract: Disclosed is a method for forming a fine contact hole, and more particularly, a method capable of minimizing the loss of a silicon substrate. In the method for forming the contact hole according to the present invention, since the spacer is formed on the sidewall in the contact hole at the time of performing the dry etching process which makes it wide the approach to the contact hole, the contact area is hardly damaged by the etchant. Then, the dry etching process in accordance with the present invention can minimizes the loss of the substrate because the substrate to be exposed is under the protection of the insulating layer 43.

Abstract: A method for forming a patterned layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket target layer. There is then formed upon the blanket target layer a blanket focusing layer, where the blanket focusing layer is formed of an organic anti-reflective coating (ARC) material which is susceptible to a reproducible positive taper within a first etch method employed in forming from the blanket focusing layer a patterned focusing layer. The first etch method is a first plasma etch method employing an etchant gas composition comprising carbon tetrafluoride and argon. There is then formed upon the blanket focusing layer a blanket photoresist layer. The blanket photoresist layer is then photoexposed and developed layer to form a patterned photoresist layer.

Abstract: A method and apparatus for improving the accuracy of a contact to an underlying layer comprises the steps of forming a first photoresist layer over the underlying layer, forming a mask layer over the first photoresist layer, then forming a patterned second photoresist layer over the mask layer. The mask layer is patterned using the second photoresist layer as a pattern then the first photoresist layer is patterned using the mask layer as a pattern. A tapered hole is formed in the first photoresist layer, for example using an anisotropic etch. The tapered hole has a bottom proximate the underlying layer and a top distal the underlying layer with the top of the hole being wider than the bottom of the hole.

Abstract: A semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material includes, a) providing a node within a mass of insulating dielectric material; b) first stage etching into the insulating dielectric material over the node in a manner substantially selective relative to the node; c) after the first stage etching, second stage etching the dielectric material in a manner which increases a degree of sidewall polymerization over that occurring in the first stage etching and in a manner substantially selective relative to the node; and d) after the second stage etching, third stage etching the dielectric material with a degree of sidewall polymerization which is less than that of the second stage etching and in a manner substantially selective relative to the first node. An alternate method provides an etch stop annulus cap overlying an electrically conductive ring which projects from a primary insulating layer.

Abstract: A method of etching openings in a dielectric layer of a semiconductor device by utilizing a novel etchant gas system of sulfur hexafluoride/chlorine such that sloped sidewalls can be formed in the openings having a desired taper of between about 20.degree. and about 85.degree. for achieving improved step coverage and profile control of the TFT fabrication process.