Abstract: A method for forming a microelectronic device includes the steps of forming a spin-on-glass layer on a microelectronic substrate, and forming a capping layer on the spin-on-glass layer opposite the substrate. A masking layer is formed on the capping layer opposite the substrate wherein the masking layer exposes portions of the capping layer and the spin-on-glass layer. The exposed portions of said capping layer and the spin-on-glass layer are etched using the masking layer as an etch mask to thereby form a contact hole through the capping layer and the spin-on-glass layer wherein protruding edge portions of the capping layer extend beyond the spin-on-glass layer adjacent the contact hole. The mask layer is removed, and the protruding edge portions of the capping layer are removed from adjacent the contact hole.

Abstract: The reliability of in-laid metallization patterns, e.g., of copper or copper alloy, is significantly enhanced by voidlessly filling recesses in a substrate by an electroplating process, wherein "pinching-off" of the recess opening due to earlier formation of overhanging nucleation/seed layer deposits at the corners of the opening as a result of increased rates of deposition thereat is prevented. Embodiments include selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface by means of a directed beam etching or ablation process while rotating the substrate, which tapered width profile effectively prevents formation of overhanging deposits thereat which can result in occlusion and void formation during filling of the recesses by electroplating.

Abstract: An isolation structure and a method of making the same are provided. In one aspect, the method includes the steps of forming a trench in the substrate and a first insulating layer in the trench that has a bottom, a first sidewall and a second sidewall. Silicon nitride is deposited in the trench. Silicon nitride is removed from the bottom of the first insulating layer to establish a layer of silicon nitride on the first and second sidewalls by performing a first plasma etch of the deposited silicon nitride with an ambient containing He, SF.sub.6, and HBr, and a second plasma etch with an ambient containing He, SF.sub.6, and HBr. An insulating material is deposited in the trench. The method provides for reliable manufacture of nitride liners for trench isolation structures. Scaling is enhanced and the potential for parasitic leakage current due to liner oxide fracture or irregularity is reduced.

Abstract: A method of fabricating a node contact window. A substrate having devices and a first dielectric layer is provided. Bit lines having spacer are formed on the first dielectric layer and a second is formed on the first dielectric layer. A hard material layer is then formed on the second dielectric layer. An opening is formed within the second dielectric layer to expose the spacer and the first dielectric layer. A polysilicon spacer is then formed on the sidewalls of the opening. A node contact window is formed by etching through the first dielectric layer to expose the substrate.

Abstract: A method to fabricate bottle-shaped deep trench in a semiconductor substrate which mainly involves two substitute plasma etching steps from the conventional approach. After a neck profile is formed, instead of raising the plasma gas pressure while keeping the etching composition constant, as in the conventional approach, the plasma gas pressure is first maintained the same, then decreased substantially. On the other hand, the concentrations of HBr and NF.sub.3 are increased substantially in both new steps. The first substitute plasma etching step is conducted at a pressure of 100 mtorr an RF power of about 1,000 W, a magnetic field of 65 Gauss. The plasma gas composition consists of HBr, NF.sub.3, and (He/O.sub.2) a at a ratio of about 200:20:20. The second substitute plasma etching step is conducted at plasma gas pressure of 30 mtorr, an RF power of 600 W, a magnetic field of 65 Gauss. The plasma gas composition consists of HBr, NF.sub.3, and (He/O.sub.2) a at a ratio of about 150:13:20.

Abstract: A method for forming an isolating layer in a semiconductor device including the steps of sequentially forming a buffer oxide layer, a CVD oxide layer and a first nitride layer on a semiconductor substrate, selectively removing the first nitride layer, selectively exposing a surface of the semiconductor substrate using the first nitride layer as a mask, forming and planarizing a second nitride layer on the selectively exposed surface of the semiconductor substrate, removing the CVD oxide layer and buffer oxide layer using the second nitride layer as a mask, while leaving a nitride pattern layer which becomes wider in an upward direction, forming oxide sidewalls at sides of the nitride pattern layer, forming a trench having a slope by selectively etching the semiconductor substrate using the oxide sidewalls as a mask, depositing a filling insulating material layer on the nitride pattern layer, the oxide sidewalls and in the trench, planarizing the filling insulating material layer until a surface of the nitride

Abstract: In order that reaction products of low vapor pressure may be prevented from being deposited on the side wall of a predetermined pattern when this pattern is to be formed by dry-etching a Pt film or a PZT film, a resist mask 54 having a rounded outer periphery at its head is used when the Pt film 53 deposited on a semiconductor substrate 50 is to be dry-etched. After this dry-etching, moreover, an overetching of a proper extent is performed to completely remove the side wall deposited film 55 which is left on the side of the pattern. The resist mask 54 is formed by exposing and developing a benzophenone novolak resist and subsequently by heating to set it while irradiating it, if necessary, with ultraviolet rays.

Abstract: A method for etching a contact for forming a contact hole having a sidewall profile with a single process by controlling a flow rate of carrier gas at an etcher having a mixture of gases, the mixture including CF.sub.4, a polymer forming gas and a carrier gas, including steps for forming an insulation layer on a substrate, exposing a portion of the insulation layer by providing a photoresist pattern on the insulation layer, etching the insulation layer to form the contact hole, the contact hole having a sloped sidewall. The step of etching the insulation layer includes the steps of, introducing a plurality of gases into an etching chamber, the plurality of gases including a first gas including CF.sub.4, a second gas including a polymer forming gas, and a third gas including a balance gas and controlling a flow rate into the etching chamber of the balance gas, and removing the photoresist pattern from the insulation layer.

Abstract: A semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material includes, a) providing a node within a mass of insulating dielectric material; b) first stage etching into the insulating dielectric material over the node in a manner substantially selective relative to the node; c) after the first stage etching, second stage etching the dielectric material in a manner which increases a degree of sidewall polymerization over that occurring in the first stage etching and in a manner substantially selective relative to the node; and d) after the second stage etching, third stage etching the dielectric material with a degree of sidewall polymerization which is less than that of the second stage etching and in a manner substantially selective relative to the first node. An alternate method provides an etch stop annulus cap overlying an electrically conductive ring which projects from a primary insulating layer.

Abstract: A method of forming a field oxide or an isolation region in a semiconductor die. An oxidation mask layer (over an oxide layer disposed over the substrate) is patterned and subsequently etched, preferably so that the oxidation mask layer may have a nearly vertical sidewall. The oxide layer and the substrate in the isolation region are etched to form a recess in the substrate having a sloped surface with respect to the sidewall of the oxidation mask layer. A field oxide is then grown in the recess using a dry oxidizing atmosphere. The sloped sidewall of the substrate recess effectively moves the face of the exposed substrate away from the edge of the oxidation mask layer sidewall. Compared to non-sloped techniques, the oxidation appears to start with a built-in offset from the patterned etch. This leads to a reduction of oxide encroachment and less field oxide thinning. The preferred range of slopes for the substrate sidewall is from approximately 10.degree. to 40.degree.

Abstract: A barrier metal film, Al alloy film and anti-reflective film are sequentially deposited on a surface to form an interconnect pattern by a photolithography technique. An overhanging portion of the anti-reflective film is etched away by a plasma of a Cl.sub.2 /BCl.sub.3 -mixed gas. Then an insulating interlayer is deposited on a resultant semiconductor structure.

Abstract: In a fabrication method of a semiconductor apparatus, the semiconductor apparatus is made with a selective gold plating process rather than an ion-milling process. A tungsten film (W film) as a current supplying layer is formed on the entire front surface of an insulation film. The insulation film is formed on a GaAs substrate on which devices such as FETs are formed. With a mask of a photoresist film, a titanium (Ti) film, a platinum (Pt) film, and a gold (Au) film are successively evaporated and then lift-off process is performed. A photoresist film is patterned. A gold plate film with a thickness of 8 .mu.m is formed. The current supplying layer is removed by magnetron discharge plasma ion-etching process. Thick U-shaped gold plate lines are formed.

Abstract: Disclosed is a vertically oriented capacitor structure, which is of particular usefulness in MOS DRAM memory modules. The structure has upper and lower polysilicon capacitor plates separated by a dielectric layer, each of the plates and dielectric layers sloping at an angle with of about 80-85 degrees with respect to an underlying silicon substrate. As such, the novel capacitor is formed in a sloped contact opening. The contact area of electrical connection of the lower capacitor plate with an underlying active region has a sufficiently small horizontal cross-section that the contact area will not extend laterally beyond the active region and leakage will not occur. A method for forming the contact opening is disclosed and comprises first, the formation of an active region, preferably located between two insulating bird's beak regions, and covering the active area with a thin layer of oxide etch barrier material. A polysilicon layer is then formed above the oxide etch barrier.

Abstract: In a method of a semiconductor device, an insulating film on a semiconductor substrate is formed. Then, a first mask on the insulating film in a first region is formed and the insulating film is removed using the first mask for isolation insulating films in the first region. In this case, an element to be formed in the first region has a first active region. Also, a second mask is formed on the insulating film in a second region. The second mask is different from the first mask. The insulting film is removed using the second mask for isolation insulating films in the second region. In this case, a first element to be formed in the first region has a first active region narrower than a second active region of a second element to be formed in the second region. Generally, the insulating film in the first region is removed and then the insulating film in the second region is removed.

Abstract: An ultra-fine microfabrication method using an energy beam is based on the use of shielding provided by nanometer or micrometer sized micro-particles to produce a variety of three-dimensional fine structures which have not been possible by the traditional photolithographic technique which is basically designed to produce two-dimensional structures. When the basis technique of radiation of an energy beam and shielding is combined with a shield positioning technique using a magnetic, electrical field or laser beam, with or without the additional chemical effects provided by reactive gas particle beams or solutions, fine structures of very high aspect ratios can be produced with precision. Applications of devices having the fine structures produced by the method include wavelength shifting in optical communications, quantum effect devices and intensive laser devices.

Abstract: A method for minimizing the dimension of a contact forms a thick dielectric layer on a provided substrate first, and then forms a contact on the first dielectric layer and expose the substrate by performing a slope etching process. The contact with the target contact size is obtained by partially removing the thick dielectric layer. Since the target contact size is obtained by a self-aligned method, the upper diameter of the contact is not limited by a conventional fabrication process. Furthermore, after a contact is formed, it is optional to fill the contact with filler. Even after a desired contact is formed in the case that filler is used, the remains of the filler can be either kept or removed depending on the conductivity of the filler.

Abstract: A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

Abstract: A method for fabricating contact holes in high density integrated circuits and the resulting structure are disclosed. It is shown that by judiciously integrating the process of forming shallow tapered holes with self-alignment techniques, self-aligned holes can be fabricated with reduced number of masking process steps. This is accomplished by first forming shallow tapered holes to a certain depth over certain regions in a substrate by means of isotropic etching and then extending them by anisotropic etching to full depth corresponding to the regions they are allowed to contact. The net result is a whole set of holes which are self-aligned and which are formed by means of a single photoresist mask.

Abstract: A method for forming dual damascene metallic structure that utilizes the formation of a protective photoresist layer at the bottom of a vertical window to prevent damages to a device region in the substrate when subsequent etching operation is carried out to form a horizontal trench pattern. The protective photoresist layer at the bottom of the vertical window is formed by irradiating the photoresist layer with a dose of radiation having energy level insufficient to chemically dissociate the photoactive molecules of the photoresist layer near the bottom of the vertical window.

Abstract: Methods of forming contact openings over a node location and related integrated circuitry are described. In one aspect of the invention, a node location is formed within a semiconductive substrate adjacent an isolation oxide region. A layer of material is formed over the node location and a contact opening is etched through the layer of material to outwardly expose a node location planar upper surface. In one preferred implementation, the contact opening includes an inner surface portion which faces generally transversely away from the isolation oxide region and which defines an angle with the node location upper surface which is greater at a bottom of the contact opening than at a top of the contact opening. In another preferred implementation, the contact opening includes sidewall portions which define a profile which having a non-uniform degree of taper between the contact opening top and bottom.

Abstract: A wiring according to the present invention is made of a chromium layer and a chromium nitride layer. To make the wiring, a layer of chromium is deposited on a substrate, and then a layer of chromium nitride is deposited. A layer of photoresist is covered on the layer of chromium nitride and patterned, the layers of chromium and chromium nitride are wet etched in sequence using the photoresist pattern as a mask. Since the layer of chromium nitride is etched more quickly than the layer of chromium, the layer of photoresist and the layer of chromium are separated from each other and the chromium layer is isotropically etched to form a pattern having an edge with a gentle slope.

Abstract: A method for forming a patterned target layer within an integrated circuit. The method employs a plasma pre-treatment of a patterned photoresist layer employed in patterning a blanket focusing which in turn is employed in patterning the patterned target layer from a blanket target layer. The plasma pre-treatment employs a plasma pre-treatment composition comprising carbon tetrafluoride and argon without oxygen. After the plasma pre-treatment, the blanket focusing layer is etched with a reproducible negative etch bias in a plasma etch method employing an etchant gas composition comprising carbon tetrafluoride and argon without oxygen. Through the method there may be formed patterned target layers, with enhanced uniformity, of linewidth dimension as narrow as about of 0.25 microns while employing near ultra-violet (NUV) (ie: 365 nm) photoexposure methods.

Abstract: An adjustable method for making trenches for a semiconductor IC device having eliminated top corners is disclosed. The adjustable method includes forming a masking layer on the surface of the silicon nitride layer covering the device substrate that has openings corresponding to the openings of the trenches formed. Dimension of the masking layer opening is relatively greater than the dimension of the opening of the corresponding trench. An anisotropic etching procedure is then performed against the portions of the device substrate exposed out of the coverage of the masking layer, and the anisotropic etching shapes the trench sidewalls into sloped ones having larger dimension at the opening than at the surface of the filling material inside the trenches. This eliminates the top corners at the edges of the trench opening, charge accumulation and consequent leakage current can thus be prevented.

Abstract: A semiconductor device comprises a monocrystalline silicon wafer having a major surface lying in the {100} crystal plane. Disposed on the surface is a mesa having a generally square cross-section with generally rounded corners. The mesa has four main side walls each having a slope of around 45 degrees with respect to the base plane of the mesa, and the horizontal edges of the main side walls are disposed at an angle of at least around 12 degrees to the {111} directions on the wafer surface. The corners of the mesa each comprises a number of surfaces also having slopes of around 45 degrees and one surface having a slope of around 54 degrees. A high-low (N.sup.+ N.sup.- or P.sup.+ P.sup.-) junction is disposed within the mesa and makes a continuous line intercept with the mesa side walls around the entire periphery of the mesa. Except for exceptionally small deviations of no great significance, the high-low junction intercept is at a constant height location entirely around the mesa periphery.

Abstract: A method is disclosed for forming Y-shaped holes in semiconductor substrates by using Y-contact etching. The hole is formed with a single, two-step dry-etching process in a single chamber with one masking step for the whole hole. The upper portion of the Y-shaped hole is formed by means of an isotropic tapered dry-etching process while the lower portion is formed by means of a straight anisotropic recipe of the same dry-etching process. The result is a Y-shaped hole formed with fewer process steps and with maximized contact area for improved reliability.

Abstract: The present invention provides a method for fabricating shallow isolation trenches with sloped walls in semiconductor wafers. The method uses a conformal polysilicon layer to form an etch barrier over trench regions in a semiconductor substrate. This etch barrier has areas of varying thickness. The thickest areas of the etch barrier are located on the edges of trench structures and slow the etch process in the underlying substrate. The thinner regions of the etch barrier do not impede the etch process to as great an extent. This etch rate differential causes a sloped trench wall profile. The isolation trenches are completed by filling the surface with dielectric materials then planarizing.

Abstract: Method of fabricating thin-film transistors in which contact with connecting electrodes becomes reliable. When contact holes are formed, the bottom insulating layer is subjected to a wet etching process, thus producing undercuttings inside the contact holes. In order to remove the undercuttings, a light etching process is carried out to widen the contact holes. Thus, tapering section are obtained, and the covering of connection wiring is improved.

Abstract: The present invention relates to a method of forming a contact hole of a semiconductor device, and discloses a method of forming a contact hole of a semiconductor device which can remove an oxide film formed on the bottom of the contact hole, and make the edge portions of the entrance to the contact hole and reduce the topology of the contact hole by performing high frequency plasma etching processes in two stage in which the condition of pressure and electric power are different.

Abstract: A new method for planarizing a shallow trench isolation is disclosed by using a polysilicon layer or bottom anti-reflective coating (BARC) to form a reverse tone with a taper profile. The formation of the shallow trench isolation described includes a pad layer, and a silicon nitride layer formed-on a semiconductor wafer. Trenches are created by photolithography and dry etching processes. An oxide layer is formed in the trenches for the purpose of isolation. A polysilicon layer or bottom anti-reflective coating is subsequently formed on the oxide layer. A plurality of openings are generated in the polysilicon or the BARC layer. An etching is used to etch the oxide layer, thereby forming a reverse tone having a taper profile. A Chemical Mechanical Polishing is performed to planarize the surface of a semiconductor wafer.

Abstract: An in-situ etching process for creating local interconnects in a semiconductor device includes using one etching tool to: etch through an organic, or inorganic BARC layer using O.sub.2 gas, or C.sub.2 F.sub.6 /O.sub.2 gases, respectively; a masked dielectric layer to a stop layer using a mixture of C.sub.4 F.sub.8, CH.sub.3 F and argon (Ar) gasses; etch away the mask layer using a mixture of O.sub.2 and Ar gasses; and, etch through the stop layer using a mixture of CH.sub.3 F gas and O.sub.2 gas. Remaining portions of the BARC layer, whether organic or inorganic, are also removed during the in-situ etching process using appropriate gases. The method then includes depositing conductive material within the openings that were etched to form local interconnects.

Abstract: A method of semiconductor fabrication which permits the creation of openings which have dimensions smaller than what may be achieved by conventional lithography. In an illustrative processing sequence, a pattern transfer material is deposited upon another material layer. The pattern transfer material is covered with photoresist which is subsequently patterned. With the patterned photoresist as a mask, the pattern transfer material is etched with a process which creates inward sloping walls. Then the pattern transfer material is used as a mask to etch the underlying material. The inward sloping walls of the pattern transfer material permit creation of an opening in the underlying material which is smaller than the corresponding opening in the photoresist. The method may also be used to create trenches or field oxides which have dimensions smaller than those achievable by lithography.

Abstract: A diode includes a semiconductor substrate of first conductivity type and including a surface having a doped portion of second conductivity type opposite the first conductivity type. In addition, a dielectric layer on the surface of the substrate extends over a first portion of the doped surface portion and leaves a second portion of the doped surface portion exposed. This dielectric layer includes a low-angle tapered portion having a thickness which increases as said tapered portion extends from the exposed doped surface portion of the substrate. In particular, the low-angle tapered portion of the dielectric layer may extend from the exposed portion of a surface at an angle of less than about 10.degree.. Furthermore, the diode may also include a conductive contact on the exposed portion of the substrate and a field plate extending from the conductive contact over a portion of the dielectric layer.

Abstract: A method for forming a gate with a tapered spacer is disclosed. The method includes forming a polysilicon layer on a substrate, and then forming a first oxide layer on the polysilicon layer. A photoresist layer is formed on the first oxide layer, where the photoresist layer defines a gate region, and then portions of the oxide layer and the polysilicon layer are removed using the photoresist layer as a mask, thereby forming a gate. A second oxide layer is formed on the substrate and the first oxide layer. Afterwards, the second oxide layer is isotropically etched so that the slope of the second oxide layer near the upper corners of the gate is reduced. Finally, the second oxide layer is anisotropically etched back to form spacers on the sidewalls of the gate.

Abstract: A metal film forming method by which a metal film having a desired pattern can be formed with good reproducibility and satisfactory precision. In a metal film forming method for forming a metal film into the desired pattern on a surface of an object by the lift-off method, a resist layer is laminated on the surface of the object, the resist layer is exposed to light with the desired pattern and it is developed. Radio frequency sputtering is then performed against the resist layer so that the opening is deformed into a shape which is suited for the lift-off process. A metal film is then laminated on the surfaces of the resist layer and the metal film forming object. Then the resist layer is subjected to lift-off processing, whereby the metal film can be formed with good precision and satisfactory reproducibility. In this way, such a metal film forming method can be realized that a metal film having the desired pattern can be formed with good reproducibility and satisfactory precision.

Abstract: A method of etching openings in a dielectric layer of a semiconductor device by utilizing a novel etchant gas system of sulfur hexafluoride/chlorine such that sloped sidewalls can be formed in the openings having a desired taper of between about 20.degree. and about 85.degree. for achieving improved step coverage and profile control of the TFT fabrication process.

Abstract: A method of etching an article having a substrate, an etchable film and a mask layer having a pattern formed therein includes the step of exposing the article to an etchant gas mixture which includes a halogen-containing gas and an inert gas. An etching profile is formed which is substantially smooth across an interface between the etchable film and the mask layer. The method is particularly useful in producing components of articles such as flat-panel displays.

Abstract: A method for forming a bottle shaped trench 20 in a semiconductor substrate 10 includes reactive ion etching a trench having a tapered top portion 25 in the semiconductor device and continuing to reactive ion etch while increasing the temperature of the semiconductor device to impart a reentrant profile 22 to the trench.

Abstract: A structure and a method for connecting multiple interconnect layers on an integrated circuit structure (10) using landed or non-landed vias. An integrated circuit structure (10) has an interconnect trace (11) formed over a surface. A dielectric layer (13) is formed over the integrated circuit structure (10) and a photoresist layer (14) having an opening in the area where a via is desired is formed on the dielectric layer (13). The dielectric layer (13) is isotropically etched in an upper portion (16) through the opening in the photoresist layer (14) and then anisotropically etched to expose the interconnect trace (11). The photoresist layer (14) is removed and the dielectric layer (13) subjected to a high pressure sputter etch for smoothing the surfaces of the via opening and for filling voids (18) in the dielectric layer (13).

Abstract: A shallow trench isolation structure and method for forming such structure. In one embodiment, the semiconductor device isolating structure of the present invention includes a trench formed into a semiconductor substrate. A cross-section of the trench has a first sidewall sloping inwardly towards the center of a substantially planar bottom surface, and a second sidewall sloping inwardly towards the center of the substantially planar bottom surface. Additionally, a cross section of the trench has a first rounded bottom trench corner at an interface of the first sidewall and the substantially planar bottom surface, and a second rounded bottom trench corner at an interface of the second sidewall and the substantially planar bottom surface.

Abstract: A method of providing isolation structure in a semiconductor device having a shallow trench with a rounded top corner is provided for preventing stress centralization as well as current leakage of a device.

Abstract: A process for anisotropically etching a tungsten silicide or tungsten polycide structure. If the silicide/polycide film has an overlying oxide layer, the insulating layer is removed by a gas mixture composed of CHF.sub.3 and C.sub.2 F.sub.6. The WSi.sub.x silicide layer is then etched in a reactive ion etch using a gas mixture formed from Cl.sub.2 and C.sub.2 F.sub.6, with sufficient O.sub.2 added to control polymer formation and prevent undercutting of the silicide. The polysilicon layer is then etched using a gas mixture formed from Cl.sub.2 and C.sub.2 F.sub.6. The result is a highly anisotropic etch process which preserves the critical dimension of the etched structures. The etch parameters may be varied to produce a tapered sidewall profile for use in the formation of butted contacts without the need for a contact mask.

Abstract: Ordinary anisotropic etching is performed up to a depth (d1) while anisotropic etching is performed to form an inward taper from the depth (d1) by changing etching conditions such as components in a vapor phase and the temperature of a silicon substrate (1), thereby forming a groove (20). Thereafter silicon is epitaxially grown in the groove (20), thereby forming an epitaxial silicon layer (4). An NMOS transistor is formed on an upper layer part of the epitaxial silicon layer (4). At this time, the taper of the groove (20) is located under a part of an n.sup.+ layer (8) forming the NMOS transistor. Thus, a method of fabricating a semiconductor device capable of performing element isolation with neither halation nor formation of bird's beak in fabrication while minimizing a leakage current flowing across elements is obtained.

Abstract: A method in a substrate processing chamber for forming a conductive feature by etching through a conductive layer disposed above a semiconductor substrate. The method includes etching at least partially through the conductive layer using a first etch recipe to form a top portion of the conductive feature. The method further includes thereafter etching at least partially through a remaining thickness of the conductive layer using a second etch recipe different from the first etch recipe to form a bottom portion of the conductive feature. The bottom portion is disposed below the top portion. The second etch recipe is configured to yield a sloped etch foot in the bottom portion of the conductive feature.

Abstract: A method for forming a contact hole for a semiconductor device includes forming an insulation layer on a substrate and forming a photoresist film pattern on the insulation layer and exposing a portion of the insulation layer corresponding to the photoresist film pattern. The insulation layer is etched using the photoresist film pattern as a mask using a high density plasma etcher of an inductively coupled plasma type. The photoresist film is removed to form a contact hole having a sloped side wall.

Abstract: The present invention describes a method for rounding the top corners of a sub-micron trench in a semiconductor device directly after trench formation. In one embodiment of the present invention the etch process uses an etchant made up of a carbon-fluorine gas, an argon gas, and a nitrogen gas. The combination of gases enables the rounding of the top corners of the trench directly after the trench is formed. The combination of the carbon-fluorine and nitrogen gases etch back the silicon nitride and stress relief oxide layers in order to expose the top corners of the trench. As the top corners of the substrate are exposed the nitrogen and argon gases sputter the top corners rounding them as the etch process completes the trench.

Abstract: A laminated structure formed by alternately laminating a silicon film and a silicon oxide film is successively etched in the same chamber. Two groups are selected from groups A, B, and C, the group A including NF.sub.3, CF.sub.4, and SF.sub.6, the group B including CO, CHF.sub.3, CH.sub.2 F.sub.2, C.sub.2 F.sub.6, C.sub.3 F.sub.8, and C.sub.4 F.sub.8, and the group C including Cl.sub.2, HBr, HCl and Br.sub.2. The laminated structure is etched by successively etching one of the silicon film and the silicon oxide film by a combination of gases having a first mixture ratio and the other by the combination of gases having a second mixture ratio different from the first mixture ratio, the combination of gases including at least one kind of gas selected from one group of the selected two groups and at least one kind of gas selected from the other group. A technology of manufacturing a semiconductor device is provided which can etch an alternate laminate efficiently with a simple system.

Abstract: Defect density of amorphous silicon layers is increased from the lowest layer toward the highest layer by controlling one of or both of the pressure of gaseous mixture containing silane and hydrogen and the flow rate of the hydrogen, and a dry etching tapers both end portions of the amorphous silicon layers so as to improve the step coverage of a metal layer formed into source and drain electrodes.

Abstract: A sacrificial oxide etching solution of carboxylic acid and HF having a high etch selectivity for silicon oxide relative to polysilicon, metal, and nitride. The solution is useful in the fabrication of microstructures having integrated electronics on the same chip. A carboxylic acid anhydride can be added to this solution to substantially remove all free water so that the etch selectivity to metal is improved. One specific solution is formed by mixing acetic acid, acetic anhydride, and aqueous HF.

Abstract: The present invention is a method for forming a shallow trench with tapered profile and round corners for the application of shallow trench isolation (STI). This invention utilizes a multiple-step dry etching process with reduced RF power and increased pressure to etch a shallow trench. This takes advantage of different degree of polymer deposition in different steps by varing the pressure and the RF power. Thus, a shallow trench with tapered profile and round corners is achieved.

Abstract: A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and second conditions include the presence or absence of a deposit film, or the presence, absence or shape of a taper angle. Various parameters for controlling the first and second conditions are contemplated.