Including Change In Etch Influencing Parameter (e.g., Energizing Power, Etchant Composition, Temperature, Etc.) Patents (Class 438/714)
  • Patent number: 11120974
    Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Tung-Wen Cheng, Che-Cheng Chang, Jr-Jung Lin, Chih-Han Lin
  • Patent number: 10964527
    Abstract: Methods for removing residuals after a selective deposition process are provided. In one embodiment, the method includes performing a selective deposition process to form a metal containing dielectric material at a first location of a substrate and performing a residual removal process to remove residuals from a second location of the substrate.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: March 30, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Jong Mun Kim, Biao Liu, Cheng Pan, Erica Chen, Chentsau Ying, Srinivas Nemani, Ellie Yieh
  • Patent number: 10947110
    Abstract: The present invention provides a manufacturing method for MEMS structure. The method includes steps of: S1: providing a substrate, including a structural layer and a silicon-based layer overlapped with the structural layer; S2: carrying out a main etching process for etching out a cavity hole from an end of the silicon-based layer, which is far away from the structural layer, in a direction toward the structural layer until the cavity hole contacts the structural layer; and S3: carrying out an over-etching process for deepening the cavity hole and control an included angle ? between a side wall of the cavity hole and the structural layer to be larger than 10° but smaller than 90°. The invention also provides a MEMS structural and a MEMS microphone manufactured by the method.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: March 16, 2021
    Assignee: AAC Technologies Pte. Ltd.
    Inventors: Lieng Loo, Shaoquan Wang, Xiaohui Zhong, Kahkeen Lai
  • Patent number: 10921616
    Abstract: An optoelectronic device and method of making the same. The device comprising: a substrate; an epitaxial crystalline cladding layer, on top of the substrate; and an optically active region, above the epitaxial crystalline cladding layer; wherein the epitaxial crystalline cladding layer has a refractive index which is less than a refractive index of the optically active region, such that the optical power of the optoelectronic device is confined to the optically active region.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: February 16, 2021
    Assignee: Rockley Photonics Limited
    Inventors: Guomin Yu, Hooman Abediasl, Damiana Lerose, Amit Singh Nagra, Pradeep Srinivasan, Haydn Jones
  • Patent number: 10847349
    Abstract: A semiconductor manufacturing method and semiconductor manufacturing tool for performing the same are disclosed. The semiconductor manufacturing tool includes a plasma chamber, a mounting platform disposed within the plasma chamber, a focus ring disposed within the plasma chamber, and at least one actuator mechanically coupled to the focus ring and configured to move the focus ring vertically. The actuator is configured to move the focus ring vertically when a plasma is present in the plasma chamber.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chi Lin, Yi-Wei Chiu, Hung Jui Chang, Chin-Hsing Lin
  • Patent number: 10790152
    Abstract: In a method for etching a multilayer film of a target object by using a plasma processing apparatus, the multilayer film of the target object includes a layer made of a metal magnetic material and a mask is provided on the multilayer film. The multilayer film is etched in a state where a pressure in a processing chamber of the plasma processing apparatus is set to a first pressure that is a relatively high pressure. Subsequently, the multilayer film is further etched in a state where the pressure in the processing chamber is set to a second pressure lower than the first pressure.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: September 29, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takuya Kubo, Song yun Kang, Tamotsu Morimoto
  • Patent number: 10707139
    Abstract: An etching method for an IC is provided. The etching method includes retrieving processing data including a pattern-density and at least one etching parameter of an etching process for a semiconductor device; determining end point time by consulting a table which records historical information of a plurality of PDs, the etching parameter and the EP time; compensating for the PD and the EP time by adjusting the etching parameter to perform the etching process; and performing the etching process on another semiconductor device based on the adjusted etching parameter, the PD and the EP time to manufacture the IC.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Sheng Lien, Shih-Ta Yu
  • Patent number: 10699944
    Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Jou Lian, Kuo-Bin Huang, Neng-Jye Yang, Li-Min Chen
  • Patent number: 10692701
    Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Tung-Wen Cheng, Che-Cheng Chang, Jr-Jung Lin, Chih-Han Lin
  • Patent number: 10665431
    Abstract: A method for performing a process on a target in a chamber. A gas discharge unit includes a first space having a discharge hole for discharging a first gas, a second space having a discharge hole for discharging a second gas and a third space having a discharge hole for discharging a gas generated between the first and second spaces. A distribution unit includes a first distribution pipe communicating with the first space, a second distribution pipe communicating with the second space and a third distribution pipe communicating with the third space. A valve group includes a first valve opened or closed to the first distribution pipe and a second valve opened or closed to the second distribution pipe. The method includes switching, without mixing the first gas and the second gas, the gas discharged from the discharge hole in the third space by opening or closing the valve group.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: May 26, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazuyuki Tezuka, Kenichi Kato, Atsushi Sawachi, Takamichi Kikuchi, Takanori Mimura
  • Patent number: 10658213
    Abstract: A storage facility includes N accommodating sections, where N is a positive integer, M main pipes through which an inert gas flows, where M is a positive integer of 2?M<N, M flow control devices, M branch pipe groups, and a plurality of switching valves. Each branch pipe group includes N branch pipes, and the switching valves are respectively provided on the branch pipes included in at least (M?1) of the branch pipe groups. Each flow control device is configured to control the flow rate of the inert gas flowing through the main pipe to which this flow control device is connected, based on a flow-through pipe count, which is the number of the branch pipes for which the flow of the inert gas is not blocked by the switching valve, out of the N branch pipes of the branch pipe group that corresponds to this main pipe.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 19, 2020
    Assignee: Daifuku Co., Ltd.
    Inventors: Takeshi Abe, Tadahiro Yoshimoto
  • Patent number: 10615257
    Abstract: A semiconductor device includes a first type nanosheet device having a first plurality of nanosheet portions alternately stacked with a first plurality of work function metal layers on a substrate, and a second type nanosheet device having a second plurality of nanosheet portions alternately stacked with a second plurality of work function metal layers on the substrate. The second type nanosheet device is spaced apart from the first type nanosheet device. The semiconductor device also includes a dielectric layer disposed in the space between the first and second type nanosheet devices. The first and second plurality of work function metal layers are directly disposed on the dielectric layer, and bottom surfaces of the directly disposed first and second plurality of work function metal layers are co-planar with each other.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Wei Wang, Kevin W. Brew
  • Patent number: 10559475
    Abstract: A method for performing atomic layer etching (ALE) on a substrate is provided, including the following operations: performing a surface modification operation on a substrate surface, the surface modification operation configured to convert at least one monolayer of the substrate surface to a modified layer, wherein a bias voltage is applied during the surface modification operation, the bias voltage configured to control a depth of the substrate surface that is converted by the surface modification operation; performing a removal operation on the substrate surface, the removal operation configured to remove at least a portion of the modified layer from the substrate surface, wherein removing the portion of the modified layer includes applying thermal energy to effect desorption of the portion of the modified layer. A plasma treatment can be performed to remove residues from the substrate surface following the removal operation.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: February 11, 2020
    Assignee: Lam Research Corporation
    Inventors: Andreas Fischer, Thorsten Lill, Richard Janek
  • Patent number: 10418254
    Abstract: In an etching method of etching a tungsten film, the method is provided to execute a generating a surface reaction layer on a tungsten film that is formed on a surface of a base material by supplying a reactive species including fluorine which is generated in plasma onto the base material for a first predetermined time in a state where the base material of which the tungsten film is formed on at least a portion of the surface is cooled to a melting point temperature or lower of a tungsten fluoride, and a removing the surface reaction layer that is generated on the tungsten film by heating the base material of which the surface reaction layer is generated on the tungsten film to a boiling point temperature or higher of the tungsten fluoride for a second predetermined time.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 17, 2019
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Kazunori Shinoda, Naoyuki Kofuji, Hiroyuki Kobayashi, Nobuya Miyoshi, Kohei Kawamura, Masaru Izawa, Kenji Ishikawa, Masaru Hori
  • Patent number: 10410833
    Abstract: The present invention concerns a method comprising the steps of: introducing a substrate comprising a surface to be coated in a low-pressure reaction chamber; exposing said surface to a plasma during a treatment period within said reaction chamber; ensuring a stable plasma ignition by applying a power input, characterized in that the power input is continuously strictly higher than zero Watt (W) during said treatment period and comprises at least a lower limit power and at least an upper limit power strictly larger than said lower limit power, thereby obtaining a substrate with a coated surface. The present invention further concerns an apparatus for treating a substrate with a low-pressure plasma process and a substrate treated as such.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: September 10, 2019
    Assignee: Europlasma NV
    Inventors: Filip Legein, Eva Rogge, Marc Sercu
  • Patent number: 10312079
    Abstract: An etching method includes: disposing a target substrate which includes silicon and silicon-germanium in a chamber; supplying the chamber with processing gas which comprises H2 gas and Ar gas in an excited state; and selectively etching the silicon with respect to the silicon-germanium by the processing gas which is in the excited state. Due to this configuration, silicon can be etched, with high selectivity, with respect to the silicon-germanium.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 4, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koji Takeya, Kazuaki Nishimura, Nobuhiro Takahashi, Junichiro Matsunaga
  • Patent number: 10128085
    Abstract: A method of plasma etching includes an etching process that generates plasma from a process gas that includes fluorocarbon by using first high frequency power output by a first high frequency power source, and by the generated plasma, etches a low-k film with a metal-containing film as a mask. In the etching process, the first high frequency power is intermittently applied.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: November 13, 2018
    Assignee: Tokyo Electron Limited
    Inventor: Toshiharu Wada
  • Patent number: 9997366
    Abstract: A method for ion-assisted etching a stack of alternating silicon oxide and silicon nitride layers in an etch chamber is provided. An etch gas comprising a fluorine component, helium, and a fluorohydrocarbon or hydrocarbon is flowed into the etch chamber. The gas is formed into an in-situ plasma in the etch chamber. A bias of about 10 to about 100 volts is provided to accelerate helium ions to the stack and activate a surface of the stack to form an activated surface for ion-assisted etching, wherein the in-situ plasma etches the activated surface of the stack.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: June 12, 2018
    Assignee: Lam Research Corporation
    Inventors: Zhongkui Tan, Hua Xiang, Wenbing Hu, Qing Xu, Qian Fu
  • Patent number: 9960016
    Abstract: In a plasma processing method in which multiple cycles, each of which includes a first stage of generating plasma of a first processing gas containing a first gas and a second stage of generating plasma of a second processing gas containing the first gas and a second gas, are performed, a time difference between a start time point of a time period during which the second stage is performed and a start time point of an output of the second gas from a gas supply system is decided automatically according to a recipe. A delay time corresponding to flow rates of the first gas and the second gas in the second stage is specified from a function or a table. The output of the second gas is begun prior to the start time point of the second stage by a time difference set based on the delay time.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: May 1, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kumiko Ono, Hiroshi Tsujimoto, Koichi Nagami
  • Patent number: 9905431
    Abstract: In the present invention, a dry etching method for plasma etching a second laminated film in which a first laminated film in which a silicon-containing film and a silicon dioxide film are laminated is laminated in plurality and an inorganic film arranged over the second laminated film, includes etching the inorganic film and the second laminated film by a mixed gas of an NF3 gas and a CH3F gas.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: February 27, 2018
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Satoshi Terakura, Masahito Mori, Takao Arase, Ryuta Machida
  • Patent number: 9872373
    Abstract: Methods of operating a plasma enhanced substrate processing system using multi-level pulsed RF power are provided herein. In some embodiments, a method of operating a plasma enhanced substrate processing system using multi-level pulsed RF power includes providing a first multi-level RF power waveform to a process chamber, the first multi-level RF power waveform having at least a first power level, a second power level, and a third power level, providing, after a first delay period, a second multi-level RF power waveform to the process chamber, the second multi-level RF power waveform having at least a first power level, a second power level, and a third power level, and processing the substrate using the first multi-level RF power waveform and the second multi-level RF power waveform to produce a features on the substrate have an aspect ratio of greater than 60:1 while maintaining an etch rate of greater than 170 nm/min.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: January 16, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Daisuke Shimizu, Wonseok Lee, Katsumasa Kawasaki, Li Ling, Justin Phi, Kevin Choi
  • Patent number: 9852922
    Abstract: A plasma etching method includes: mounting a target substrate on a first electrode which is provided to be parallel with a second electrode with a preset gap within a processing chamber, a base material of the second electrode containing silicon or SiC; generating plasma of a fluorocarbon-based etching gas in a processing space; applying a low frequency AC power or a high frequency AC power having a frequency, which an ion in the plasma is allowed to follow, to the second electrode; and increasing an effective voltage value of the AC power to enhance sputtering at the second electrode such that silicon sputtered from the base material reacts with fluorine radicals generated from the fluorocarbon-based etching gas to produce a reaction product of SiF4, to irradiate electrons generated near the second electrode to the target substrate and to increase a plasma potential near a sidewall of the processing chamber.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: December 26, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hikaru Watanabe, Masanobu Honda
  • Patent number: 9842743
    Abstract: A method of etching a shallow trench is disclosed in the present invention. By removing the photoresist layer immediately at the end point of the hard mask layer etching and further using the improved process conditions etch the top of the substrate at the same time of the hard mask layer over-etching, such as a lower bias power, a higher pressure and a bigger polymer gases flow rate, the present invention has formed a smooth morphology on the top of the shallow trench. Therefore, the sharp corner appeared in the prior art is avoided by changing the start point of the silicon substrate etching, so as to fundamentally eliminate the leakage current caused by the sharp corner.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: December 12, 2017
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Jin Xu, Zaifeng Tang, Minjie Chen, Yu Ren, Yukun Lv
  • Patent number: 9818930
    Abstract: A support structure includes an internal cavity. An elastic membrane extends to divide the internal cavity into a first chamber and a second chamber. The elastic membrane includes a nanometric-sized pin hole extending there through to interconnect the first chamber to the second chamber. The elastic membrane is formed of a first electrode film and a second electrode film separated by a piezo insulating film. Electrical connection leads are provided to support application of a bias current to the first and second electrode films of the elastic membrane. In response to an applied bias current, the elastic membrane deforms by bending in a direction towards one of the first and second chambers so as to produce an increase in a diameter of the pin hole.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: November 14, 2017
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John Hongguang Zhang
  • Patent number: 9761489
    Abstract: A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: September 12, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bencherki Mebarki, Huixiong Dai, Yongmei Chen, He Ren, Mehul Naik
  • Patent number: 9738511
    Abstract: A MEMS (microelectromechanical systems) structure comprises a MEMS wafer. A MEMS wafer includes a cap with cavities bonded to a structural layer through a dielectric layer disposed between the cap and the structural layer. Unique configurations of MEMS devices and methods of providing such are set forth which provide for, in part, creating rounded, scalloped or chamfered MEMS profiles by shaping the etch mask photoresist reflow, by using a multi-step deep reactive ion etch (DRIE) with different etch characteristics, or by etching after DRIE.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: August 22, 2017
    Assignee: INVENSENSE, INC.
    Inventors: Jongwoo Shin, Kirt Reed Williams, Cerina Zhang, Kuolung (Dino) Lei
  • Patent number: 9607874
    Abstract: A plasma processing apparatus includes a stage in a processing chamber where plasma is formed, a wafer to be processed, and an electrode arranged at an upper part of the stage and supplied with power to electrostatically attract and hold the wafer on the stage, and consecutively processing a plurality of wafers one by one. There are plural processing steps of conducting processing using the plasma under different conditions and there are plural periods when formation of plasma is stopped between the processing steps. An inner wall of the processing chamber is coated before starting the processing of any wafer, and voltage supplied to the electrode is changed according to a balance of respective polarities of particles floating and charged in the processing chamber in each period when formation of plasma is stopped.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: March 28, 2017
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Hiroyuki Kobayashi, Tomoyuki Tamura, Masaki Ishiguro, Shigeru Shirayone, Kazuyuki Ikenaga, Makoto Nawata
  • Patent number: 9570301
    Abstract: A process for fabricating an integrated circuit is provided. The process includes providing a substrate and forming a hard mask on the substrate. The hard mask may be formed by atomic-layer deposition (ALD) or molecular-layer deposition (MLD). The process also includes disposing an exposure mask over the hard mask and exposing the exposure mask to a patterning particle to pattern a gap in the hard mask. The patterning particle may be, for example, a photon or a charged particle.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: February 14, 2017
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Kuen-Yu Tsai, Miin-Jang Chen, Si-Chen Lee
  • Patent number: 9564520
    Abstract: A method of forming a semiconductor device is disclosed. A sacrificial oxide layer is formed on a substrate having first and second areas. Using a photoresist mask exposing the first area and covering the second area as a mask layer, by a wet etching process, the sacrificial oxide layer in the first area and an edge portion of the sacrificial oxide layer in the second area are simultaneously removed, wherein the sacrificial oxide layer remained in the second area has a sidewall with a slope smaller than 40 degrees. An oxide-nitride-oxide (ONO) layer is formed over the first and second areas. The sacrificial oxide layer and the ONO layer formed thereon in the second area are removed, so that the ONO layer remained in the first area forms a first gate insulating layer in the first area. A second gate insulating layer is formed in the second area.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 7, 2017
    Assignee: United Microelectronics Corp.
    Inventor: Tzu-Ping Chen
  • Patent number: 9520302
    Abstract: A method of processing a substrate includes depositing an oxide material on a substrate having a first region, a second region and a plurality of features, wherein the first region has a high feature density and the second region has a low feature density; and controlling a ratio of an etch rate of the oxide material in the first region to an etch rate of the oxide material in the second region by forming an ammonium hexafluorosilicate ((NH4)2SiF6) layer having a first thickness atop the oxide material in the first region and having a second thickness atop the oxide material in the second region.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: December 13, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jungmin Ko, Sean Kang, Kwang-Soo Kim, Olivier Luere
  • Patent number: 9437450
    Abstract: In a plasma etching method, with respect to a substrate to be processed, which has a base layer, a silicon oxide film, and an etching mask formed in this order, the etching mask having an etching pattern formed thereon and being formed of polysilicon, a silicon-containing deposit is deposited on a surface of the etching mask using a plasma generated from a processing gas, while applying a negative direct current voltage to an upper electrode formed of silicon. Furthermore, in the plasma etching method, the silicon oxide film is etched using plasma generated from a first CF-based gas using, as a mask, the etching mask having the silicon-containing deposit deposited thereon.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: September 6, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Tetsuro Kikuchi
  • Patent number: 9419211
    Abstract: A gas for an etching process and a treatment process of a metal stacked film in which an insulating layer is interposed between two layers of magnetic materials can be optimized. An etching method of etching a multilayered film including a metal stacked film in which an insulating layer is interposed between a first magnetic layer and a second magnetic layer includes etching the metal stacked film with plasma generated by supplying a gas containing at least C, O, and H into a processing chamber; and treating the metal stacked film with plasma generated by supplying a gas containing at least a CF4 gas into the processing chamber.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: August 16, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Eiichi Nishimura, Masato Kushibiki, Nao Koizumi, Takashi Sone, Fumiko Yamashita
  • Patent number: 9306019
    Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a layered fin overlying a substrate, where the layered fin includes an SiGe layer and an Si layer. The SiGe layer and the Si layer alternate along a height of the layered fin. A dummy gate is formed overlying the substrate and the layered fin, and a source and a drain area formed in contact with the layered fin. The dummy gate is removed to expose the SiGe layer and the Si layer, and the Si layer is removed to produce an SiGe nanowire. A high K dielectric layer that encases the SiGe nanowire between the source and the drain is formed, and a replacement metal gate is formed so that the replacement metal gate encases the high K dielectric layer and the SiGe nanowire between the source and drain.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: April 5, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Jing Wan, Guillaume Bouche, Andy Wei, Shao Ming Koh
  • Patent number: 9299579
    Abstract: An etching method of selectively etching a first region formed of silicon oxide with respect to a second region formed of silicon nitride includes: a process (a) and a process (b). In the process (a), a target object is exposed to plasma of a fluorocarbon gas and a thickness of a protective film on the second region is larger than a thickness of a protective film formed on the first region. In the process (b), the first region is etched by plasma of a fluorocarbon gas. In the process (a), a temperature of the target object is set to 60° C. or more to 250° C. or less.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: March 29, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Maju Tomura, Hikaru Watanabe, Takahiko Kato, Masanobu Honda
  • Patent number: 9275869
    Abstract: A method for etching a layer in a plasma chamber with an inner injection zone gas feed and an outer injection zone gas feed is provided. The layer is placed in the plasma chamber. A pulsed etch gas is provided from the inner injection zone gas feed at a first frequency, wherein flow of pulsed etch gas from the inner injection zone gas feed is ramped down to zero. The pulsed etch gas is provided from the outer injection zone gas feed at the first frequency and simultaneous with and out of phase with the pulsed etch gas from the inner injection zone gas feed. The etch gas is formed into a plasma to etch the layer, simultaneous with the providing the pulsed etch gas from the inner injection zone gas feed and providing the pulsed gas from the outer interjection zone gas feed.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: March 1, 2016
    Assignee: Lam Research Corporation
    Inventors: Saravanapriyan Sriraman, Alexander Paterson
  • Patent number: 9246071
    Abstract: The disclosure relates to a method for making a grating. The method includes the following steps. First, a substrate is provided. Second, a photoresist film is formed on a surface of the substrate. Third, a nano-pattern is formed on the photoresist film by nano-imprint lithography. Fourth, the photoresist film is etched to form a patterned photoresist layer. Fifth, a mask layer is covered on the patterned photoresist layer and the surface of the substrate exposed to the patterned photoresist layer. Sixth, the patterned photoresist layer and the mask layer thereon are removed to form a patterned mask layer. Seventh, the substrate is etched through the patterned mask layer by reactive ion etching, wherein etching gases includes carbon tetrafluoride, sulfur hexafluoride, and argon. Finally, the patterned mask layer is removed.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: January 26, 2016
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Zhen-Dong Zhu, Qun-Qing Li, Li-Hui Zhang, Mo Chen
  • Patent number: 9238870
    Abstract: A reactive ion etching (RIE) process comprising a chlorine source gas and an oxygen source gas with an atomic ratio of chlorine to oxygen in the plasma of at least 6 to 1 is used to etch chromium alloy films such as SiCr, SiCrC, SiCrO, SiCrCO, SiCrCN, SiCrON, SiCrCON, CrO, CrN, CrON, and NiCr for example. Additionally, a fluorine source may be added to the etch chemistry.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: January 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Abbas Ali
  • Patent number: 9214355
    Abstract: As device feature size shrinks, plasma induced damage is a major concern affecting micro-electronic and nano-electronic device fabrication. Pulsed plasmas are a means of mitigating the damages. However, in conventional standard etch chemistry, the etch rate for pulsed plasmas is reduced significantly resulting in a substantially decreased throughput of tech processes. A new etch chemistry is disclosed in the present invention to increase throughput in pulsed plasma applications driven mainly by the molecular radicals.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: December 15, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sebastian U. Engelmann, Nathan P. Marchack, Masahiro Nakamura
  • Patent number: 9208997
    Abstract: A method of etching a copper layer of a target object including, on the copper layer, a mask having a pattern to be transferred onto the copper layer is provided. The method includes etching the copper layer by using plasma of a first gas containing a hydrogen gas; and processing the target object by using plasma of a second gas containing a hydrogen gas and a gas (hereinafter, referred to as “deposition gas”) that is deposited on the target object. Further, the etching of the copper layer by using plasma of the first gas and the processing of the target object by using plasma of the second gas are repeated alternately.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: December 8, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Eiichi Nishimura, Masato Kushibiki, Takashi Sone, Akitaka Shimizu, Fumiko Yamashita
  • Patent number: 9202894
    Abstract: One method includes forming trenches that define a fin structure including a first layer of a first semiconductor material and a second layer of a second semiconductor material positioned above a substrate, performing at least one etching process that exposes opposing end surfaces of the first and second layers, performing at least one recess etching process that removes end portions of the first layer and defines a cavity on opposite ends of the first layer, performing an epitaxial deposition process that fills each of the cavities with a support structure including a third semiconductor material, and performing an etching process to selectively remove remaining portions of the recessed first layer relative to the second layer and the support structures, the end portions of the second layer and the support structures defining pillars on opposite ends of the fin structure.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: December 1, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Hui Zang
  • Patent number: 9159612
    Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 13, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Byoung-Gue Min, Sang Choon Ko, Jong-Won Lim, Hokyun Ahn, Hyung Sup Yoon, Jae Kyoung Mun, Eun Soo Nam
  • Patent number: 9147692
    Abstract: A method for forming separate narrow lines is described. A target layer is formed over a substrate. Base patterns are formed over the target layer. Target line patterns and connection patterns between the ends of the target line patterns are formed as spacers on the sidewalls of the base patterns. The base patterns are removed. The target line patterns and the connection patterns are transferred to the target layer to form target lines and connection segments between the ends of the target lines. At least a portion of each connection segment is removed to disconnect the target lines while other area of the substrate is subjected to a patterned removal treatment.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: September 29, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Chin-Cheng Yang
  • Patent number: 9139909
    Abstract: New and improved microwave plasma assisted reactors, for example chemical vapor deposition (MPCVD) reactors, are disclosed. The disclosed microwave plasma assisted reactors operate at pressures ranging from about 10 Torr to about 760 Torr. The disclosed microwave plasma assisted reactors include a movable lower sliding short and/or a reduced diameter conductive stage in a coaxial cavity of a plasma chamber. For a particular application, the lower sliding short position and/or the conductive stage diameter can be variably selected such that, relative to conventional reactors, the reactors can be tuned to operate over larger substrate areas, operate at higher pressures, and discharge absorbed power densities with increased diamond synthesis rates (carats per hour) and increased deposition uniformity.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: September 22, 2015
    Assignees: BOARD OF TRUSTEES OF MICHIGAN STATE UNIVERSITY, Fraunhofer USA
    Inventors: Jes Asmussen, Timothy Grotjohn, Donnie K. Reinhard, Thomas Schuelke, M. Kagan Yaran, Kadek W. Hemawan, Michael Becker, David King, Yajun Gu, Jing Lu
  • Patent number: 9129911
    Abstract: Boron-doped carbon-based hardmask etch processing is described. In an example, a method of patterning a film includes etching a boron-doped amorphous carbon layer with a plasma based on a combination of CH4/N2/O2 and a flourine-rich source such as, but not limited to, CF4, SF6 or C2F6.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: September 8, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Kenny Linh Doan, Jong Mun Kim, Daisuke Shimizu
  • Patent number: 9105585
    Abstract: An etching method can selectively etch a second region formed of silicon oxide in a target object with respect to a first region formed of silicon in the target object. The etching method includes (a) processing the target object with plasma of a first processing gas containing fluorocarbon and fluorohydrocarbon by generating the plasma of the first processing gas with a microwave, and (b) after the processing of the target object with the plasma of the first processing gas, processing the target object with plasma of a second processing gas containing fluorocarbon by generating the plasma of the second processing gas with the microwave.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: August 11, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hironori Matsuoka, Hiroto Ohtake, Kosuke Kariu
  • Patent number: 9087788
    Abstract: Various embodiments provide shallow trenches and fabrication methods. In an exemplary method, a semiconductor substrate can be provided. A mask layer can be provided on the semiconductor substrate. An etch-cleaning process can be performed. The etch-cleaning process can include etching the semiconductor substrate to form a shallow trench by one or more etching steps using the mask layer as an etch mask. The etch-cleaning process can further include performing a plasma cleaning process after each of the one or more etching steps. The plasma cleaning process can use a plasma that is electronegative.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: July 21, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Haiyang Zhang, Dongjiang Wang
  • Patent number: 9068265
    Abstract: Embodiments of the present invention provide a gas distribution plate assembly having protective elements for plasma processing. The gas distribution plate assembly includes a base plate having a front side and a backside, and a plurality of protective elements in direct contact with the base plate. The protective elements cover the front side of the base plate to protect the base plate from a plasma processing environment during use.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: June 30, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Dmitry Lubomirsky, Kartik Ramaswamy, Kallol Bera, Jennifer Sun
  • Patent number: 9064812
    Abstract: Embodiments of methods for etching a substrate include exposing the substrate to a first plasma formed from an inert gas; exposing the substrate to a second plasma formed from an oxygen-containing gas to form an oxide layer on a bottom and sides of a low aspect ratio feature and a high aspect ratio feature, wherein the oxide layer on the bottom of the low aspect ratio feature is thicker than on the bottom of the high aspect ratio feature; etching the oxide layer from the bottom of the low and high aspect ratio features with a third plasma to expose the bottom of the high aspect ratio feature while the bottom of the low aspect ratio feature remains covered; and exposing the substrate to a fourth plasma formed from a halogen-containing gas to etch the bottom of the low aspect ratio feature and the high aspect ratio feature.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: June 23, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jinsu Kim, Xiaosong Ji, Jinhan Choi, Ho Jeong Kim, Byungkook Kong, Hoon Sang Lee
  • Patent number: 9040427
    Abstract: A method of plasma etching a silicon carbide workpiece includes forming a mask on a surface of the silicon carbide workpiece, performing an initial plasma etch on the masked surface using a first set of process conditions, wherein the plasma is produced using an etchant gas mixture which includes i) oxygen and ii) at least one fluorine rich gas which is present in the etchant gas mixture at a volume ratio of less than 50%, and subsequently performing a bulk plasma etch process using a second set of process conditions which differ from the first set of process conditions.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: May 26, 2015
    Assignee: SPTS Technologies Limited
    Inventors: Huma Ashraf, Anthony Barker
  • Patent number: 9039909
    Abstract: There is provided a plasma etching method for forming a hole in a silicon oxide film formed on an etching stopper layer. The plasma etching method includes a main etching process for etching the silicon oxide film; and an etching process that is performed when at least a part of the etching stopper layer is exposed after the main etching process. The etching process includes a first etching process using a gaseous mixture of a C4F6 gas, an Ar gas and an O2 gas as the processing gas; and a second etching process using a gaseous mixture of a C4F8 gas, an Ar gas and an O2 gas or a gaseous mixture of a C3F8 gas, an Ar gas and an O2 gas as the processing gas. The first etching process and the second etching process are alternately performed plural times.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: May 26, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akira Nakagawa, Yuji Otsuka