Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures having a back-end-of-line (BEOL) single damascene (SD) top via spacer defined by pillar mandrels. In a non-limiting embodiment of the invention, a first conductive line is formed in a first dielectric layer. A mandrel is formed over the first conductive line and a spacer is formed on a sidewall of the mandrel. A portion of a second dielectric layer is recessed to expose a top surface of the spacer and a top surface of the mandrel and the mandrel is removed. The spacer prevents damage to the second dielectric layer while removing the mandrel. The mandrel is replaced with a conductive material. A first portion of the conductive material defines a via and a second portion of the conductive material defines a second conductive line. The via couples the first conductive line to the second conductive line.

Abstract: A semiconductor device structure includes a dielectric layer formed on a silicon substrate, an amorphous carbon layer (ACL) formed on the dielectric layer, and a charge dissipation layer formed between the ACL and the dielectric layer. The charge dissipation layer is formed from a material having a resistivity lower than the resistivity of the ACL. Methodologies to fabricate the semiconductor device structure are also disclosed and include forming the dielectric layer on the silicon substrate, forming the charge dissipation layer on the dielectric layer, and forming the ACL on the charge dissipation layer. Alternative semiconductor device structures and fabrication methodologies are also disclosed.

Abstract: Exemplary etching methods may include forming a plasma of a fluorine-containing precursor to produce plasma effluents. A first bias frequency may be applied while forming the plasma. The methods may include contacting a substrate housed in a processing region of a semiconductor processing chamber with the plasma effluents. The substrate may be or include a photomask. The methods may include etching a first layer of the photomask. Etching the first layer of the photomask may expose a second layer of the photomask. The methods may include adjusting the first bias frequency to a second bias frequency while maintaining the plasma of the fluorine-containing precursor. The methods may include etching the second layer of the photomask.

Abstract: A germanium-on-silicon photodetector is fabricated by forming a thin silicon oxide layer on a silicon layer, and then forming a silicon nitride layer on the silicon oxide layer. A nitride dry etch process is used to etch an opening through the silicon nitride layer (through a photoresist mask). The nitride dry etch is stopped on the thin silicon oxide layer, preventing damage to the underlying silicon layer. A wet etch is then performed through the opening in the silicon nitride layer to remove the exposed silicon oxide layer. The wet etch exposes (and cleans) a portion of the underlying silicon layer. High-quality germanium is epitaxially grown over the exposed portion of the silicon layer, thereby providing a germanium structure that forms the intrinsic region of a PIN photodiode.

Abstract: An etching method of forming, on a substrate having a base film; a stacked film in which a first film and a second film are alternately stacked on the base film; and a mask on the stacked film, a recess in the stacked film through the mask by using plasma includes preparing the substrate; and etching the stacked film until the recess of the stacked film reaches the base film by plasma formed from a gas containing hydrogen, fluorine and carbon, while maintaining a substrate temperature equal to or less than 15° C.

Abstract: Embodiments of the present disclosure generally relate to apparatus and methods for controlling an ion energy distribution during plasma processing. In an embodiment, the apparatus includes a substrate support that has a body having a substrate electrode for applying a substrate voltage to a substrate, and an edge ring electrode embedded for applying an edge ring voltage to an edge ring. The apparatus further includes a substrate voltage control circuit coupled to the substrate electrode, and an edge ring voltage control circuit coupled to the edge ring electrode. The substrate electrode, edge ring electrode, or both are coupled to a power module configured to actively control an energy distribution function width of ions reaching the substrate, edge ring, or both. Methods for controlling an energy distribution function width of ions during substrate processing are also described.

Abstract: A method involving determining an etch bias for a pattern to be etched using an etch step of a patterning process based on an etch bias model, the etch bias model including a formula having a variable associated with a spatial property of the pattern or with an etch plasma species concentration of the etch step, and including a mathematical term including a natural exponential function to the power of a parameter that is fitted or based on an etch time of the etch step; and adjusting the patterning process based on the determined etch bias.

Abstract: A method for forming a stair-step structure in a stack on a substrate is provided. The method comprises at least one stair step cycle. Each stair step cycle comprises trimming the mask and etching the stack. Etching the stack is provided in a plurality of cycles wherein each cycle comprises etching a SiO2 layer and etching a SiN layer. Etching a SiO2 layer comprises flowing a SiO2 etching gas into the plasma processing chamber, wherein the SiO2 etching gas comprises a hydrofluorocarbon, an inert bombardment gas, and at least one of SF6 and NF3, generating a plasma from the SiO2 etching gas, providing a bias, and stopping the SiO2 layer etch. The etching a SiN layer comprises flowing a SiN etching gas into the plasma processing chamber, comprising a hydrofluorocarbon and oxygen, generating a plasma from the SiN etching gas, providing a bias, and stopping the SiN layer etch.

Abstract: Disclosed are an apparatus for monitoring pulsed high-frequency power and a substrate processing apparatus including the same. The apparatus includes an attenuation module configured to attenuate a pulsed high-frequency power signal; a rectifier module configured to convert the pulsed high-frequency power signal into a direct current signal; and a detection module configured to detect a pulse parameter based on the direct current signal.

Abstract: In a disclosed inspection method, a substrate and an edge ring are placed on first and second regions, respectively. A first inspection circuit is connected to the substrate. The first inspection circuit has impedance. A second inspection circuit is connected to the edge ring. The second inspection circuit has impedance. A first electrical bias and a second electrical bias having a common bias frequency are applied to a first electrode in the first region and a second electrode in the second region, respectively. A voltage waveform of the substrate and a voltage waveform of the edge ring is acquired by using a waveform monitor.

Abstract: A method for processing a substrate in a plasma chamber is provided. The method includes providing a substrate on which an underlying layer to be etched and a mask are formed. The method further includes forming a protective film on the mask. The method further includes performing an anisotropic deposition to selectively form a deposition layer on a top portion of the mask.

Abstract: An etching method includes: providing, on a stage, a substrate including an etching film containing a silicon oxide film, and a mask formed on the etching film; setting a temperature of the stage to be 0° C. or less; and generating plasma from a gas containing fluorine, nitrogen, and carbon, and having a ratio of the number of fluorine to the number of nitrogen (F/N) in a range of 0.5 to 10, thereby etching the silicon oxide film through the mask.

Abstract: In certain embodiments, a method for processing a semiconductor substrate includes receiving a semiconductor substrate that includes a film stack. The film stack includes first and second germanium-containing layers and a first silicon layer positioned between the first and second germanium-containing layers. The method includes selectively etching the first silicon layer by exposing the film stack to a plasma that includes fluorine agents and nitrogen agents. The plasma etches the first silicon layer, and causes a passivation layer to be formed on exposed surfaces of the first and second germanium-containing layers to inhibit etching of the first and second germanium-containing layers during exposure of the film stack to the plasma.

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, a plasma process combining etching and deposition processes is used to form a recess having a rounded corner shape in a cross section along the second direction.

Abstract: A semiconductor chip packaging method includes forming a bump on a wafer, forming a coating film covering the bump, laser grooving the wafer, plasma etching the wafer on which the laser grooving is performed, exposing the bump by removing the coating film covering the bump, fabricating a semiconductor die by performing mechanical sawing of the wafer, and packaging the semiconductor die.

Abstract: A plasma processing method includes performing a first plasma processing in a processing chamber in a first period, and performing a second plasma processing in the processing chamber during a second period continuously after the first period. In the first period and the second period, a first radio-frequency power for bias is continuously supplied to a lower electrode. A second radio-frequency power for plasma generation may be supplied as a pulsed radio-frequency power in a first partial period in each cycle of the first radio-frequency power in the first period. The second radio-frequency power may be supplied as a pulsed radio-frequency power in a second partial period in each cycle of the first radio-frequency power in the second period.

Abstract: Embodiments provide a non-plasma etch, such as a gas-phase and/or remote plasma etch, of titanium-containing material layers with tunable selectivity to other material layers. A substrate is received within a process chamber, and the substrate has exposed material layers including a titanium-containing material layer and at least one additional material layer. The additional material layer is selectively etched with respect to the titanium-containing material layer by exposing the substrate to a controlled environment including a halogen-containing gas. For one embodiment, the halogen-containing gas includes a fluorine-based gas. For one embodiment, the titanium-containing material layer is a titanium or a titanium nitride material layer. For one embodiment, the additional material layer includes tungsten, tungsten oxide, hafnium oxide, silicon oxide, silicon-germanium, silicon, silicon nitride, and/or aluminum oxide.

Abstract: A plasma processing method includes performing a first plasma processing in a processing chamber in a first period, and performing a second plasma processing in the chamber in a second period which is after the first period or following the first period. The first plasma processing and the second plasma processing are performed in a state where a substrate is disposed on a substrate support stage provided in the processing chamber. A sequence including the first plasma processing and the second plasma processing is performed a plurality of times.

Abstract: An electrostatic chuck includes a first ceramic member disk-shaped and having an annular step surface outside a circular wafer holding surface thereof, the annular step surface being at a lower level than the wafer holding surface, the first ceramic member having a volume resistivity that allows Coulomb force to be exerted; a first electrode embedded in the first ceramic member at a position facing the wafer holding surface; a second electrode disposed on the annular step surface of the first ceramic member, the second electrode being independent of the first electrode; and a second ceramic member having an annular shape and configured to cover the annular step surface having the second electrode thereon, the second ceramic member having a volume resistivity that allows Johnsen-Rahbek force to be exerted, wherein an upper surface of the second ceramic member is a focus ring holding surface on which a focus ring is placed.

Abstract: Systems and methods for processing a workpiece are provided. In one example, a method includes placing a workpiece on a workpiece support in a processing chamber. The workpiece has at least one material layer and at least one structure thereon. The method includes admitting a process gas into a plasma chamber, generating one or more species from the process gas, and filtering the one or more species to create a filtered mixture. The method further includes providing RF power to a bias electrode to generate a second mixture and exposing the workpiece to the second mixture to etch a least a portion of the material layer and to form a film on at least a portion of the material layer.

Abstract: The invention has been made in view of the above problems, and provides a plasma processing method capable of preventing etching shape abnormality in a plasma processing method for forming a mask layer of a polysilicon film. The invention relates to a plasma processing method for plasma-etching a polysilicon film, the plasma processing method comprising plasma-etching the polysilicon film using a mixed gas including a halogen gas, a fluorocarbon gas, an oxygen gas, and a carbonyl sulfide gas.

Abstract: Provided are a process gas supply apparatus which supplies a process gas onto a wafer to etch an oxide layer by dividing an edge zone into a first zone and a second zone located outside the first zone and dividing the second zone into a plurality of sub-zones and a wafer treatment system including the process gas supply apparatus.

Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.

Abstract: Methods for removing residuals after a selective deposition process are provided. In one embodiment, the method includes performing a selective deposition process to form a metal containing dielectric material at a first location of a substrate and performing a residual removal process to remove residuals from a second location of the substrate.

Abstract: The present invention provides a manufacturing method for MEMS structure. The method includes steps of: S1: providing a substrate, including a structural layer and a silicon-based layer overlapped with the structural layer; S2: carrying out a main etching process for etching out a cavity hole from an end of the silicon-based layer, which is far away from the structural layer, in a direction toward the structural layer until the cavity hole contacts the structural layer; and S3: carrying out an over-etching process for deepening the cavity hole and control an included angle ? between a side wall of the cavity hole and the structural layer to be larger than 10° but smaller than 90°. The invention also provides a MEMS structural and a MEMS microphone manufactured by the method.

Abstract: An optoelectronic device and method of making the same. The device comprising: a substrate; an epitaxial crystalline cladding layer, on top of the substrate; and an optically active region, above the epitaxial crystalline cladding layer; wherein the epitaxial crystalline cladding layer has a refractive index which is less than a refractive index of the optically active region, such that the optical power of the optoelectronic device is confined to the optically active region.

Abstract: A semiconductor manufacturing method and semiconductor manufacturing tool for performing the same are disclosed. The semiconductor manufacturing tool includes a plasma chamber, a mounting platform disposed within the plasma chamber, a focus ring disposed within the plasma chamber, and at least one actuator mechanically coupled to the focus ring and configured to move the focus ring vertically. The actuator is configured to move the focus ring vertically when a plasma is present in the plasma chamber.

Abstract: In a method for etching a multilayer film of a target object by using a plasma processing apparatus, the multilayer film of the target object includes a layer made of a metal magnetic material and a mask is provided on the multilayer film. The multilayer film is etched in a state where a pressure in a processing chamber of the plasma processing apparatus is set to a first pressure that is a relatively high pressure. Subsequently, the multilayer film is further etched in a state where the pressure in the processing chamber is set to a second pressure lower than the first pressure.

Abstract: An etching method for an IC is provided. The etching method includes retrieving processing data including a pattern-density and at least one etching parameter of an etching process for a semiconductor device; determining end point time by consulting a table which records historical information of a plurality of PDs, the etching parameter and the EP time; compensating for the PD and the EP time by adjusting the etching parameter to perform the etching process; and performing the etching process on another semiconductor device based on the adjusted etching parameter, the PD and the EP time to manufacture the IC.

Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.

Abstract: A method for performing a process on a target in a chamber. A gas discharge unit includes a first space having a discharge hole for discharging a first gas, a second space having a discharge hole for discharging a second gas and a third space having a discharge hole for discharging a gas generated between the first and second spaces. A distribution unit includes a first distribution pipe communicating with the first space, a second distribution pipe communicating with the second space and a third distribution pipe communicating with the third space. A valve group includes a first valve opened or closed to the first distribution pipe and a second valve opened or closed to the second distribution pipe. The method includes switching, without mixing the first gas and the second gas, the gas discharged from the discharge hole in the third space by opening or closing the valve group.

Abstract: A storage facility includes N accommodating sections, where N is a positive integer, M main pipes through which an inert gas flows, where M is a positive integer of 2?M<N, M flow control devices, M branch pipe groups, and a plurality of switching valves. Each branch pipe group includes N branch pipes, and the switching valves are respectively provided on the branch pipes included in at least (M?1) of the branch pipe groups. Each flow control device is configured to control the flow rate of the inert gas flowing through the main pipe to which this flow control device is connected, based on a flow-through pipe count, which is the number of the branch pipes for which the flow of the inert gas is not blocked by the switching valve, out of the N branch pipes of the branch pipe group that corresponds to this main pipe.

Abstract: A semiconductor device includes a first type nanosheet device having a first plurality of nanosheet portions alternately stacked with a first plurality of work function metal layers on a substrate, and a second type nanosheet device having a second plurality of nanosheet portions alternately stacked with a second plurality of work function metal layers on the substrate. The second type nanosheet device is spaced apart from the first type nanosheet device. The semiconductor device also includes a dielectric layer disposed in the space between the first and second type nanosheet devices. The first and second plurality of work function metal layers are directly disposed on the dielectric layer, and bottom surfaces of the directly disposed first and second plurality of work function metal layers are co-planar with each other.

Abstract: A method for performing atomic layer etching (ALE) on a substrate is provided, including the following operations: performing a surface modification operation on a substrate surface, the surface modification operation configured to convert at least one monolayer of the substrate surface to a modified layer, wherein a bias voltage is applied during the surface modification operation, the bias voltage configured to control a depth of the substrate surface that is converted by the surface modification operation; performing a removal operation on the substrate surface, the removal operation configured to remove at least a portion of the modified layer from the substrate surface, wherein removing the portion of the modified layer includes applying thermal energy to effect desorption of the portion of the modified layer. A plasma treatment can be performed to remove residues from the substrate surface following the removal operation.

Abstract: In an etching method of etching a tungsten film, the method is provided to execute a generating a surface reaction layer on a tungsten film that is formed on a surface of a base material by supplying a reactive species including fluorine which is generated in plasma onto the base material for a first predetermined time in a state where the base material of which the tungsten film is formed on at least a portion of the surface is cooled to a melting point temperature or lower of a tungsten fluoride, and a removing the surface reaction layer that is generated on the tungsten film by heating the base material of which the surface reaction layer is generated on the tungsten film to a boiling point temperature or higher of the tungsten fluoride for a second predetermined time.

Abstract: The present invention concerns a method comprising the steps of: introducing a substrate comprising a surface to be coated in a low-pressure reaction chamber; exposing said surface to a plasma during a treatment period within said reaction chamber; ensuring a stable plasma ignition by applying a power input, characterized in that the power input is continuously strictly higher than zero Watt (W) during said treatment period and comprises at least a lower limit power and at least an upper limit power strictly larger than said lower limit power, thereby obtaining a substrate with a coated surface. The present invention further concerns an apparatus for treating a substrate with a low-pressure plasma process and a substrate treated as such.

Abstract: An etching method includes: disposing a target substrate which includes silicon and silicon-germanium in a chamber; supplying the chamber with processing gas which comprises H2 gas and Ar gas in an excited state; and selectively etching the silicon with respect to the silicon-germanium by the processing gas which is in the excited state. Due to this configuration, silicon can be etched, with high selectivity, with respect to the silicon-germanium.

Abstract: A method of plasma etching includes an etching process that generates plasma from a process gas that includes fluorocarbon by using first high frequency power output by a first high frequency power source, and by the generated plasma, etches a low-k film with a metal-containing film as a mask. In the etching process, the first high frequency power is intermittently applied.

Abstract: A method for ion-assisted etching a stack of alternating silicon oxide and silicon nitride layers in an etch chamber is provided. An etch gas comprising a fluorine component, helium, and a fluorohydrocarbon or hydrocarbon is flowed into the etch chamber. The gas is formed into an in-situ plasma in the etch chamber. A bias of about 10 to about 100 volts is provided to accelerate helium ions to the stack and activate a surface of the stack to form an activated surface for ion-assisted etching, wherein the in-situ plasma etches the activated surface of the stack.

Abstract: In a plasma processing method in which multiple cycles, each of which includes a first stage of generating plasma of a first processing gas containing a first gas and a second stage of generating plasma of a second processing gas containing the first gas and a second gas, are performed, a time difference between a start time point of a time period during which the second stage is performed and a start time point of an output of the second gas from a gas supply system is decided automatically according to a recipe. A delay time corresponding to flow rates of the first gas and the second gas in the second stage is specified from a function or a table. The output of the second gas is begun prior to the start time point of the second stage by a time difference set based on the delay time.

Abstract: In the present invention, a dry etching method for plasma etching a second laminated film in which a first laminated film in which a silicon-containing film and a silicon dioxide film are laminated is laminated in plurality and an inorganic film arranged over the second laminated film, includes etching the inorganic film and the second laminated film by a mixed gas of an NF3 gas and a CH3F gas.

Abstract: Methods of operating a plasma enhanced substrate processing system using multi-level pulsed RF power are provided herein. In some embodiments, a method of operating a plasma enhanced substrate processing system using multi-level pulsed RF power includes providing a first multi-level RF power waveform to a process chamber, the first multi-level RF power waveform having at least a first power level, a second power level, and a third power level, providing, after a first delay period, a second multi-level RF power waveform to the process chamber, the second multi-level RF power waveform having at least a first power level, a second power level, and a third power level, and processing the substrate using the first multi-level RF power waveform and the second multi-level RF power waveform to produce a features on the substrate have an aspect ratio of greater than 60:1 while maintaining an etch rate of greater than 170 nm/min.

Abstract: A plasma etching method includes: mounting a target substrate on a first electrode which is provided to be parallel with a second electrode with a preset gap within a processing chamber, a base material of the second electrode containing silicon or SiC; generating plasma of a fluorocarbon-based etching gas in a processing space; applying a low frequency AC power or a high frequency AC power having a frequency, which an ion in the plasma is allowed to follow, to the second electrode; and increasing an effective voltage value of the AC power to enhance sputtering at the second electrode such that silicon sputtered from the base material reacts with fluorine radicals generated from the fluorocarbon-based etching gas to produce a reaction product of SiF4, to irradiate electrons generated near the second electrode to the target substrate and to increase a plasma potential near a sidewall of the processing chamber.

Abstract: A method of etching a shallow trench is disclosed in the present invention. By removing the photoresist layer immediately at the end point of the hard mask layer etching and further using the improved process conditions etch the top of the substrate at the same time of the hard mask layer over-etching, such as a lower bias power, a higher pressure and a bigger polymer gases flow rate, the present invention has formed a smooth morphology on the top of the shallow trench. Therefore, the sharp corner appeared in the prior art is avoided by changing the start point of the silicon substrate etching, so as to fundamentally eliminate the leakage current caused by the sharp corner.

Abstract: A support structure includes an internal cavity. An elastic membrane extends to divide the internal cavity into a first chamber and a second chamber. The elastic membrane includes a nanometric-sized pin hole extending there through to interconnect the first chamber to the second chamber. The elastic membrane is formed of a first electrode film and a second electrode film separated by a piezo insulating film. Electrical connection leads are provided to support application of a bias current to the first and second electrode films of the elastic membrane. In response to an applied bias current, the elastic membrane deforms by bending in a direction towards one of the first and second chambers so as to produce an increase in a diameter of the pin hole.

Abstract: A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.

Abstract: A MEMS (microelectromechanical systems) structure comprises a MEMS wafer. A MEMS wafer includes a cap with cavities bonded to a structural layer through a dielectric layer disposed between the cap and the structural layer. Unique configurations of MEMS devices and methods of providing such are set forth which provide for, in part, creating rounded, scalloped or chamfered MEMS profiles by shaping the etch mask photoresist reflow, by using a multi-step deep reactive ion etch (DRIE) with different etch characteristics, or by etching after DRIE.

Abstract: A plasma processing apparatus includes a stage in a processing chamber where plasma is formed, a wafer to be processed, and an electrode arranged at an upper part of the stage and supplied with power to electrostatically attract and hold the wafer on the stage, and consecutively processing a plurality of wafers one by one. There are plural processing steps of conducting processing using the plasma under different conditions and there are plural periods when formation of plasma is stopped between the processing steps. An inner wall of the processing chamber is coated before starting the processing of any wafer, and voltage supplied to the electrode is changed according to a balance of respective polarities of particles floating and charged in the processing chamber in each period when formation of plasma is stopped.

Abstract: A process for fabricating an integrated circuit is provided. The process includes providing a substrate and forming a hard mask on the substrate. The hard mask may be formed by atomic-layer deposition (ALD) or molecular-layer deposition (MLD). The process also includes disposing an exposure mask over the hard mask and exposing the exposure mask to a patterning particle to pattern a gap in the hard mask. The patterning particle may be, for example, a photon or a charged particle.