Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.

Abstract: Methods for processing a substrate are described herein. Methods can include positioning a substrate with an exposed surface comprising a silicon oxide layer in a processing chamber, biasing the substrate, treating the substrate to roughen a portion of the silicon oxide layer, heating the substrate to a first temperature, exposing the exposed surface of the substrate to a plasma comprising ammonium fluoride to form one or more volatile products while maintaining the first temperature, and heating the substrate to a second temperature, which is higher than the first temperature, to sublimate the volatile products.

Abstract: A semiconductor device manufacturing method includes a plasma etching step for etching an etching target film formed on a substrate accommodated in a processing chamber. In the plasma etching step, a processing gas including a gaseous mixture containing predetermined gases is supplied into the processing chamber, and a cycle including a first step in which a flow rate of at least one of the predetermined gases is set to a first value during a first time period and a second step in which the flow rate thereof is set to a second value that is different from the first value during a second time period is repeated consecutively at least three times without removing a plasma. The first time period and the second time period are set to about 1 to 15 seconds.

Abstract: Uniformity of a plasma process on a surface of a substrate is to be improved. In a plasma processing apparatus that processes a substrate by generating plasma from a processing gas introduced in a processing container, a ratio between an introducing amount of the processing gas introduced to a center portion of the substrate received in the processing container and an introducing amount of the processing gas introduced to a peripheral portion of the substrate received in the processing container is changed during a plasma process. Accordingly, a variation in an etching rate or the like between the center portion and the peripheral portion of the substrate may be reduced. Therefore, uniformity of the plasma process on the surface of the substrate is improved.

Abstract: A semiconductor processing method that can generate a hole with different diameters, comprising: providing first material and second material different from the first material; and utilizing a etching process to etch the first material and the second material to form a hole through the first material and the second material; wherein the etching process has different etching rates for the first material and the second material such that the hole have different diameters. A semiconductor structure corresponding to the above-mentioned method is also disclosed.

Abstract: Methods and apparatus for controlling microloading, such as within cell microloading between adjacent cells or isolated/dense microloading between areas of isolated or dense features during shallow trench isolation (STI) fabrication processes, or other trench fabrication processes, are provided herein. In some embodiments, a method for fabricating STI structures may include providing a substrate having a patterned mask layer formed thereon corresponding to one or more STI structures to be etched; etching the substrate through the patterned mask layer using a plasma formed from a process gas to form one or more STI structure recesses on the substrate; and pulsing the plasma for at least a portion of etching the substrate to control at least one of a depth or width of the one or more STI structure recesses.

Abstract: A method for processing a target object includes arranging a first electrode and a second electrode for supporting the target object in parallel to each other in a processing chamber and processing the target object supported by the second electrode by using a plasma of a processing gas supplied into the processing chamber, the plasma being generated between the first electrode and the second electrode by applying a high frequency power between the first electrode and the second electrode. The target object includes an organic film and a photoresist layer formed on the organic film. The processing gas contains H2 gas, and the organic film is etched by a plasma containing H2 by using the photoresist layer as a mask while applying a negative DC voltage to the first electrode.

Abstract: A method for etching features with different aspect ratios in an etch layer is provided. A plurality of cycles is provided wherein each cycle comprises a pre-etch transient conditioning of the etch layer, which provides a transient condition of the etch layer, wherein the transient condition has a duration and etching the etch layer for a duration, wherein the duration of the etching with respect to the duration of the transient condition is controlled to control etch aspect ratio dependence.

Abstract: A method of manufacturing a semiconductor device comprises placing a semiconductor substrate in an ashing chamber, the semiconductor substrate having a gate, a silicon nitride gate sidewall offset spacer or a silicon nitride gate sidewall pacer formed thereon, and a photo resist residue remaining on the semiconductor substrate, introducing a gas mixture including D2 or T2 into the ashing chamber, and ashing the photo resist residue using a plasma that is formed from the gas mixture. The gas mixture can include a deuterium gas or a tritium gas having a volume ratio ranging between about 1% and about 20%. Embodiments can reduce Si recess and the loss of silicon nitride thin film during ashing.

Abstract: A plasma etching method is provided for etching a semiconductor substrate with plasma using a metal mask that is patterned on the semiconductor substrate. The plasma etching method includes a first etching step of controlling a pressure within a chamber to a first pressure and etching the semiconductor substrate inside the chamber under the first pressure using a plasma generated from a fluorine-containing gas; and a second etching step to be performed after the first etching step, the second etching step including controlling the pressure within the chamber to a second pressure, which is higher than the first pressure, and etching the semiconductor substrate inside the chamber under the second pressure using the plasma generated from the fluorine-containing gas.

Abstract: An apparatus for etching a dielectric layer contained by a substrate is provided. An etch reactor comprises a top electrode and a bottom electrode. An etch gas source supplies an etch gas into the etch reactor. A first Radio Frequency (RF) source generates a first RF power with a first frequency and supplies the first RF power into the etch reactor, whereas the first frequency is between 100 kilo Hertz (kHz) and 600 kHz. A second RF source generates a second RF power with a second frequency and supplies the second RF power into the etch reactor, whereas the second frequency is at least 10 mega Hertz (MHz).

Abstract: A plasma processing apparatus includes a processing chamber which plasma-processes a sample, a first high-frequency power supply which supplies first high-frequency power for plasma generation to the processing chamber, a second high-frequency power supply which supplies second high-frequency power to a sample stage on which the sample is placed and a pulse generation device which generate first pulses for time-modulating the first high-frequency power and second pulses for time-modulating the second high-frequency power. The pulse generation device includes a control device which controls the first and second pulses so that frequency of the first pulses is higher than frequency of the second pulses and the on-period of the second pulse is contained in the on-period of the first pulse.

Abstract: A gas switching system for a gas distribution system for supplying different gas compositions to a chamber, such as a plasma processing chamber of a plasma processing apparatus, is provided. The chamber can include multiple zones, and the gas switching section can supply different gases to the multiple zones. The switching section can switch the flows of one or more gases, such that one gas can be supplied to the chamber while another gas can be supplied to a by-pass line, and then switch the gas flows.

Abstract: A method for opening a conformal layer at the bottom of a contact via on a substrate is described. The method includes providing a substrate having a first layer with a via pattern formed therein and a second layer conformally deposited on the first layer and within the via pattern to establish a contact via pattern characterized by an initial mid-critical dimension (CD). The method further includes etching through the second layer at the bottom of the contact via pattern to extend the contact via pattern through the second layer and form a contact via while retaining at least part of the second layer on the top surface of the first layer, the corner at the entrance to the via pattern, and the sidewalls of the via pattern, wherein the etching is performed by irradiating the substrate with a gas cluster ion beam (GCIB) according to a GCIB etching process.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method may comprise: forming a gate stack on a substrate; depositing a first dielectric layer and a second dielectric layer sequentially on the substrate and the gate stack; and etching the second dielectric layer and the first dielectric layer sequentially with an etching gas containing helium to form a second spacer and a first spacer, respectively. According to the method disclosed herein, a dual-layer complex spacer configuration is achieved, and two etching operations where the etching gas comprises the helium gas are performed. As a result, it is possible to reduce damages to the substrate and also to reduce the process complexity. Further, it is possible to optimize a threshold voltage, effectively reduce an EOT, and enhance a gate control capability and a driving current.

Abstract: Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 100° C. and 350° C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.

Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from a capping region of the gate structure and a substrate region on the substrate adjacent a base of the gate structure, while retaining a spacer sidewall positioned along a sidewall of the gate structure.

Abstract: Provided is an etching method capable of etching even a silicon film that is included in a multi-layered structure by using a resist film or an organic film as a mask, and also capable of integrally etching the silicon film and a silicon oxide film disposed under the silicon film. The etching method which etches the multi-layered structure including the silicon oxide film and the silicon film formed on the silicon oxide film, includes: integrally etching the silicon film and the silicon oxide film included in the multi-layered structure by using a resist film or an organic film as an etching mask and using an etching gas containing a CH2F2 gas as an etching gas, when the silicon film and the silicon oxide film in the multi-layered structure are etched.

Abstract: A plasma etching method includes supplying an etching gas containing an oxygen gas and a sulfur fluoride gas at a predetermined flow rate into a processing chamber that accommodates a processing substrate including a silicon layer and a resist layer, and etching the silicon layer with plasma generated from the etching gas using the resist layer as a mask. The plasma etching method further includes a first step of etching the silicon layer while a flow ratio of the oxygen gas to the sulfur fluoride gas is adjusted to a first flow ratio; a second step of etching the silicon layer while decreasing a flow rate of the oxygen gas to decrease the flow ratio to a second flow ratio, which is lower than the first flow ratio; and a third step of etching the silicon layer while the flow ratio is adjusted to the second flow ratio.

Abstract: In a method of vapor etching, a sample that includes a first layer atop of and in contact with a second layer which is atop of and in contact with a third layer, wherein at least the first and second layers are comprised of different materials. The sample is etched by a vapor etchant under first process conditions that cause at least a part of the first layer to be fully removed while leaving the third layer and the second layer underlying the removed part of the first layer substantially unetched. The sample is then etched by the same or a different vapor etchant under second process conditions that cause at least the part of the second layer exposed by the removal of the at least part of the first layer to be fully removed while leaving the third layer underlying the removed part of the second layer substantially unetched.

Abstract: The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer.

Abstract: A method for fabricating black silicon by using plasma immersion ion implantation is provided, which includes: putting a silicon wafer into a chamber of a black silicon fabrication apparatus; adjusting processing parameters of the black silicon fabrication apparatus to preset scales; generating plasmas in the chamber of the black silicon fabrication apparatus; implanting reactive ions among the plasmas into the silicon wafer, and forming the black silicon by means of the reaction of the reactive ions and the silicon wafer. The method can form the black silicon which has a strong light absorption property and is sensitive to light, and has advantages of high productivity, low cost and simple production process.

Abstract: A method of taper-etching a layer to be etched that is made of a dielectric material and has a top surface. The method includes the steps of: forming an etching mask with an opening on the top surface of the layer to be etched; and taper-etching a portion of the layer to be etched, the portion being exposed from the opening, by reactive ion etching so that a groove having two wall faces intersecting at a predetermined angle is formed in the layer to be etched. The step of taper-etching employs an etching gas containing a first gas contributing to the etching of the layer to be etched and a second gas contributing to the deposition of a sidewall protective film, and changes, during the step, the ratio of the flow rate of the second gas to the flow rate of the first gas so that the ratio increases.

Abstract: A plasma processing method for a plasma processing device is provided. The plasma processing device includes a reaction chamber, multiple Radio Frequency (RF) power supplies with different RF frequency outputs apply RF electric fields to the reaction chamber, the output of at least one pulse RF power supply has multiple output states, and the processing method includes a match frequency obtaining step and a pulse processing step. In the match frequency obtaining step, the output state of the pulse RF power supply is switched to make the reaction chamber have multiple impedances to simulate the impedances in the pulse processing step. The output frequencies of the variable frequency RF power supply are adjusted to match the simulated impedances. The adjusted output frequencies are stored as match frequencies. In the subsequent pulse processing step, the fast switched impedances are instantly matched by the stored match frequencies.

Abstract: In a method of manufacturing a semiconductor device, a substrate is loaded to a process chamber having, unit process sections in which unit processes are performed, respectively. The unit processes are performed on the substrate independently from one another at the unit process sections under a respective process pressure. The substrate sequentially undergoes the unit processes at the respective unit process section of the process chamber. Cleaning processes are individually performed to the unit process sections, respectively, when the substrate is transferred from each of the unit process sections and no substrate is positioned at the unit process sections. Accordingly, the process defects of the process units may be sufficiently prevented and the operation period of the manufacturing apparatus is sufficiently elongated.

Abstract: A process for cleaning a compound semiconductor wafer; the compound semiconductor wafer comprises, taking gallium arsenide (GaAs) as a representative, a group III-V compound semiconductor wafer. The process comprises the following steps: 1) treating the wafer with a mixture of dilute ammonia, hydrogen peroxide and water at a temperature not higher than 20° C.; 2) washing the wafer with deionized water; 3) treating the wafer with an oxidant; 4) washing the wafer with deionized water; 5) treating the wafer with a dilute acid solution or a dilute alkali solution; 6) washing the wafer with deionized water; and 7) drying the resulting wafer. The process can improve the cleanliness, micro-roughness and uniformity of the wafer surface.

Abstract: A method of etching a substrate is described. In one embodiment, the method includes preparing a mask layer having a pattern formed therein on or above at least a portion of a substrate, etching a feature pattern into the substrate from the pattern in the mask layer using a gas cluster ion beam (GCIB), and controlling a sidewall profile of the feature pattern etched into the substrate by adjusting a beam divergence of the GCIB.

Abstract: There is provided a substrate processing method capable of preventing the decrease in etching efficiency by positive ions and increasing the overall etching efficiency by using negative ions. The substrate processing method includes applying a plasma RF and a bias RF in the pattern of a pulse wave, respectively. The substrate processing method repeatedly performs the steps of: (3b) etching a substrate by positive ions in plasma by applying both the plasma RF and the bias RF; (3c) generating negative ions in a processing chamber by stopping the application of both the plasma RF and the bias RF; and (3a) attracting the negative ions to the substrate by applying the bias RF and stopping the application of the plasma RF. A duty ratio of the bias RF is set to be greater than a duty ratio of the plasma RF.

Abstract: A method for calibrating a high frequency measuring device so as to accurately measure plasma processing parameters within a chamber. A calibration parameter is calculated from a first set of three reference loads measured by a high frequency measurement device. A second calibration parameter is calculated from S parameters measured between a connection point where the high-frequency measuring device is connected and the inside of the chamber of a plasma processing device. A second set of three reference loads, which include the impedance previously calculated and encompass a range narrower than that encompassed by the first set of three reference loads, is measured with the reference loads in the chamber.

Abstract: A plasma etching method includes a preparation process for performing a plasma etching process using a processing gas including a first processing gas containing carbon (C) and fluorine (F), a ratio (C/F) of the first processing gas having a first value, and obtaining a residual amount of the mask layer corresponding to a variation point where a variation amount of the bowing CD is increased; a first plasma etching process using the processing gas including the first processing gas until a residual amount of the mask layer reaches the variation point; and a second plasma etching process performed after the first plasma etching process. The second plasma etching process is performed by using a processing gas including at least a second processing gas containing carbon (C) and fluorine (F), and a ratio (C/F) of the second processing gas is smaller than the first value.

Abstract: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.

Abstract: A display device and method for fabricating includes patterning a field shield dielectric layer to expose conductors and form a cavity over the conductors. InkJet printing a semiconductor material fills a portion of the cavity in contact with the conductors. An insulation material is deposited on the semiconductor material. A pixel pad is formed over the insulation material and the field shield dielectric layer. A pixel is formed which includes a thin film transistor with an ink jet printed semiconductor layer.

Abstract: Nano-sized materials and/or polysilicon are formed using heat generated from a micro-heater, the micro-heater may include a substrate, a heating element unit formed on the substrate, and a support structure formed between the substrate and the heating element unit. Two or more of the heating element units may be connected in series.

Abstract: A method for etching a substrate includes etching at least one first layer of the substrate with a non-uniform substrate temperature and etching at least one second layer of the substrate with uniform substrate temperatures.

Abstract: This invention is directed to form a homogeneous film in a via hole formed in a semiconductor device using Bosch process. The via hole that penetrates through a predetermined region in a semiconductor substrate is formed by etching the semiconductor substrate from one of its surface to the other by the Bosch process using a mask layer as a mask. Next, the mask layer is removed. Then, scallops are removed by dry etching to flatten a sidewall of the via hole. Following the above, an insulation film, a barrier layer and the like are formed homogeneously in the via hole.

Abstract: A method of etching or removing an organic hardmask overlying a low dielectric constant film in a lithographic process. The method includes providing a dielectric film having thereover an organic hardmask to be removed, the dielectric film having a dielectric constant no greater than about 4.0, introducing over the organic hardmask an ionizable gas comprising a mixture of hydrogen and an oxidizing gas, and applying energy to the mixture to create a plasma of the mixture. The method further includes contacting the organic hardmask with the plasma, with the organic hardmask being at a temperature in excess of 200° C., to remove the organic hardmask without substantially harming the underlying substrate.

Abstract: The present invention discloses a method of fabricating a semiconductor device. In the present invention, after the formation of a photo-resist mask on a substrate, the photo-resist is subjected to a plasma pre-treatment, and then etch is conducted. With the plasma pre-treatment, a line width roughness of a linear pattern of the photo-resist can be improved, and thus much better linear patterns can be formed on the substrate during the subsequent etching steps.

Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain\-inducing semiconductor material, superior uniformity may be achieved by using an implantation process so as to selectively modify the etch behavior of exposed portions of the active region. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility, while at the same time the dependence on pattern loading effect may be reduced. Consequently, a significantly reduced variability of transistor characteristics may be achieved.

Abstract: A method for controlling pulsed power that includes measuring a first pulse of power from a power amplifier to obtain data. The method also includes generating a first signal to adjust a second pulse of delivered power, the first signal correlated to the data to minimize a power difference between a power set point and a substantially stable portion of the second pulse. The method also includes generating a second signal to adjust the second pulse of delivered power, the second signal correlated to the data to minimize an amplitude difference between a peak of the second pulse and the substantially stable portion of the second pulse.

Abstract: Methods, systems, and computer programs are presented for semiconductor manufacturing are provided. One wafer processing apparatus includes: a top electrode; a bottom electrode; a first radio frequency (RF) power source; a second RF power source; a third RF power source; a fourth RF power source; and a switch. The first, second, and third power sources are coupled to the bottom electrode. Further, the switch is operable to be in one of a first position or a second position, where the first position causes the top electrode to be connected to ground, and the second position causes the top electrode to be connected to the fourth RF power source.

Abstract: Methods of patterning low-k dielectric films are described.

Abstract: A method of etching exposed silicon-and-nitrogen-containing material on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and an oxygen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon-and-nitrogen-containing material. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon-and-nitrogen-containing material from the exposed silicon-and-nitrogen-containing material regions while very slowly removing other exposed materials. The silicon-and-nitrogen-containing material selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate.

Abstract: The present invention is directed to post-deposition, wet etch processes for patterning AuSn solder material and devices fabricated using such processes. The processes can be applied to uniform AuSn layers to generate submicron patterning of thin AuSn layers having a wide variety of features. The use of multiple etching steps that alternate between different mixes of chemicals enables the etch to proceed effectively, and the same or similar processes can be used to etch under bump metallization. The processes are simple, cost-effective, do not contaminate equipment or tools, and are compatible with standard cleanroom fabrication processes.

Abstract: A method for etching on a semiconductors at the back end of line using reactive ion etching. The method comprises reduced pressure atmosphere and a mixture of gases at a specific flow rate ratio during plasma generation and etching. Plasma generation is induced by a source radio frequency and anisotropic etch performance is induced by a second bias radio frequency.

Abstract: The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a phosphorus-and-oxygen-containing compound therein. The etching composition can, for example, include one or both of ammonium hydroxide and tetra-methyl ammonium hydroxide. The invention also includes methods in which titanium-containing whiskers are removed from between titanium-containing capacitor electrodes. Such removal can be, for example, accomplished with an etch utilizing one or more of hydrofluoric acid, ammonium fluoride, nitric acid and hydrogen peroxide.

Abstract: A method for etching features into an etch layer in a plasma processing chamber, comprising a plurality of cycles is provided. Each cycle comprises a deposition phase and an etching phase. The deposition phase comprises providing a flow of deposition gas, forming a plasma from the deposition gas in the plasma processing chamber, providing a first bias during the deposition phase to provide an anisotropic deposition, and stopping the flow of the deposition gas into the plasma processing chamber. The etching phase, comprises providing a flow of an etch gas, forming a plasma from the etch gas in the plasma processing chamber, providing a second bias during the etch phase, wherein the first bias is greater than the second bias, and stopping the flow of the etch gas into the plasma processing chamber.

Abstract: In a plasma etching method, a substrate, on which an oxide film as a target layer to be etched, a hard mask layer, and a patterned photoresist are sequentially formed, is loaded into the processing chamber and mounted on a lower electrode. A processing gas containing CxFy (x is 3 or less and y is 8 or less), C4F8, a rare gas and O2 is supplied and a plasma of the processing gas is generated by applying a high frequency power to an upper or a lower electrode. Further, a high frequency power for bias is applied to the lower electrode, and a DC voltage is applied to the upper electrode.

Abstract: A method and system for fabricating a substrate is disclosed. First, a plurality of process chambers are provided, at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate and at least one of the plurality of process chambers containing a plasma filtering plate library. A plasma filtering plate is selected and removed from the plasma filtering plate library. Then, the plasma filtering plate is inserted into at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate. Subsequently, an etching process is performed in the substrate.

Abstract: A method for etching a conductive layer through a mask with wider and narrower features is provided. A steady state etch gas is flowed. A steady state RF power is provided to form a plasma from the etch gas. A pulsed bias voltage is provided during the steady state etch gas flow, wherein the pulsed bias voltage has a frequency between 1 to 10,000 Hz. Wider and narrower features are etched into the conductive layer using the plasma formed from the etch gas.

Abstract: The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings. The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.