Abstract: A general method of the invention is to provide a polymer-hardening precursor piece (such as silicon, carbon, silicon carbide or silicon nitride, but preferably silicon) within the reactor chamber during an etch process with a fluoro-carbon or fluoro-hydrocarbon gas, and to heat the polymer-hardening precursor piece above the polymerization temperature sufficiently to achieve a desired increase in oxide-to-silicon etch selectivity. Generally, this polymer-hardening precursor or silicon piece may be an integral part of the reactor chamber walls and/or ceiling or a separate, expendable and quickly removable piece, and the heating/cooling apparatus may be of any suitable type including apparatus which conductively or remotely heats the silicon piece.

Abstract: An apparatus and method is provided for rapid thermal processing (RTP) of semiconductor wafers that compensates for variations in heat absorption characteristics of the wafers. Wafer-to-wafer temperature variation is substantially eliminated using a model of the heat absorption characteristics of different wafer types to predict a steady state temperature of a wafer undergoing processing. This prediction is used to detect potential variations in wafer temperature during the RTP process and correct for these variations by adjusting the output of the heat source.

Abstract: In the semiconductor wafer manufacturing method of the present invention, a deteriorated layer on the surface of a semiconductor wafer which has been made flat by lapping or polishing is removed by the following dry etching. Plasma which contains a neutral active species is generated within a discharge tube. The neutral active species is separated from the plasma thus generated and is then conveyed to an orifice side of a nozzle portion of the discharge tube. The orifice is opposed to the wafer surface and the nozzle portion moves along the wafer surface while the neutral active species is sprayed from the nozzle orifice toward the wafer surface which is pre-heated. By such dry etching, the deteriorated layer on the wafer surface is removed without the occurrence of any etch pit.

Abstract: A gas distribution system for uniformly or non-uniformly distributing gas across the surface of a semiconductor substrate. The gas distribution system includes a support plate and a showerhead which are secured together to define a gas distribution chamber therebetween. A baffle assembly including one or more baffle plates is located within the gas distribution chamber. The baffle arrangement includes a first gas supply supplying process gas to a central portion of the baffle chamber and a second gas supply supplying a second process gas to a peripheral region of the baffle chamber. Because the pressure of the gas is greater at locations closer to the outlets of the first and second gas supplies, the gas pressure at the backside of the showerhead can be made more uniform than in the case with a single gas supply.

Abstract: In order to carry out ashing at a high efficiency without leaving any residue and also to inhibit corrosion of an underlying material of a resist and further to prevent particle contamination, a photoresist is ashed at a low temperature to be removed and a residue of the photoresist is removed at a high temperature.

Abstract: The temperature of a dry etch process of a semiconductor substrate in a plasma etch chamber is controlled to maintain selectivity while also providing a high etch rate by introducing one or more cooling steps into the etch process. To maintain selectivity of the etch as well as a high rate of etch, the formation of plasma is terminated prior to exceeding a predetermined maximum temperature at at least one selected location in the chamber. The temperature at the selected location is reduced prior to the resumption of plasma flow and etching. The plasma etch is then continued, and may optionally be terminated again to permit cooling, as needed, until etching has been completed.

Abstract: A method for plasma stripping a defective resist from a wafer that significantly reduces formation of residue between metal lines caused by conventional plasma stripping methodology and eliminates bridging, short-circuiting, and device failure caused thereby. The method includes locating a wafer in a chamber having a platen, reducing a pressure in the chamber to a predetermined pressure, and placing the wafer in contact with the platen to heat the wafer. In the method, the wafer is heated to a temperature below approximately 210° C. and is then moved away from the platen while the wafer temperature is below approximately 210° C. Plasma stripping a resist layer is then performed while maintaining the wafer temperature below approximately 210° C. By maintaining the temperature of the wafer below approximately 210° C., residue formation is substantially prevented and product yield is improved.

Abstract: It is an object of the present invention, when forming a high-density plasma CVD film, to suppress the production of particles, which are the cause of unsatisfactory formation of a micropattern, without causing a drop in productivity, and thus improve the yield of a semiconductor device. For this purpose, a CVD film is formed on a predetermined plurality of semiconductor substrates by repeating, in order, a process #101a in which a plasma CVD film is formed on a semiconductor substrate, and a process #101b in which low-pressure cleaning of the inside of a reaction chamber is performed by way of exhaustion to a first exhaust line on which a turbo pump employed in #101a is placed. In this manner, reactant, which has adhered to the first exhaust line, can be removed during the low-pressure cleaning.

Abstract: A wafer processing apparatus includes a processing chamber, a chuck arranged in the processing chamber for supporting a wafer, and a pedestal which is spaced apart from the chuck. A first gas layer is provided between the chuck and the wafer and a second gas layer is provided in the space between the pedestal and the chuck. The pressure of the first gas layer is controlled to be in a pressure range in which a thermal conductivity of the first gas layer is substantially constant with respect to changes in pressure of the first gas layer and the pressure of the second gas layer is controlled so as to control an amount of heat transferred to/from the pedestal.

Abstract: A method for etching a dielectric in a thermally controlled plasma etch chamber with an expanded processing window. The method is adapted to incorporate benefits of a the thermal control and high evacuation capability of the chamber. Etchent gases include hydrocarbons, oxygen and inert gas. Explanation is provided for enablling the use of hexafluoro-1,3-butadiene in a capacitively coupled etch plasma. The method is very useful for creating via, self aligned contacts, dual damascene, and other dielectric etch.

Abstract: A method of manufacturing a contact of a semiconductor device includes a series of pretreatment processes each performed in a plasma pretreatment module. A semiconductor substrate has an interlayer formed on an underlayer of a material containing silicon. A contact hole is formed in the interlayer to expose a surface of the underlayer. Subsequently, the semiconductor substrate is loaded into a plasma pretreatment module. The photoresist pattern is removed by ashing in the plasma pretreatment module. A damaged layer at the surface exposed by the contact hole is then removed in the plasma pretreatment module. Subsequently, the semiconductor substrate is pre-cleaned in the plasma pretreatment module. The semiconductor substrate is then transferred, while in a vacuum, to a deposition module. There, an upper layer is formed on the substrate to fill the contact hole. SEC.

Abstract: A method for treating a film of material, which can be defined on a substrate, e.g., silicon. The method includes providing a substrate comprising a cleaved surface, which had a porous silicon layer thereon. The substrate may have a distribution of hydrogen bearing particles defined from the cleaved surface to a region underlying said cleaved surface. The method also includes increasing a temperature of the cleaved surface to greater than about 1,000 Degrees Celsius while maintaining the cleaved surface in a etchant bearing environment to reduce a surface roughness value by about fifty percent and greater. Preferably, the value can be reduced by about eighty or ninety percent and greater, depending upon the embodiment.

Abstract: A process for revealing agglomerated intrinsic point defects in a single crystal silicon sample. The process includes heat-treating the single crystal silicon sample, cooling the heat-treated sample and then coating a surface of the cooled sample with a composition containing a metal which is capable of decorating agglomerated intrinsic point defects. The coated sample is then heat-treated in an inert atmosphere at a temperature and for a time sufficient to diffuse the metal into the sample. A non-defect delineating etch is performed, followed by a defect delineating etch to reveal the decorated agglomerated intrinsic point defects.

Abstract: A process is provided for etching a silicon based material in a substrate, such as a photomask, to form features with straight sidewalls, flat bottoms, and high profile angles between the sidewalls and bottom, and minimizing the formation of polymer deposits on the substrate. In the etching process, the substrate is positioned in a processing chamber, a processing gas comprising a fluorocarbon, which advantageously is a hydrogen free fluorocarbon, is introduced into the processing chamber, wherein the substrate is maintained at a reduced temperature, and the processing gas is excited into a plasma state at a reduced power level to etch the silicon based material of the substrate. The processing gas may further comprise an inert gas, such as argon.

Abstract: In a related interconnection structure that is formed by filling a metal, there have been problems, since defective connection occurs due to generation of voids and other features caused by poor filling of the metal, which entails reduction in reliability, and contact resistance is large due to a barrier metal layer at a contact portion. A novel interconnection structure is provided which comprises: a recess (for example, a contact hole, a trench, or a trench and a contact hole formed at a bottom of the trench), which is connected onto a conductive material mass formed in an insulating film, and which is formed in the insulating film; a barrier metal layer formed on side walls of the recess; and metal material masses filled in the interior of the recess, wherein the metal material masses are formed with a metal repeatedly filled into the recess over a plurality of times, and a metal material mass and a conductive material mass are directly connected to each other.

Abstract: A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas. Specifically, one embodiment of the present invention utilizes a dry abrasive polishing pad to abrade the desired surface of the semiconductor wafer within a vacuum planarization chamber. As a result of abrading the surface, the abrasive polishing pad breaks the chemical bonds of a thin layer of the dielectric surface material.

Abstract: There are included steps of forming a silicon nitride layer on a silicon layer or a silicon oxide layer, loading the silicon layer or the silicon oxide layer and the silicon nitride layer in a dry etching atmosphere, and selectively etching the silicon nitride layer with respect to the silicon layer or the silicon oxide layer by flowing a fluorine gas consisting of any one of CH2F2, CH3F, or CHF3 and an inert gas to the dry etching atmosphere. Hence, in the etching process of the silicon nitride layer, the etching selectivity of the silicon nitride layer to Si or SiO2 can be enhanced and also etching anisotropy can be enhanced.

Abstract: In one aspect, the invention encompasses a method of etching insulative materials which comprise complexes of metal and oxygen. The insulative materials are exposed to physical etching conditions within a reaction chamber and in the presence of at least one oxygen-containing gas. In another aspect, the invention encompasses a method of forming a capacitor. An electrically conductive first layer is formed over a substrate, and a second layer is formed over the first layer. The second layer is a dielectric layer and comprises a complex of metal and oxygen. A conductive third layer is formed over the second layer. The first, second and third layers are patterned into a capacitor construction. The patterning of the second layer comprises exposing the second layer to at least one oxygen-containing gas while also exposing the second layer to physical etching conditions.

Abstract: In a dry etching apparatus, a susceptor cover is attached to a substrate susceptor to shape it into a tapered contour, and no other element is positioned around a wafer support plane to ensure a flatness. A wafer positioning mechanism is provided near the perimeter of the wafer support plane, and it is raised to extend to a level higher than the wafer support plane and used in this status only upon setting or removing the wafer.

Abstract: A method of cleaning a substrate is provided which can remove contamination after working a surface of a substrate by use of chemicals etc. or treat the surface of a substrate by use of the chemicals, etc. prior to film formation. The method of cleaning the substrate can clean the surface of the substrate 30 by use of a vapor of chlorosulfonic acid (SO2Cl(OH)).

Abstract: According to the disclosed method, there is provided a structure consisting of a silicon substrate coated with a bottom thin SiO2 layer, a doped polysilicon layer, a refractory metal layer and a top Si3N4 capping layer. Said refractory metal and doped polysilicon layers will form a polycide layer under subsequent thermal treatments. First, a sacrificial layer of a dielectric material such as oxynitride is deposited onto the structure. Oxynitride is impervious to UV radiation and has excellent conformal properties. Then, a layer of a photoresist material is deposited onto the structure and patterned to form a mask. Now the dielectric and top Si3N4 layers are anisotropically etched using the photoresist mask. The mask is stripped and the refractory metal and doped polysilicon layers are anisotropically dry etched down to the SiO2 layer using the patterned dielectric layer as an in-situ hard mask.

Abstract: A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber, which includes a fluorine scavenger in the form of silicon. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 and 40 sccm for CHF3 and between about 10 and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added.

Abstract: An improved vacuum plasma etching device for plasma etching semiconductor wafers that have a photo-resist pattern. The improved plasma etching device has a reaction chamber in which the plasma etching is performed during a process cycle, an entrance vacuum loadlock for holding the next semiconductor wafer to be plasma etched, an exit vacuum loadlock for transporting the semiconductor wafers out of the reaction chamber after the plasma etching process, and a source of ultraviolet light. Exposing the semiconductor wafer to the ultraviolet light cures the photo-resist patterns, thereby improving CD dispersion, enhancing pattern transfer, and preventing photo-resist reticulation. Curing the photo-resist patterns while the semiconductor wafer is being held during the process cycle in the entrance vacuum loadlock, increases efficiency and productivity.

Abstract: A method of supporting a semiconductor substrate according to the present invention can be applied to the step of processing the semiconductor substrate at a high temperature of 350° C. or higher, and there is provided a process for the production of electronic parts, comprising the steps of forming semiconductor circuits on one surface (surface A) of a semiconductor substrate (SEC) having a thickness of at least 0.2 mm, supporting the semiconductor substrate on a supporting substrate (BP) by bonding (AS) of said surface A to the supporting substrate (BP), grinding and polishing the exposed other surface (surface B) of the semiconductor substrate (SEC) by a physical method, a chemical method or a method of combination of these methods, to decrease the thickness of the semiconductor substrate (SEC) to less than 0.

Abstract: Adherent matrix layers such as post-etch and other post-process residues are removed from a substrate by exposing them to a vapor phase solvent to allow penetration of the vapor phase solvent into the adherent matrix layers and condensing the vapor phase solvent into the adherent matrix layers and revaporized to promote fragmentation of the matrix and facilitate removal. Megasonic energy may be transmitted via a transmission member to the adherent matrix through the solvent condensed thereon to loosen fragments and particles. The substrate is typically rotated to improve contact between the megasonic energy transmission member and the condensed solvent and achieve more uniform cleaning. A co-solvent which is soluble in the vapor phase solvent may be added to enhance removal of specific adherent matrix materials.

Abstract: A heating processing chamber has a plate for holding a wafer and a heater heating the plate portion. The plate portion is composed of a plurality of divided plates separated from each other, and thereby the plate is hard to break even through a drastic change in temperature, thus making it possible to increase the durability of the plate.

Abstract: A method for cleaning a polymer in a trench produced by a dry anisotropic etching process is disclosed. The method includes steps of introducing a gas into a trench for reacting with the polymer to form a volatile substance and removing the remaining polymer in the trench by a wet etching process. The gas is preferably a gaseous hydrofluoric acid to clean the polymer. Because the gas can enter the small hole of the deep trench easily, this method can completely remove the polymer in the trench.

Abstract: An objective of this invention is to provide a plasma processing method that is capable of reducing particle contamination during plasma processing performed upon a semiconductor wafer. If the use of electron cyclotron resonance to generate a plasma and form a thin film of SiOF or the like is used by way of example, a sheath zone of a few mm thick is formed between the wafer and the plasma, and particles are trapped within a boundary zone between the sheath zone and the plasma. At this point, a microwave power is not dropped suddenly to zero after the film-formation processing, but is reduced to a lower level of, for example, 1 kW and is held for 10 seconds. This reduces the plasma density and thickens the sheath zone, so that particles are held away from the wafer surface. When the microwave power is subsequently cut, the particles move freely around, but only a small proportion thereof adhere to the wafer.

Abstract: There is provided a method of dry etching a nickel film formed on a substrate by means of plasma of an etching gas, wherein the etching gas includes at least one of CO and CO2 gases, and the substrate is designed to keep a temperature in the range of −25° C. to 40° C. both inclusive, while the substrate is being etched. For instance, the etching gas is a mixture gas including CO and CO2 gases, a mixture gas including CO, CO2 and H2 gases, or a mixture gas including CO and H2 gases. The above-mentioned method provides higher etching accuracy, higher etching rate, and less etching damage in a substrate.

Abstract: Presented is a method of enhancing the rate of removal of a photoresist layer from wafers of semiconductor material after the latter have gone through various process steps to define the patterns of integrated circuits. The method includes heating the wafer and treating it with low-pressure steam in a vacuum environment before starting to remove the photoresist by plasma or wet solutions. This pre-treatment of the photoresists allows the time for removing the photoresist to be reduced substantially and eliminates problems from residue.

Abstract: The present disclosure provides a method for etchback of a conductive layer in a contact via (contact hole). The method described is typically used in the formation of a conductive plug within the contact hole. The method includes a first etchback in which the conductive layer is etched back; a buffer (i.e., transition) step during which the etch rate of the conductive layer is reduced; and a second etchback in which the amount of chemically reactive etchant is reduced from that used in the first etchback and a plasma species is added to provide additional physical bombardment, in an isotropic etch of the substrate surface surrounding the contact hole.

Abstract: A local etching apparatus and a local etching method provide a high etching rate without impairing the mirror surface of the object to be etched and free from unevenness of the etching rate, thereby enabling the entire surface of an object to be etched to be etched by a uniform etching rate. The local etching apparatus includes a plasma generator 1 to cause plasma discharge of a mixed gas of CF4 and O2 fed from a gas feeder 3 to an alumina discharge tube 2 to produce F radicals R and spraying the F radicals R from the nozzle portion 20 to a silicon wafer W on a chuck 93 so as to locally etch the silicon wafer W. At this time, a power supply 71 of a wafer heating portion 7 is turned on and a voltage adjusted by a voltage regulator 72 is supplied to a spiral-shaped heating wire 70 in the chuck 93 to heat the entire silicon wafer W to, preferably, a heating temperature of the silicon wafer W set to a temperature range of from 20° C. to 300° C.

Abstract: A method for anisotropically etching a partially manufactured semiconductor structure, more specifically, a stacked FET gate structure containing a bottom anti-reflective coating (Barc) layer is described. The structure is covered with a photoresist layer which is patterned to defines the gate region. The processing chemistry is predominantly carbon tetrafluoride, (CF4) with the inclusion of chlorine (Cl2) where fluorine (F) is generated in the plasma as the etchant for the structure. During processing, the wafer is cooled with helium (He) that lowers the wafer temperature and promotes sidewall deposition from the fluorine species which acts as a passivation layer producing a anisotropic or vertical etch profile. The process reduces etch time and results in very repeatable end point control of the Bark etch and poly cap etch improving the control of the structure critical dimensions and improving process throughput. The reduction in the use of fluorine based species reduces any potential environmental impact.

Abstract: In one embodiment, the present invention relates to a method of processing a semiconductor structure including a resist thereon, involving contacting the semiconductor structure including the resist with a plasma comprising at least one inert gas selected from the group consisting of nitrogen, helium, neon, argon, krypton and xenon; exposing the semiconductor structure including the resist to actinic radiation having a wavelength of about 160 nm or less through a lithography mask; and developing the resist with a developer.

Abstract: A method of limiting surface damage during reactive ion etching of an organic polymer layer on a semiconductor substrate combines particular choices of process gases and plasma conditions with a post-etch passivation treatment. According to the method, a low density plasma etcher is used with a process gas mixture of one or more of an inert gas such as argon, helium, or nitrogen; methane; hydrogen; and oxygen, where the percentage of oxygen is up to about 5%. Typically a parallel plate plasma etcher is used. The reactive ion etching is followed by a post-etch passivation treatment in a which a gas containing hydrogen is flowed over the etched layer at an elevated temperature. The method is particularly useful in reactive ion etching of fluorinated organic polymer layers such as films formed from parylene AF4, and layers of poly(arylene ethers) and TEFLON®.

Abstract: A method for forming a patterned shape from a noble metal, in accordance with the present invention, includes forming a noble metal layer over a dielectric layer and patterning a hard mask layer on the noble metal layer. The hard mask layer includes a mask material that is selectively removable relative to the noble metal layer and the dielectric layer and capable of withstanding plasma etching. Alternately, the hard mask material may be consumable during the noble metal layer plasma etching. Plasma etching is performed on the noble metal layer in accordance with the patterned hard mask layer. The hard mask layer is removed such that a patterned shape formed in the noble metal layer remains intact after the plasma etching and the hard mask removal.

Abstract: The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure comprising a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.

Abstract: A process for determining particles in a dry etching system, prior to performing the dry etching definition of a desired pattern, has been developed. The process features a two cycle, dry etching procedure, with the first cycle performed using a first set of dry etching conditions, not robust enough to result in etching of exposed material, but robust enough do allow the activation, and operation, of a backside helium alarm procedure, used to monitor particle count in the dry etching chamber, to be realized. If particle counts are acceptable a second cycle of the dry etching procedure, using a second set of dry etching conditions, is employed to define the desired pattern. If the particle counts observed via use of the backside helium alarm procedure during the non-etching, first cycle, are high, the dry etching procedure is interrupted. After cleanup of the dry etching chamber, the same samples, with a re-worked photoresist, are again subjected to the two cycle, dry etching procedure.

Abstract: A method for removing a photoresist layer from a semiconductor substrate following a conventional dry etching step. A first wet chemical treatment strips the photoresist. A second dry ash with oxygen plasma completes the photoresist removal. To assure complete removal of photoresist imbedded on or within the material underlying the photoresist film, the semiconductor substrate is preheat treated to a temperature in the range of 150 to 250 degrees Centigrade to release the photoresist prior to the second dry ash with oxygen plasma operation. In particular, this method eliminates photoresist extrusion defects from occurring during a bond pad alloy operation.

Abstract: A plasma processing chamber includes a substrate holder and a gas distribution plate having an inner surface facing the substrate holder, the inner surface being maintained below a threshold temperature to minimize process drift during processing of substrates. The inner surface is cooled by adding a heat transfer gas such as helium to process gas supplied through the gas distribution plate. The chamber can include a dielectric window between an antenna and the gas distribution plate. The control of the temperature of the inner surface facing the substrate minimizes process drift and degradation of the quality of the processed substrates during sequential processing of the substrates such as during oxide etching of semiconductor wafers.

Abstract: A method for removing residual photoresist and polymer residues from silicon wafers after a polysilicon plasma etch with minimal gate oxide loss is described. The method is particularly useful for cleaning wafers after polysilicon or polycide gate etching in MOSFET with when very thin gate oxides (<100Å). In order to etch the final portion of the polysilicon gate structure including an over etch to removed isolated polysilicon patches, an etchant containing HBr is used to provide a high polysilicon to gate oxide selectivity. This etch component causes a polymer veil to form over the surface of the photoresist which is difficult to remove except by aqueous etchants which also cause significant gate oxide loss. The method of the invention addresses the removal of the veil polymer, the photoresist, and a sidewall polymer by an all dry etching process.

Abstract: An aluminum nitride-based sintered body is disclosed, which includes aluminum nitride as a main ingredient and magnesium and has a polycrystalline structure composed of aluminum nitride crystals.

Abstract: A plasma etching apparatus and a plasma etching method for conducting a plasma etching treatment for a substrate to be treated placed on one of parallel plate electrodes disposed oppositely to each other in a treatment chamber, wherein gas supplying device is used to supply a mixed gas including oxygen and a fluorine gas in the treatment chamber and the plasma discharge is conducted between the parallel plate electrodes under the condition that the product PL of a distance L[m] between the plate electrodes and the pressure P[Pa] of the mixed gas in the treatment chamber takes a value within 2.5[Pa·m] to 15[Pa·m] so as to efficiently perform an etching treatment, at a low cost, and in uniform.

Abstract: In one embodiment, a first dielectric film (24), and a second dielectric film (32) are formed over a substrate (10). The substrate is cured to at least partially change a property of the second dielectric film thereby forming an intermediate etch stop (46). A third dielectric film (42) is formed over the substrate (10). The substrate (10) is then etched to remove portions of the first dielectric film (24) and portions of the third dielectric film (42) using the intermediate etch stop (46) to form a portion of an interconnect opening (103). In an alternative embodiment, a resist layer (92), and portions of an interlevel dielectric layer (50) are etched. Upon completion of the step of etching, the photoresist layer (92) and portions of the interlevel dielectric layer (50) are completely removed.

Abstract: An apparatus and method for controlling a plasma in a plasma processing system. The apparatus comprises a wafer support pedestal surrounded by a process kit that is driven by an RF signal. Both an electrode (cathode) in the pedestal and the process kit are driven with an RF signal to establish a primary plasma above the pedestal and a secondary plasma above the process kit.

Abstract: A process for removal of photoresist present on a polymer dielectric on a semiconductor substrate and for removal of photoresist residues on the inside walls of microvias formed in the dielectric layer. The process is conducted by generating a plasma in a plasma generator from a gas comprising one or more fluorine compound containing etchant gases and etching the substrate having a dielectric layer thereon, and a photoresist layer on the dielectric layer and on the inside walls of microvias formed in the dielectric layer. The etching is conducted at a temperature of from about 0° C. to about 90° C. and at a pressure of from about 10 torr or less, to thereby remove the photoresist present on the dielectric layer and on the inside walls of the microvias.

Abstract: There is disclosed a heat treatment method for a silicon wafer. A silicon wafer, on which a natural oxide film is formed at least at the surface thereof, is loaded directly into a heat treatment furnace heated to a temperature within a temperature range of 1000° C. to the melting point of silicon. Subsequently, the silicon wafer is heat-treated at a temperature within the temperature range, and the silicon wafer having a temperature within the temperature range is unloaded from the heat treatment furnace immediately after the heat treatment is completed. The heat treatment method can be performed at low cost, and can remove crystal defects within a short period of time, with no use of gas endangering safety such as hydrogen.

Abstract: A method of patterning a brittle material, and particularly a semiconductor material, is provided comprising ion implantation induced selective area exfoliation. The method includes steps of masking the material, implanting unmasked regions of the material, with light ions of Hydrogen or Helium, and rapid thermal annealing at the temperature causing exfoliation of the material from the implanted regions. As a result, the material is patterned to a depth determined by the depth of ion implantation. The method allows patterning through crystalline or non-crystalline materials, or several layers of different materials at the same time. When the mask has straight sharp edges aligned parallel to natural cleavage planes of the semiconductor material, the exfoliation results in formation of high quality sidewall-facets of exfoliated material and of the remaining patterned material at the boundaries of exfoliated regions.

Abstract: The present invention provides a method for etching a poly-silicon layer of a semiconductor wafer. The semiconductor wafer comprises a dielectric layer, a poly-silicon layer situated on the dielectric layer and containing dopants to a predetermined depth, and a photo-resist layer having a rectangular cross-section above a predetermined area of the poly-silicon layer. The semiconductor wafer is processed in a plasma chamber. A first dry-etching process is performed to vertically etch away the dopant-containing portion of the poly-silicon layer not covered by the photo-resist layer. Then, a second dry-etching process is performed to vertically etch away the residual portion of the poly-silicon layer not covered by the photo-resist layer down to the surface of the dielectric layer. The etching gases used in the first dry-etching process differ from those used in the second dry-etching process, and the main etching gas of the first dry-etching process is C2F6.

Abstract: A CVD processing reactor employs a pyrometer to control temperature ramping. The pyrometer is calibrated between wafer processing by using a thermocouple that senses temperature during a steady state portion of a processing operation.