Abstract: A method for manufacturing an article having polymeric residue that is to be removed during the manufacture of the article is disclosed. The article is introduced into a controlled environment of a processing tool having one or more processing chambers. Free radicals are generated from one or more reactant gases and introduced into at least one of the one or more processing chambers where they react with the polymeric residue. A cryogenic cleaning medium is supplied into at least one of the one or more processing chambers where the cryogenic cleaning medium removes the polymeric residue present after the free radicals react with the polymeric residue. The reactant gases are selected to facilitate removal of the polymeric residue with the cryogenic cleaning medium. The cryogenic cleaning medium is supplied with a pulsating flow via a nozzle implement that sweeps across the article.

Abstract: A method of changing the temperature of a substrate during processing of the substrate includes providing the substrate on a substrate holder, the substrate holder including a temperature controlled substrate support for supporting the substrate, a temperature controlled base support for supporting the substrate support and a thermal insulator interposed between the temperature controlled substrate support and the temperature controlled base support. The method further includes setting the temperature of the base support to a first base temperature corresponding to a first processing temperature of the substrate, setting the substrate support to a first support temperature corresponding to the first processing temperature of the substrate, setting the temperature of the base support to a second base temperature corresponding to a second processing temperature of the substrate, and setting the substrate support to a second support temperature corresponding to the second processing temperature of the substrate.

Abstract: The present invention relates to a method for forming a contact opening. First, a substrate having at least a dielectric layer formed thereon is provided. Then, a photoresist layer having a first opening is formed on the dielectric layer. A plasma etching operation is performed to form a second opening in the dielectric layer, and the first opening is located above the second opening. The bottom part of the first opening has a diameter smaller than that of the top part of the second opening. Thereafter, the photoresist layer is removed from the dielectric layer. Accordingly, at least a portion of the exposed contact opening will not be oxidized to prevent an increase in the resistance between the conductive pattern and the conductive layer that fills in the contact opening.

Abstract: A method and system for patterning a dielectric film such as a low dielectric constant (low-k) material. A dry non-plasma etching process can be implemented to transfer a pattern from a photo-lithographic layer to a hard mask layer, while minimizing the evolution of surface roughness in the sidewall of the etched pattern in the hard mask layer. Once a pattern is transferred to the hard mask layer, the photo-lithographic layer can be removed in order to minimize the exposure of the underlying low-k dielectric film to the ashing or wet stripping process that facilitates removal of the photo-lithographic layer. The dry non-plasma removal process comprises a chemical treatment of the exposed hard mask layer, followed by a thermal treatment of the chemically treated exposed layer. The two steps, chemical and thermal treatment, can be repeated.

Abstract: A plasma etch process for etching a porous carbon-doped silicon oxide dielectric layer using a photoresist mask is carried out first in an etch reactor by performing a fluoro-carbon based etch process on the workpiece to etch exposed portions of the dielectric layer while depositing protective fluoro-carbon polymer on the photoresist mask. Then, in an ashing reactor, polymer and photoresist are removed by heating the workpiece to over 100 degrees C., exposing a peripheral portion of the backside of said workpiece, and providing products from a plasma of a hydrogen process gas to reduce carbon contained in polymer and photoresist on said workpiece until the polymer has been removed from a backside of said workpiece. The process gas preferably contains both hydrogen gas and water vapor, although the primary constituent is hydrogen gas. The wafer (workpiece) backside may be exposed by extending the wafer lift pins.

Abstract: Systems and method for adjusting an etch rate of an organic bottom antireflective coating (BARC) layer on a wafer. The BARC layer can be exposed to an energy source at varied intensities to determine a relationship between bake temperature and solubility of the BARC after baking, which correlates to a rate at which the BARC can be etched. The BARC can be a cross-linking BARC, which becomes more cross-linked as bake temperature is increased, resulting in decreased etch rate, or can be a cleaving BARC, which is subject to removal of etch-resistant monomers as bake temperature is increased, resulting in increased etch rate. Thus, the invention provides for adjustable BARC etch rates that can be aligned to an etch rate of a photoresist deposited over the BARC to permit concurrent etching of both layers while mitigating structural defects that can occur if etch rates of the respective layers differ.

Abstract: A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.

Abstract: The present invention provides a method for processing a photolithographic substrate within a vacuum chamber. The method comprising the steps of cooling the photolithographic substrate to a target temperature before the photolithographic substrate is processed within the vacuum chamber. At least one processing gas is introduced into the vacuum chamber. After the photolithographic substrate is at the target temperature, a plasma is ignited from the processing gas wherein the photolithographic substrate is processed using the plasma. Upon completion of the processing, the photolithographic substrate is unloaded from the vacuum chamber.

Abstract: A system and method of passivating an exposed conductive material includes placing a substrate in a process chamber and injecting a hydrogen species into the process chamber. A hydrogen species plasma is formed in the process chamber. A surface layer species is reduced from a top surface of the substrate is reduced. The reduced surface layer species are purged from the process chamber.

Abstract: A method of manufacturing a semiconductor device includes first and second processes, the latter requiring more processing time. An apparatus for performing the semiconductor manufacturing process includes a first reactor, and a plurality of second reactors for each first reactor. A first group of wafers are subjected to the first process within the first reactor, and are then transferred into a second reactor as isolated from the outside air. The first group of wafers is subjected to the second process within the second reactor. At the same time, a second group of wafers are subjected to the first process within the first reactor. After the first process is completed, the second group of wafers is transferred into an unoccupied one of the second reactors as isolated from the outside air. There, the second group of wafers is subjected to the second process.

Abstract: In a metal film production apparatus, a copper plate member is etched with a Cl2 gas plasma within a chamber to form a precursor comprising a Cu component and a Cl2 gas; and the temperatures of the copper plate member and a substrate and a difference between their temperatures are controlled as predetermined, to deposit the Cu component of the precursor on the substrate, thereby forming a film of Cu. In this apparatus, Cl* is formed in an excitation chamber of a passage communicating with the interior of the chamber to flow a Cl2 gas, and the Cl* is supplied into the chamber to withdraw a Cl2 gas from the precursor adsorbed onto the substrate, thereby promoting a Cu film formation reaction. The apparatus has a high film formation speed, can use an inexpensive starting material, and can minimize impurities remaining in the film.

Abstract: A plasma processing method utilizing a plasma processing apparatus having a plasma generating unit, a process chamber including an outer cylinder for withstanding a reduced pressure, and an inner cylinder made of non-magnetic material and being replaceable arranged inside the outer cylinder, a process gas supply unit for supplying gas to the process chamber, a specimen table for holding a specimen and a vacuum pumping unit. A temperature of the inner cylinder is monitored, and a desired inner cylinder temperature which is inputted in advance in response to a processing condition of the specimen is compared with the monitored temperature of the inner cylinder. A temperature of the outer cylinder is controlled in response to a result of the comparison so as to control the inner cylinder temperature to a predetermined value.

Abstract: A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.

Abstract: The present invention is directed to a method for thermally processing a substrate in a thermal processing system. The method provides an amount of heat to the substrate and obtains information associated with the substrate when the amount of heat is provided. For example, the substrate is provided at a presoak position within the thermal processing system, wherein the presoak position, and one or more properties associated with the substrate, such as a position and temperature, are measured. An optimal process parameter value to provide an optimal thermal uniformity of the substrate is then determined, based, at least in part, on the information obtained from the substrate. For example, a soak position of the substrate is determined, wherein the determination is based, at least in part, on the one or more measured properties associated with the substrate, and a thermal uniformity associated with a reference data set.

Abstract: To produce a mask, a first mask layer (40) is applied to the substrate (10). During or after the deposition of the first mask layer (40), the latter is exposed to an etching step. The etching step is carried out in such a manner that the material of the first mask layer (40) that has been deposited on side flanks (30) of the raised structure (20) is completely removed from the side flanks (30) or is at least in sections completely removed from the side flanks (30). A second mask layer (50) is applied to the first mask layer and to the uncovered side flank sections (150) of the raised structure (20). Then, the first and second mask layers can be patterned so as to complete the mask (60).

Abstract: A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber, which includes a fluorine scavenger in the form of silicon. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 and 40 sccm for CHF3 and between about 10 and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added.

Abstract: The invention provides a method of assaying at least one element in a material including silicon. The method includes the steps of decomposing a portion of the material with an etching agent to form a solution containing hexafluorosilicic acid and at least one element to be assayed, heating the solution to a temperature sufficient to transform a substantial portion of the hexafluorosilicic acid into silicon tetrafluoride and to cause at least some of the silicon tetrafluoride to evaporate, such that a solution for assaying is obtained in which the silicon content is reduced while and the elements to be assayed are conserved; and assaying at least one element contained in the solution. The invention is applicable to the field of manufacturing substrates or components for optics, electronics, or optoelectronics, and in particular to the field of quality control.

Abstract: A mask forming method that can reduce manufacturing cost is disclosed. The method forms a mask on the surface of a member to be processed in order to form a desired pattern using liquid material for patterning. The method also includes applying resist to the entire surface of the member to be processed, drying the applied resist, patterning by removing the resist in a pattern-formation area using photolithography, and heating the resist.

Abstract: A method for minimizing slip line faults on a surface of a semiconductor wafer that has been obtained using a transfer technique. The method includes heating the semiconductor wafer from an ambient temperature to a first higher temperature and pausing the heating at the first higher temperature for a time sufficient to stabilize the wafer. Then the wafer is heated further from the first higher temperature to a target higher temperature during a predetermined time interval. The further heating during an initial portion of the time interval is conducted at a relatively low heating rate and the heating during a final portion of the time interval is conducted at a relatively higher heating rate to thus minimize slip line faults in the surface of the wafer.

Abstract: The present invention is a plasma processing method including: a step of introducing a substrate into a processing container, a metal or metallic compound film being formed on a surface of the substrate; a step of supplying a noble gas and an H2 gas into the processing container; and a step of generating plasma in the processing container while the noble gas and the H2 gas are supplied, so that a natural oxide film formed on a surface of the metal or metallic compound film is removed by means of the plasma. According to the invention, the noble gas and the H2 gas are supplied into the processing container, the plasma is generated in the processing container, and the plasma acts on the natural oxide film formed on a surface of the metal or metallic compound film. Thus, active hydrogen in the plasma reduces the natural oxide film, and active species of the noble gas etch the natural oxide film. As a result, the natural oxide film can be removed with a satisfactory selective ratio.

Abstract: A thermal cleaning of a substrate that has been subjected to wet cleaning is carried out under a high vacuum atmosphere to remove an oxide film remaining on the substrate. Thereafter, a thermal cleaning is carried out under a hydrogen atmosphere to remove contamination such as carbon or the like. At this time, the oxide film has already been removed and therefore contamination is effectively removed by a relatively low temperature and short duration thermal cleaning. Thus, problems such as the degradation of the profile of the impurity concentration in the impurity diffusion layer which has been formed over the substrate are prevented.

Abstract: The present invention provides method and apparatus for surface treatment which, when employed in process steps of manufacturing semiconductor devices, can result in the final products having enhanced reliability. According to the surface processing method, an object to be processed W is introduced in a processing vessel 10, which is then supplied with ClF3 gas serving as cleaning gas from a supply unit 26. The ClF3 gas is bound to the surface of the object to be processed W, and although the supply of the gas to the processing vessel is interrupted, the ClF3 gas bound to the surface of the object to be processed W serves to clean the surface of the object to be processed. Next, reducing gas is introduced into the processing vessel W to remove chlorine from the object to be processed W, the chlorine being derived from the ClF3 gas. After that, the introduction of the reducing gas is interrupted, and the cleaned object to be processed W is exported from the processing vessel 10.

Abstract: The copper interconnect formed by the use of a damascene technique is improved in dielectric breakdown strength (reliability). During post-CMP cleaning, alkali cleaning, a deoxidizing process due to hydrogen annealing or the like, and acid cleaning are carried out in this order. After the post-CMP cleaning and before forming an insulation film for a cap film, hydrogen plasma and ammonia plasma processes are carried out on the semiconductor substrate. In this way, a copper-based buried interconnect is formed in an interlayer insulation film structured of an insulation material having a low dielectric constant.

Abstract: A method of depositing a high density plasma silicon oxide layer having improved gapfill capabilities. In one embodiment the method includes flowing a process gas consisting of a silicon-containing source, an oxygen-containing source and helium into a substrate processing chamber and forming a plasma from the process gas. The ratio of the flow rate of the helium with respect to the combined flow rate of the silicon source and oxygen source is between 0.5:1 and 3.0:1 inclusive. In one particular embodiment, the process gas consists of monosilane (SiH4), molecular oxygen (O2) and helium.

Abstract: A cleaning process for cleaning the surface of a substrate is disclosed, wherein the surface comprises portions of a dielectric material and portions of a conductive material. According to the method disclosed, the temperature at the surface of the substrate is kept below a predefined value during the actual cleaning step in a reactive and/or inert plasma ambient, such as an argon gas ambient, wherein the predefined value corresponds to the surface temperature at which agglomeration of the conductive material occurs.

Abstract: According to one embodiment, a method for reducing contaminants in a reactor chamber is disclosed where the method comprises a step of etching the reactor chamber, which can comprise, for example, a dry etch process performed with hydrogen and HCL. Next, the reactor chamber is baked, which can comprise, for example, baking with hydrogen. Thereafter, an undoped semiconductor layer, such as an undoped silicon layer, is deposited in the reactor chamber to form a sacrificial semiconductor layer, for example, a sacrificial silicon layer. Then, the sacrificial semiconductor layer, for example, the sacrificial silicon layer, is removed from the reactor chamber. The removal step can comprise, for example, a dry etch process performed with HCL. In another embodiment, a wafer is fabricated in a reactor chamber that is substantially free of contaminants due to the implementation of the above method.

Abstract: In a plasma processing apparatus for plasma-processing a silicon wafer 6 to which a protective film 6a is stuck in a state that the silicon wafer 6 is held by a first electrode 3 by electrostatic absorption and is being cooled, the top surface 3g of the first electrode 3 consists of a top surface central area A that is inside a boundary line P2 that is distant inward by a prescribed length from the outer periphery P1 of the silicon wafer 6 and in which the conductor is exposed, and a ring-shaped top surface peripheral area B that surrounds the top surface central area A and in which the conductor is covered with an insulating coating 3f. This structure makes it possible to hold the silicon wafer 6 by sufficient electrostatic holding force by bringing the silicon wafer 6 into direct contact with the conductor and to increase the cooling efficiency by virtue of heat conduction from the silicon wafer 6 to the first electrode 3.

Abstract: A process for controlling the plasma etch of a silicon dioxide layer at a high etch rate and high selectivity with respect to silicon nitride, particularly in a multilayer structure, by (1) maintaining various portions of the etch chamber at elevated temperatures, and/ox (2) using an etch chemistry having a fluorohydrocarbon gas containing at least as many hydrogen atoms as fluorine atoms, preferably CH2F2 or CH3F.

Abstract: The present invention relates to a method for fabricating a ferroelectric random access memory device. The method includes the steps of: (a) forming a first inter-layer insulation layer on a substrate providing a transistor; (b) etching the first inter-layer insulation layer to form a storage node contact hole exposing a partial portion of the substrate; (c) burying a storage node contact including a plug and a barrier metal layer into the storage node contact hole; (d) forming an adhesion layer on the storage node contact and the first inter-layer insulation layer; (e) inducing a predetermined portion of the adhesion layer to be cracked, the predetermined portion disposed above an upper part of the plug; (f) selectively removing the cracked predetermined portion to expose a surface of the barrier metal layer formed on the plug; and (g) forming a ferroelectric capacitor connected to the plug through the exposed surface of the barrier metal layer.

Abstract: In one aspect, the invention encompasses a method of etching insulative materials which comprise complexes of metal and oxygen. The insulative materials are exposed to physical etching conditions within a reaction chamber and in the presence of at least one oxygen-containing gas. In another aspect, the invention encompasses a method of forming a capacitor. An electrically conductive first layer is formed over a substrate, and a second layer is formed over the first layer. The second layer is a dielectric layer and comprises a complex of metal and oxygen. A conductive third layer is formed over the second layer. The first, second and third layers are patterned into a capacitor construction. The patterning of the second layer comprises exposing the second layer to at least one oxygen-containing gas while also exposing the second layer to physical etching conditions.

Abstract: This invention relates to a method and apparatus for forming a micromachined device, where a workpiece is plasma etched to define a microstructure. The plasma etching is conducted in the presence of a magnetic field, which can be generated and manipulated by an electric field. The magnetic field effects the electrons present in the plasma by directing them to “collect” on a desired plane or surface of the workpiece. The electrons attract the ions of the plasma to etch the desired region of the a workpiece to a greater extent than other regions of the workpiece, thereby enabling the formation of more precise “cuts” in the workpiece to form specific shapes of microstructures. The magnetic field can be controlled in direction and intensity and substrate bias power can also be controlled during etching to precisely and accurately etch the workpiece.

Abstract: Chemical generator and method for generating a chemical species at a point of use such as the chamber of a reactor in which a workpiece such as a semiconductor wafer is to be processed. The species is generated by creating free radicals, and combining the free radicals to form the chemical species at the point of use.

Abstract: A method for SAC etching is provided involving a) etching a Si wafer having a nitride present thereon with a first etching gas containing a first perfluorocarbon and carbon monoxide, and b) etching the resultant Si wafer having an initially etched nitride photoresist thereon with a second etching gas containing a second perfluorocarbon in the substantial absence of carbon monoxide, wherein the etching steps a) and b) are performed at high RF power and low pressure compared to conventional processes to provide higher selectivity etching and a larger process window for SAC etching, as well as the ability to perform SAC etching and island contact etching under the same conditions with high verticality of the island contact and SAC walls.

Abstract: A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.

Abstract: After etching a Si-containing low permittivity insulating film with chlorine based gas, the etched wafer is subjected to an etching aftertreatment process comprising introducing oxygen gas to a vacuum processing chamber with a pressure as low as 0.2 Pa to 1 Pa and a flow rate as low as 5 cc to 20 cc/min, generating plasma within the chamber, heating the wafer 2 being subjected to aftertreatment between 50° C. and 200° C., applying a wafer bias power within the range of 50 W to 200 W, and exposing the wafer to the generated plasma, thereby simultaneously removing the photoresist components, the antireflection film components and the halogen components.

Abstract: An improved integrated circuit package for providing built-in heating or cooling to a semiconductor chip is provided. The improved integrated circuit package provides increased operational bandwidth between different circuit devices, e.g. logic and memory chips. The improved integrated circuit package does not require changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can consist of recycled rejected wafers from the front-end semiconductor processing. Micro-machined vias are formed through the silicon interposer. The micro-machined vias include electrical contacts which couple various integrated circuit devices located on the opposing surfaces of the silicon interposer. The packaging includes a Peltier element.

Abstract: Method and apparatus for etching a metal layer disposed on a substrate, such as a photomask, are provided. In one aspect, a method is provided for processing a substrate including positioning the substrate in a processing chamber, introducing a processing gas comprising (i) hydrogen chloride, (ii) an oxygen containing gas, (iii) another chlorine containing gas, and optionally, (iv) an inert gas into the processing chamber, wherein the substrate is maintained at a reduced temperature, and the processing gas is excited into a plasma state at a reduced power level to etch exposed portions of the metal layer disposed on the substrate.

Abstract: A method for reducing the loss of silicon in a plasma assisted photoresist etching process including providing a silicon substrate including a polysilicon gate structure; masking a portion of the silicon substrate with photoresist to carry out an ion implantation process for forming source and drain regions; carrying out an ion implantation process; and, removing the photoresist according to at least one plasma assisted process wherein the at least one plasma assisted process comprises fluorine containing, oxygen, and hydrogen containing plasma source gases.

Abstract: A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.

Abstract: A method of producing well-defined polycrystalline silicon regions is described, in particular for producing electrically conducting regions, in which a substrate is provided with an insulating layer and a layer of doped amorphous silicon, electromagnetic irradiation is performed using a laser source to produce the electrically conducting regions, and a shadow mask is positioned between the laser source and the substrate having the layer for definition of the contours of the electrically conducting regions.

Abstract: A method for forming optical devices on-planar substrates, as well as optical devices formed by the method are described. The method uses a linear injection APCVD process to form optical waveguide devices on planar substrates. The method is performed at approximately atmospheric pressure. According to the method, a wafer with a lower cladding layer already formed by either CVD or oxidation is placed on a conveyer, which may include a heating element. The heated wafer is transported underneath a linear injector such that the chemicals from the linear injector react on the wafer surface to form a core layer. After the core layer is formed, photoresist is spun on the surface of the wafer, and then standard lithography is used to pattern the optical devices. Next, reactive ion etching (RIE) is used to form waveguide lines. The remaining photoresist is then removed. An upper cladding layer is formed to substantially cover the core regions.

Abstract: According to one exemplary embodiment, a method for forming a contact over a silicide layer situated in a semiconductor die comprises a step of depositing a barrier layer on sidewalls of a contact hole and on a native oxide layer situated at a bottom of the contact hole, where the sidewalls are defined by the contact hole in a dielectric layer. The step of depositing the barrier layer on the sidewalls of the contact hole and on the native oxide layer can be optimized such that the barrier layer has a greater thickness at a top of the contact hole than a thickness at the bottom of the contact hole. According to this exemplary embodiment, the method further comprises a step of removing a portion of the barrier layer and the native oxide layer situated at the bottom of the contact hole to expose the silicide layer.

Abstract: A method of planarizing a spin-on material layer is provided. A substrate having a plurality of openings thereon is provided. A spin-on material layer is formed on the substrate such that the openings are completely filled. A plasma etching process is carried out to remove a portion of the spin-on material layer and expose the substrate surface. During the plasma etching process, the substrate is cooled to maintain an etching selectivity between the spin-on material layer on the substrate surface and the spin-on material layer within the openings so that a planar spin-on material layer is ultimately obtained.

Abstract: Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.

Abstract: A method for removing silicon dioxide residuals is disclosed. The method includes reacting a portion of a silicon dioxide layer (i.e., oxide) to form a reaction product layer, removing the reaction product layer and annealing in an environment to remove oxide residuals. The method finds application in a variety of semiconductor fabrication processes including, for example, fabrication of a vertical HBT or silicon-to-silicon interface without an oxide interface.

Abstract: The invention provides a method of reducing the roughness of the free surface of a wafer of semiconductor material by applying a rapid thermal annealing process under a pure argon atmosphere for a time sufficient to uniformly heat and smooth the free surface of the wafer.

Abstract: Nanotip arrays are formed by exposing a substrate to a process gas mixture that simultaneously forms nanomasks on the substrate surface and etches exposed portions of the substrate surface to form the nanotip array. Components of the process gas mixture form nanocrystallites on the surface of the substrate, thereby masking portions of the substrate from other components of the process gas mixture, which etch exposed portions of the substrate. Accordingly, nanotip arrays formed using this technique can have nanocrytallite endpoints.

Abstract: After carrying an LCD substrate in a reaction container of a heat treatment unit, blowing a previously heated helium gas from a gas supply part, which opposes to the surface of the LCD substrate, over the entire surface of the LCD substrate. The temperature of the LCD substrate is raised by radiation heat of a heater and heat exchange with the helium gas. After performing CVD or annealing in the reaction container, cooling the LCD substrate by blowing a gas for heat exchange having a temperature about a room temperature from the gas supply part over the entire surface of the LCD substrate. Return the cooled LCD substrate to a carrier in the carrier chamber via a conveyance chamber.

Abstract: A method of fabricating a stabilized TiN control wafer comprising the following steps. A silicon substrate is provided having a silicon oxide layer formed thereover. An initial TiN layer is formed over the silicon oxide layer. The silicon substrate is placed in an atmosphere having ambient oxygen for from about 22 to 26 hours to form a rested TiN layer. The rested TiN layer is heated at a temperature of from about 115 to 125° C. for from about 85 to 95 seconds to form a heat treated TiN layer, whereby the heat treated TiN layer is stabilized to form the stabilized TiN control wafer.

Abstract: The present invention provides a manufacturing method of a contact for use in a semiconductor device and a manufacturing method of a PMOS device using the same, which can obtain an electrical characteristic of a low contact resistance similar to a mixed implantation of 49BF2+ ions and 11B+ ions and reduce a manufacturing cost. The method for forming a contact of a semiconductor device includes: the steps of: forming an insulating layer on a conductive semiconductor layer; forming a contact hole within the insulating layer to expose a portion of the conductive semiconductor layer; forming a plug implantation region by implanting 30BF+ ions into the exposed conductive semiconductor layer disposed on a bottom of the contact hole; performing an annealing process for activating dopants injected by the implantation of 30BF+ ions; and filling the contact hole with a conductive layer.