Abstract: In plasma processing equipment having a vacuum processing chamber, a plasma generation means, a stage for loading a wafer to be processed in the vacuum processing chamber, an opposing electrode having an area almost equal to or wider than the aforementioned wafer which is installed opposite to the stage, and a bias power source for applying a high frequency bias to the wafer, a current path correction means is provided for correcting the current path part in the neighborhood of the outer periphery of the wafer among the high frequency current paths produced by the high frequency bias so as to be directed toward the wafer opposing surface of the opposing electrode.

Abstract: A method for processing semiconductor wafers and similar articles has an ozone remover connected to a processing chamber. The ozone remover has a light chamber surrounded by reflectors. Ozone and other processing gases and vapors flow out of the processing chamber and into the light chamber. Ultraviolet lights in the ozone remover flood the light chamber with ultraviolet light, converting ozone into oxygen. The amount of ozone released into the environment is reduced. A recirculation line receives the gases and vapors flowing out of the ozone remover. Oxygen and any remaining ozone are separated from other gas and vapor components and are recycled back to an ozone generator, to increase the ozone generator efficiency in supplying the machine with ozone.

Abstract: A semiconductor wafer is processed while being supported without mechanical contact. Instead, the wafer is supported by gas streams emanating from a large number of passages in side sections positioned very close to the upper and lower surface of the wafer. The gas heated by the side sections and the heated side sections themselves quickly heat the wafer to a desired temperature. Process gas directed to the “device side” of the wafer can be kept at a temperature that will not cause deposition on that side section, but yet the desired wafer temperature can be obtained by heating non-process gas from the other side section to the desired temperature. A plurality of passages around the periphery of the wafer on the non-processed side can be employed to provide purge gas flow that prevents process gas from reaching the non-processed side of the wafer and the adjacent area of that side section.

Abstract: The HF defect density in an SOI is reduced. After annealing step (S2) of annealing an SOI at a temperature between the melting point (e.g., 993° C.) of a semiconductor metal compound (e.g., nickel silicide) formed from a metal and the semiconductor material of the crystal semiconductor of the SOI (inclusive) and the melting point of the semiconductor material (inclusive), the temperature is reduced such that the cooling rate within the temperature range from the melting point of the semiconductor metal compound and the production temperature (e.g., 775° C.) of the semiconductor metal compound becomes 0.12° C./sec or more.

Abstract: The invention concerns a method for treating a surface for the protection and functionalisation of polymers (4) by gas plasma deposit in a confined chamber (10) of one or several silicon alloy layers (43). The silicon alloy is selected among silicon and its oxides, nitrides, oxynitrides; the deposit is performed at a temperature less than the degradation temperature of the polymer, and a physico—chemical surface pre-treatment by plasma is performed in the same chamber before the silicon alloy is deposited; the pre-treatment consisting in a surface treatment comprising etching a surface zone of the polymer and step which consists in depositing a polymeric carbon compound.

Abstract: Semiconductor wafers are cleaned by placing the semiconductor wafers in a processing vessel, forming a pure water film on the surfaces of the wafers, forming an ozonic water film by dissolving ozone gas in the pure water film, and removing resist films formed on the wafers by the agency of the ozonic water film. The pure water film is formed by condensing steam on the surfaces of the wafers. The resist films formed on the surfaces of the wafers can be removed by also using hydroxyl radicals produced by interaction between steam and ozone gas supplied into the processing vessel. Thus, the resist films can be removed highly effectively.

Abstract: A method of forming narrow gates comprising the following steps. A substrate is provided having an overlying Si3N4 or an SiO2/Si3N4 stack gate dielectric layer. A gate material layer is formed over the gate dielectric layer. A hard mask layer is formed over the gate material layer. The hard mask layer and the gate material layer are patterned to form a hard mask/gate material layer stack. A planarized dielectric layer is formed surrounding the hard mask/gate material layer stack. The patterned hard mask layer is removed from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls. Masking spacers are formed on the exposed dielectric layer side walls over a portion of the patterned gate material layer. The patterned gate material layer is etched using the masking spacers as masks to expose a portion of the gate dielectric layer. The planarized dielectric layer is removed. The masking spacers are removed to form narrow gates comprising gate material.

Abstract: A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber, which includes a fluorine scavenger in the form of silicon. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 and 40 sccm for CHF3 and between about 10 and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added.

Abstract: In a method for dry-etching a coating by use of reactive gas which is activated, a second insulating layer containing carbon atoms which is formed on a first insulating layer containing carbon atoms is ashed by use of a gas containing carbon atoms and at least one of oxygen atoms, nitrogen atoms and hydrogen atoms. By using the above gas, the second insulating layer containing carbon atoms which is formed on the first insulating layer which is an underlying layer can be efficiently ashed and removed without removing carbon atoms in the side surface of the grooves formed in the first insulating layer and etching the side surface thereof. Thus, the side surface of the groove formed in the first insulating layer will not be modified or deformed.

Abstract: A method is disclosed for speeding workpiece thoughput in low pressure, high temperature semiconductor processing reactor. The method includes loading a workpiece into a chamber at atmospheric pressure, bringing the chamber down to an intermediate pressure, and heating the wafer while under the intermediate pressure. The chamber is then pumped down to the operating pressure. The preferred embodiments involve single wafer plasma ashers, where a wafer is loaded onto lift pins at a position above a wafer chuck, the pressure is rapidly pumped down to about 40 Torr by rapidly opening and closing an isolation valve, and the wafer is simultaneously lowered to the heated chuck. Alternatively, the wafer can be pre-processed to remove an implanted photoresist crust at a first temperature and the chamber then backfilled to about 40 Torr for further heating to close to the chuck temperature. At 40 Torr, the heat transfer from the chuck to the wafer is relatively fast, but still slow enough to avoid thermal shock.

Abstract: A processing gas constituted of C5F8, O2 and Ar achieving a flow rate ratio of 1≦C5F8 flow rate/O2 flow rate≦1.625 is supplied into a processing chamber 102 of an etching apparatus 100 and the atmosphere pressure is set within a range of 45 mTorr˜50 mTorr. High-frequency power is applied to a lower electrode 110 sustained within a temperature range of 20° C.˜40° C. on which a wafer W is mounted to raise the processing gas to plasma, and using the plasma, a contact hole 210 is formed at an SiO2 film 208 on an SiNx film 206 formed at the wafer W. The use of C5F8 and O2 makes it possible to form a contact hole 210 achieving near-perfect verticality at the SiO2 film 208 and also improves the selection ratio of the SiO2 film 208 relative to the SiNx film 206. C5F8, which becomes decomposed over a short period of time when released into the atmosphere, does not induce the greenhouse effect.

Abstract: A sensor for measuring a physical amount such as an amount of air includes a membrane structure composed of metal stripes sandwiched between first and second insulating layers. A metal layer made of platinum or the like is formed on the first insulating layer and then heat-treated to improve its properties. Then, the metal layer is etched into a form of the metal stripes. The second insulating layer made of a material such as silicon dioxide is formed on the etched metal stripes. Since the metal layer is heat-treated before it is etched into the form of metal stripes, the metal stripes are not deformed by the heat-treatment. The second insulating layer can be formed on the metal stripes without generating cracks in the second insulating layer.

Abstract: A method in which etching or ashing is conducted by providing satisfactory kinetic energy of reaction seeds such as ions or radicals without damaging a substrate, and an apparatus used in this method are provided. A predetermined film of for example polycrystalline silicon on the substrate is etched in vapor phase using reaction seeds or precursors thereof generated by contacting a reaction gas such as CF4 with a heated catalyst of for example tungsten.

Abstract: A semiconductor deposition system in accordance with the present invention includes a CMP apparatus operative to planarize an active surface of a semiconductor wafer, and a wafer cleaner for cleaning wafer after the CMP process. The wafer cleaner preferably.includes a wafer rotating mechanism, a steam inlet for applying steam to the active surface of the wafer as it is rotated and a liquid inlet for simultaneously applying a liquid to the back side surface of the wafer. A method for manufacturing an integrated circuit in accordance with the present invention includes subjecting an active surface of the wafer to a plurality of processes selected from a group including deposition, patterning, doping, planarization, ashing and etching, and steam cleaning the active surface at least once before, during, and after the plurality of processes. Preferably, an aqueous vapor phase is applied to the first surface of the wafer as an aqueous liquid phase is applied to the other surface of the wafer.

Abstract: Provided is a compound semiconductor single crystal and a fabrication process for a compound semiconductor device capable of forming a prescribed pattern without requirement of many steps. A group V element component in a III-V compound semiconductor single crystal or a group VI element component in the II-VI compound semiconductor single crystal is reduced less than a composition ratio expressed by a chemical formula of a corresponding compound semiconductor single crystal in a pattern-shaped portion.

Abstract: The invention is a precleaning process suitable for fabricating metal plugs in a low-&kgr;, carbon-containing dielectric. More specifically, the invention is a process for cleaning a contact area of a metal conductor on a semiconductor workpiece so as to minimize damage to a low-&kgr;, carbon-containing dielectric overlying the metal. After forming contact openings in the low-&kgr; dielectric so as to expose contact areas on the underlying metal conductor, the contact areas are cleaned by exposing the workpiece to an atmosphere formed by plasma decomposition of a mixture of hydrogen-containing and helium gases. Surprisingly, our preclean process can repair damage to the dielectric caused by preceding process steps, such as oxygen plasma ashing processes for removing photoresist.

Abstract: An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.

Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies in the wafer. During the heat-treatment, the front and back surfaces of the wafer are each exposed to either a nitriding gas or a non-nitriding gas. The front surface of the heat-treated wafer is then oxidized by heating in the presence of an oxygen-containing atmosphere in order to further effect the vacancy concentration profile within the wafer.

Abstract: The present invention discloses a method for removing silicon nitride from a substrate, characterised in that it comprises contacting said substrate with a molten halogen salt.

Abstract: A hybrid deposition system includes a reactor chamber, at least one heating unit, a first reagent gas source, a metallo-organic source, a second reagent gas source, and a valve unit for stopping flow of gas from the metallo-organic source. The hybrid incorporates features of both metal-organic chemical vapor deposition (MOCVD) and hydride vapor-phase epitaxy (HVPE). The hybrid system may be operated in MOCVD mode, in HVPE mode, or in both MOCVD and HVPE mode simultaneously. The system may be switched between deposition modes without interrupting deposition, or removing the sample from the reactor chamber. The at least one heating unit may be moved relative to the reactor chamber, or vice versa, for easily and rapidly adjusting the temperature of the reactor chamber. A method for forming at least one epitaxial layer of a III-V compound on a non-native substrate in which deposition is performed by two different techniques in the same reactor chamber.

Abstract: The invention includes a dual-damascene semiconductor processing method. A semiconductor substrate is provided, and the substrate includes a conductive structure and an insulative layer over the conductive structure. A via is etched through the insulative layer and into the conductive structure, and a resist is formed within the via. A material is formed over the resist and substrate. A portion of the material in contact with the resist is hardened, and another portion of the material that does not contact the resist is not hardened. The portion of the material which is not hardened is removed, and a slot is etched into the insulative layer.

Abstract: A method for etching material which does not readily form volatile compounds in a plasma includes providing a plasma etch chamber including a wafer electrode at an initial temperature. The wafer electrode supports a wafer, and the wafer includes a layer of the material which does not readily form volatile compounds in plasma. The wafer is bombarded with charged particles from a plasma generated in the plasma etch chamber to impart thermal energy to the wafer. A reactive gas flow is provided to react with etch products of the material. Bias power is applied to the wafer electrode to impart bombardment energy to the charged particles incident on the wafer from the plasma such that a predetermined temperature is generated on a surface of the wafer wherein the wafer electrode is maintained at about the initial temperature.

Abstract: Conventional methods of etching TiSix use Cl2 or HBr as the plasma etchant. However, these methods can lead to undesirable residues, due to the presence of silicon nodules in the TiSix The present invention overcomes the residue problem by adding a fluorine containing gas to the plasma etchant, which is then able to effectively etch the Si nodules at an etch rate which is approximately the same as the etch rate of the TiSix, so that the undesirable residue is not formed. A method of etching TiSix is provided, wherein the surface of the TiSix is exposed, typically through a patterned mask, to a plasma etchant. The plasma etchant comprises (i) at least one fluorine containing gas, such as SF6, NF3, CxFy, and compatible mixtures of such gases; and (ii) a gas selected from the group consisting of HBr, Cl2, and combinations thereof.

Abstract: The present invention is a film forming method of forming a film of a treatment solution on the front face of a substrate in a treatment chamber including the steps of: supplying the treatment solution to the substrate mounted on a holding member in the treatment chamber in states of gas being supplied into the treatment chamber and of an atmosphere in the treatment chamber being exhausted; and measuring the temperature of the front face of the substrate before the supply of the treatment solution. The measurement of the temperature of the front face of the substrate before the supply of the treatment solution enables the check of the temperature of the front face of the substrate and the temperature distribution. Then, the measured result is compared with a previously obtained ideal temperature distribution for the formation of a film with a uniform thickness, thereby predicting the film thickness of the film which will be formed in the following processing.

Abstract: A process is provided for etching a silicon based material in a substrate, such as a photomask, to form features with straight sidewalls, flat bottoms, and high profile angles between the sidewalls and bottom, and minimizing the formation of polymer deposits on the substrate. In the etching process, the substrate is positioned in a processing chamber, a processing gas comprising a fluorocarbon, which advantageously is a hydrogen free fluorocarbon, is introduced into the processing chamber, wherein the substrate is maintained at a reduced temperature, and the processing gas is excited into a plasma state at a reduced power level to etch the silicon based material of the substrate. The processing gas may further comprise an inert gas, such as argon.

Abstract: An apparatus for performing contaminant sensitive processing on a substrate. A substrate load chamber receives the substrate from an ambient contaminant laden environment, and isolates the substrate from the ambient contaminant laden environment. The substrate load chamber further forms a first environment of intermediate cleanliness around the substrate. A substrate pass through chamber receives the substrate from the substrate load chamber, and isolates the substrate from the intermediate cleanliness of the first environment of the substrate load chamber. The substrate pass through chamber further forms a second environment of high cleanliness around the substrate. A substrate transfer chamber receives the substrate from the substrate pass through chamber, and isolates the substrate from the high cleanliness of the second environment of the substrate pass through chamber.

Abstract: In a semiconductor device manufacturing method for processing a plurality of substrates by alternately repeating a pretreatment stage and a continuous substrate processing stage, the continuous substrate processing stage comprises the steps of: loading a substrate on a heater unit located at a substrate loading/unloading position, the heater unit supporting and heating the substrate; processing the loaded substrate after transferring the heater unit having thereon the loaded substrate to a substrate processing position; unloading the processed substrate; and repeating the loading step, the processing step and the unloading step until a set of substrates are processed, and wherein the pretreatment stage is carried out by maintaining the heater unit between the substrate loading/unloading position and the substrate processing position.

Abstract: A method for removing contaminants from an integrated circuit substrate include treating the substrate with a hydrogen peroxide cleaning solution containing a chelating agent, and treating the substrate with hydrogen gas and fluorine-containing gas, and annealing the substrate. Cleaning solutions includes ammonium, hydrogen peroxide, deionized water, and chelating agent. The chelating agent includes one to three compounds selected from the group consisting of carboxylic acid compounds, phosphonic acid compounds, and hydroxyl aromatic compounds. The fluorine-containing gas is a gas selected from the group consisting of nitrogen trifluoride (NF3), hexafluorosulphur (SF6), and trifluorochlorine (ClF3).

Abstract: A method is provided for preparing a substrate for processing in a chamber that has a substrate receiving portion. The substrate is positioned within the chamber in a location not on the substrate receiving portion. A gaseous flow is provided to the chamber, from which a plasma is struck to heat the substrate. After the substrate has been heated, it is moved to the substrate receiving portion for processing.

Abstract: A wafer holder for a semiconductor manufacturing apparatus that has a high heat conductivity and includes a conductive layer such as heater circuit pattern which can be formed with a high precision pattern, a method of manufacturing the wafer holder, and a semiconductor manufacturing apparatus having therein the wafer holder are provided. On a surface of a sintered aluminum nitride piece, paste containing metal particles is applied and fired to form a heater circuit pattern as a conductive layer. Between the surface of the sintered aluminum nitride piece having the heater circuit pattern formed thereon and another sintered aluminum nitride piece, a glass layer is provided as a joint layer to be heated for joining the sintered aluminum nitride pieces together.

Abstract: A method for forming aluminum lines over aluminum-filled vias in a semiconductor substrate that can compensate for some misalignment between the filled vias and the lines. By alternately depositing liner-barrier layers and aluminum layers on the substrate, different etch chemistries can be used that can anisotropically etch an aluminum layer used to form the lines without etching voids in the aluminum-filled vias.

Abstract: In a plasma processing apparatus that has a vacuum chamber, a process gas supply means of supply gas to a processing chamber, an electrode to hold a sample inside said vacuum chamber, a plasma generator installed in said vacuum chamber opposite to said sample, and a vacuum exhaust system to decrease pressure of said vacuum chamber, a bias voltage of Vdc=−300 to −50 V is applied and the surface temperature of said plate ranges from 100 to 200° C. In addition, the surface temperature fluctuation of the silicon-made plate in said plasma processing apparatus is kept within ±25° C.

Abstract: A process for selectively etching silicon from a workpiece without etching silicon oxide or silicon nitride. The principal etchant gas is molecular fluorine gas (F2) that is not excited to a plasma state.

Abstract: There are provided a manufacturing process for a mirror finished silicon wafer capable of manufacturing a mirror finished silicon wafer, having an excellent quality in which grown-in crystal defects are annihilated by heat-treating the silicon mirror finished wafer in a heat treatment in a gas atmosphere of high safety at a lower cost without selection of a heat treatment furnace for use in the heat treatment, a mirror finished silicon wafer having an excellent quality, and a heat treatment furnace preferably used in the manufacturing process.

Abstract: Various methods of inspecting a workpiece for residue are provided. In one aspect, a method of fabricating a conductor layer on a substrate is provided that includes forming an aluminum-copper film on the substrate in a first processing chamber and forming an anti-reflective coating on the aluminum-copper film in a second processing chamber. The substrate is moved from the second processing chamber into a cooling chamber to quench the substrate. A first time interval during which the substrate is in the first processing chamber and second time interval during which the substrate is present in the second processing chamber are measured. The substrate is annealed to restore a uniform equilibrium distribution of copper in the aluminum if the first time interval exceeds about 600 seconds or the second time interval exceeds about 300 seconds. The method substantially reduces the risk of metal comb bridging device failures following etch definition of conductor lines.

Abstract: Copper can be pattern etched at acceptable rates and with selectivity over adjacent materials using an etch process which utilizes a solely physical process which we have termed “enhanced physical bombardment”. Enhanced physical bombardment requires an increase in ion density and/or an increase in ion energy of ionized species which strike the substrate surface. To assist in the removal of excited copper atoms from the surface being etched, the power to the ion generation source and/or the substrate offset bias source may be pulsed. In addition, when the bombarding ions are supplied from a remote source, the supply of these ions may be pulsed. Further, thermal phoresis may be used by maintaining a substrate temperature which is higher than the temperature of a surface in the etch chamber.

Abstract: Method and apparatus for etching a silicide stack including etching the silicide layer at a temperature elevated from that used to etch the rest of the layers in order to accomplish anisotropic etch.

Abstract: An interconnection pattern made of an aluminum alloy, such as Al—Cu, on a semiconductor IC, is dry etched in an etching gas containing a chlorine component. A photo resist stripping process is carried out at a location down stream of the etching process using a conventional stripping gas, such as CF4+02, at room temperature. Before the resist-stripped substrate is exposed to open air, the substrate is heated in a vacuum to a temperature above 100° C., to remove residual chlorine components.

Abstract: A method of etching a platinum electrode layer disposed on a substrate to produce a semiconductor device including a plurality of electrodes separated by a distance equal to or less than about 0.3 &mgr;m and having a platinum profile equal to or greater than about 85°. The method comprises heating the substrate to a temperature greater than about 150° C., and etching the platinum electrode layer by employing a high density inductively coupled plasma of an etchant gas comprising chlorine, argon and a gas selected from the group consisting of BCl3, HBr, and mixtures thereof. A semiconductor device having a substrate and a plurality of platinum electrodes supported by the substrate. The platinum electrodes have a dimension (e.g., a width) which include a value equal to or less than about 0.3 &mgr;m and a platinum profile equal to or greater than about 85°.

Abstract: Plasma treatment apparatus and method in which an influence on the treatment characteristics of reaction products in plasma treatment such as etching is offset, thereby enabling uniform treatment characteristics to be obtained in the plane of a substrate are provided. In a plasma treatment method of treating a substrate to be processed by using a gas plasma via a mask in a treatment chamber, plasma treatment is performed while optimizing an amount of deposition of a side wall protection layer, equalizing the optimized deposition amount in the center of the substrate and that in a peripheral part, and maintaining the uniformity in the plane of the side wall protection layer.

Abstract: A method for forming on a substrate employed within a microelectronics fabrication a planarized inter-level metal dielectric (IMD) layer employing spin-on-glass (SOG) dielectric material, with attenuated etching damage to underlying layers. There is provided a substrate upon which is formed a patterned microelectronics layer over which is formed an inter-level metal dielectric (IMD) layer comprising a first silicon oxide dielectric layer and a second spin-on-glass (SOG) dielectric layer. The IMD layer is then planarized by plasma etchback method employing an etch cycle interrupted by an inert gas flushing step and substrate backside cooling by helium gas to control substrate temperature and etching reaction rates, resulting in attenuated damage to underlying layers resulting from over-etching of the IMD layer.

Abstract: A process is provided for etching a silicon based material in a substrate, such as a photomask, to form features with straight sidewalls, flat bottoms, and high profile angles between the sidewalls and bottom, and minimizing the formation of polymer deposits on the substrate. In the etching process, the substrate is positioned in a processing chamber, a processing gas comprising a fluorocarbon, which advantageously is a hydrogen free fluorocarbon, is introduced into the processing chamber, wherein the substrate is maintained at a reduced temperature, and the processing gas is excited into a plasma state at a reduced power level to etch the silicon based material of the substrate. The processing gas may further comprise an inert gas, such as argon.

Abstract: An apparatus and method for the hot bake to remove moisture from photoresist that has been deposited on semiconductor wafers prior to a dry plasma etch process. A wafer carrier containing semiconductor wafers on which a photoresist has been deposited is placed in a load lock chamber having a source of heat such as a heating plate or a high intensity light source. The source of the heat is activated and the semiconductor wafers are brought to a temperature sufficiently high and of a sufficient duration as to eliminate any moisture present in the photoresist mask. The load lock chamber is evacuated to eliminate any moisture or contaminants, filled with nitrogen to eliminate any residual of moisture or contaminants, and then evacuated to prepare the chamber to exposed to the atmosphere present in a dry plasma etch chamber. An exit lock of the load lock chamber is opened and the wafer carrier is placed in the dry plasma etch chamber for the execution of the dry plasma etch process.

Abstract: A method of etching a tungsten film, comprising the steps of supporting a semiconductor substrate having a tungsten film thereon on a substrate support in an interior of a plasma etcher, supplying process gas to the interior of the plasma etcher, energizing the process gas into a plasma state, etching the tungsten film by exposing the substrate to the plasma, and heating the substrate to a temperature of at least 100° C. during the etching step. The etching step can include a low temperature main etch below 100° C. followed by a high temperature overetch above 100° C., the process gas including a fluorine containing gas during the main etch and a chlorine containing gas during the overetch. The tungsten film can be located over a dielectric film which serves as a stop layer during the etching step. The tungsten film can be pure tungsten and the dielectric layer can be a silicon oxide film having a thickness of 200 Å or less.

Abstract: An etching method through which the resist-relative selection ratio is improved and the etching shape is also improved, is provided. In an etching method for etching an SiO2 layer formed at a wafer W placed inside an airtight processing chamber 104 by inducing a processing gas into the processing chamber 104, the processing gas contains at least C5F8 and CH2F2 and the flow rate ratio of C5F8 and CH2F2 in the processing gas is essentially within the range of 1/4≦(C5F8 flow rate/CH2F2 flow rate)≦1/2. Since the processing gas contains C5F8 and CH2F2, the resist-relative selection ratio can be improved. In addition, by setting the flow rate ratio of C5F8 and CH2F2 essentially equal to or larger than 1/4, deformation of grooves due to longitudinal streaking or waviness can be eliminated, whereas by setting the flow rate ratio of C5F8 and CH2F2 essentially equal to or smaller than 1/2, deformation of grooves attributable to bowing can be eliminated.

Abstract: The present invention is a method of performing processing for a substrate including the step of carrying the substrate, which has been pre-treated, to a heat treatment unit for heating the substrate, prior to supplying a treatment solution to the substrate to perform solution treatment, in which the carrying is performed such as to fix a period after the pretreatment for the substrate is completed and before it is carried to the heat treatment unit. According to the present invention, for example, in a lithography process, the substrate is carried such as to fix the period after exposure processing that is the pretreatment and before the substrate is carried to the heat treatment unit where heat treatment that is the following treatment is performed, whereby the degrees of chemical reaction of coating films by the exposure processing become uniform between the substrates.

Abstract: This invention relates to a method of etching a substrate in a chamber on an electrostatic chuck, which defines a gas cooling path at the substrate/chuck interface. The method includes electrostatically clamping the substrate on the chuck with gas in the gas path being at a first pressure; etching the substrate at a first power; detecting the end point for the etc; reducing the gas pressure to a second pressure at which the substrate floats on a gas; and over etching the wafer at a second power, which is lower than the first power.

Abstract: An integrated in situ cluster type wafer processing apparatus which can be used for forming metal wiring layers having a multi-layered structure and a wafer processing method using the same are provided. The wafer processing apparatus includes a transfer chamber which can be exhausted and has a plurality of gate valves, a plurality of vacuum processing chambers each of which can be connected to the transfer chamber via one of the gate valves, and a load lock chamber which can be exhausted and is connectable to a first gas feed line for feeding an oxygen-based gas into the load lock chamber. In a wafer processing method, a predetermined layer is formed on a wafer in one of the vacuum processing chambers. The predetermined layer on the wafer is oxidized in the load lock chamber or an oxygen atmosphere chamber.

Abstract: A wafer etching method wherein hydrogen gas, ammonia gas or mixed gas containing one of these gases is added to sulfur hexafluoride gas to suppress the occurrence of white turbidity on the surface of the wafer at the time of etching and to enable high quality mirror polishing of the wafer. In one embodiment, a mixed gas obtained by mixing SF6 gas G1 of a bomb 31 and H2 gas G2 of a bomb 32 in a predetermined ratio is fed to a discharge tube 2 and a microwave M is generated from a microwave oscillator 4 to cause plasma discharge. Further, the entire surface of the silicon wafer W can be flattened by locally etching the surface of the silicon wafer W by an activated species gas G sprayed from the nozzle portion 20.

Abstract: In a method for manufacturing a semiconductor device, a first conductive layer is formed on a semiconductor substrate. Then, a plasma etching process using Ar ions is performed upon the first conductive layer to remove natural oxide from the first conductive layer. Then, a heating process at a temperature higher than about 650° C. is performed upon the first conductive layer to expel Ar atoms from the first conductive layer. Finally, a second conductive layer is formed by a sputtering process on the first conductive layer.