Silicon Patents (Class 438/719)
  • Patent number: 10438807
    Abstract: Provided herein are methods and related apparatus to smooth the edges of features patterned using extreme ultraviolet (EUV) lithography. In some embodiments, at least one cycle of depositing passivation layer that preferentially collects in crevices of a feature leaving protuberances exposed, and etching the feature to remove the exposed protuberances, thereby smoothing the feature, is performed. The passivation material may preferentially collect in the crevices due to a higher surface to volume ratio in the crevices than in the protuberances. In some embodiments, local critical dimension uniformity (LCDU), a measure of roughness in contact holes, is reduced. In some embodiments, at least one cycle of depositing a thin layer in a plurality of holes formed in photoresist, the holes having different CDs, wherein the thin layer preferentially deposits in the larger CD holes, and anisotropically removing the thin layer to remove it at the bottoms of the holes, is performed.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: October 8, 2019
    Assignee: Lam Research Corporation
    Inventors: Richard Wise, Nader Shamma
  • Patent number: 10431472
    Abstract: A silicon oxide film or a silicon nitride film is selectively etched by using an etching gas composition including a hydrofluorocarbon that has an unsaturated bond in its molecule and is represented by CxHyFz, wherein x is an integer of from 3 to 5, and relationships y+z?2x and y?z are satisfied. Also, a silicon oxide film is etched with high selectivity relative to a silicon nitride film by controlling the ratio among the hydrofluorocarbon, oxygen, argon, etc., included in the hydrofluorocarbon-containing etching gas composition.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: October 1, 2019
    Assignee: KANTO DENKA KOGYO CO., LTD.
    Inventors: Yoshinao Takahashi, Korehito Kato, Tetsuya Fukasawa, Yoshihiko Iketani
  • Patent number: 10424467
    Abstract: Methods and systems for RF pulse reflection reduction are provided herein. In some embodiments, a method includes (a) receiving a process recipe for processing the substrate that includes a plurality of pulsed RF power waveforms from a plurality of RF generators during a first duty cycle, (b) dividing the first duty cycle into a plurality of equal time intervals, (c) for each RF generator, determining a frequency command set for all intervals and send the frequency command set to the RF generator, wherein the frequency command set includes a frequency set point for each of the intervals in the plurality of equal time intervals, and (d) providing a plurality of RF power waveforms from a plurality of RF generators to a process chamber during a first duty cycle according to the frequency command set sent to each RF generator.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: September 24, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Katsumasa Kawasaki
  • Patent number: 10403473
    Abstract: An ion beam etching device comprises: an ion source configured to generate ions; a grid on a side of the ion source, the grid configured to accelerate the generated ions to generate an ion beam; a process chamber configured to have an etching process using the ion beam performed therein; and a variable magnetic field application part adjacent to the process chamber, the variable magnetic field application part configured to apply a variable magnetic field.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Na Cho, Jong-Kyu Kim, Hyuk Kim, Jongchul Park
  • Patent number: 10312121
    Abstract: A substrate support in a substrate processing system includes an inner portion arranged to support a substrate, an edge ring surrounding the inner portion, and a controller. The controller, to selectively cause the edge ring to engage the substrate and tilt the substrate, controls at least one actuator to at least one of raise and lower the edge ring and raise and lower the inner portion of the substrate support. The controller determines an alignment of a measurement device in the substrate processing system based on a signal reflected from a surface of the substrate when the substrate is tilted.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: June 4, 2019
    Assignee: Lam Research Corporation
    Inventors: Marcus Musselman, Andrew D. Bailey, III, Dmitry Opaits
  • Patent number: 10183856
    Abstract: A manufacturing method for a Micro-Electro-Mechanical Systems (MEMS) structure includes implementing a surface modification process, to form a transformation layer on the surfaces of the MEMS structure; implementing an anti-stiction coating pre-clean process, to clean the transformation layer on the surfaces towards a particular direction; and implementing an anti-stiction coating process, to coat a monolayer on the surfaces of the MEMS structure.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: January 22, 2019
    Assignee: SensorTek technology Corp.
    Inventors: Hsin-Hung Huang, Wei-Yang Ou
  • Patent number: 10074520
    Abstract: Systems and methods for adjusting power and frequency based on three or more states are described. One of the methods includes receiving a pulsed signal having multiple states. The pulsed signal is received by multiple radio frequency (RF) generators. When the pulsed signal having a first state is received, an RF signal having a pre-set power level is generated by a first RF generator and an RF signal having a pre-set power level is generated by a second RF generator. Moreover, when the pulsed signal having a second state is received, RF signals having pre-set power levels are generated by the first and second RF generators. Furthermore, when the pulsed signal having a third state is received, RF signals having pre-set power levels are generated by the first and second RF generators.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: September 11, 2018
    Assignee: Lam Research Corporation
    Inventors: John C. Valcore, Jr., Bradford J. Lyndaker
  • Patent number: 10068988
    Abstract: A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the polysilicon layer to change its removal rate, thereby forming a doped layer, and removing the doped layer in the first region to expose the polysilicon layer in the first region and leaving at least a portion of the doped layer in the second region. The method also includes removing the exposed polysilicon layer in the first region at a first removal rate and the doped layer in the second region at a second removal rate, the polysilicon layer in the second region being exposed after the doped layer in the second region is removed, and removing the polysilicon layer in the first region and the second region at a third removal rate and a fourth removal rate, respectively.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: September 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: William Weilun Hong, Po-Chin Nien, Ying-Tsung Chen
  • Patent number: 9881805
    Abstract: A method of etching exposed silicon on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with a hydrogen-containing precursor. The combination react with the patterned heterogeneous structures to remove an exposed silicon portion faster than a second exposed portion. The silicon selectivity results from the presence of an ion suppressor positioned between the remote plasma and the substrate processing region. The methods may be used to selectively remove silicon faster than silicon oxide, silicon nitride and a variety of metal-containing materials. The methods may be used to remove small etch amounts in a controlled manner and may result in an extremely smooth silicon surface.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: January 30, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Zihui Li, Ching-Mei Hsu, Hanshen Zhang, Jingchun Zhang
  • Patent number: 9871115
    Abstract: A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the polysilicon layer to change its removal rate, thereby forming a doped layer, and removing the doped layer in the first region to expose the polysilicon layer in the first region and leaving at least a portion of the doped layer in the second region. The method also includes removing the exposed polysilicon layer in the first region at a first removal rate and the doped layer in the second region at a second removal rate, the polysilicon layer in the second region being exposed after the doped layer in the second region is removed, and removing the polysilicon layer in the first region and the second region at a third removal rate and a fourth removal rate, respectively.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: William Weilun Hong, Po-Chin Nien, Ying-Tsung Chen
  • Patent number: 9773679
    Abstract: Disclosed are sulfur-containing compounds for plasma etching channel holes, gate trenches, staircase contacts, capacitor holes, contact holes, etc., in Si-containing layers on a substrate and plasma etching methods of using the same. The plasma etching compounds may provide improved selectivity between the Si-containing layers and mask material, less damage to channel region, a straight vertical profile, and reduced bowing in pattern high aspect ratio structures.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: September 26, 2017
    Assignee: American Air Liquide, Inc.
    Inventors: Rahul Gupta, Venkateswara R. Pallem, Vijay Surla, Curtis Anderson, Nathan Stafford
  • Patent number: 9716142
    Abstract: Techniques for producing stacked SiGe nanowires using a condensation process without parasitic Ge nanowires as an undesired by-product. In one aspect, a method of forming SiGe nanowires includes the steps of: forming a stack of alternating Si and SiGe layers on a wafer; patterning fins in the stack; selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape; burying the fins in an oxide material; and annealing the fins under conditions sufficient to diffuse Ge from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires. A FET device and method for formation thereof are also provided.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: July 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Xin Miao
  • Patent number: 9576809
    Abstract: Methods of selectively etching silicon relative to silicon germanium are described. The methods include a remote plasma etch using plasma effluents formed from a fluorine-containing precursor and a hydrogen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the silicon. The plasmas effluents react with exposed surfaces and selectively remove silicon while very slowly removing other exposed materials. The methods are useful for removing Si(1-X)GeX faster than Si(1-Y)GeY, for X<Y. In some embodiments, the silicon germanium etch selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: February 21, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Mikhail Korolik, Nitin K. Ingle, Jingchun Zhang, Anchuan Wang, Jie Liu
  • Patent number: 9576812
    Abstract: Provided is a method of creating structure profiles on a substrate using faceting and passivation layers. A first plasma etch process performed generating a faceted sidewall and a desired inflection point; a second plasma etch process is performed using an oxygen, nitrogen, or combined oxygen and nitrogen plasma, generating a passivation layer; and a third plasma etch process using operating variables of an etch chemistry on the faceted sidewall and the passivation layer to induce differential etch rates to achieve a breakthrough on near-horizontal surfaces of the structure, wherein the third plasma etch used is configured to produce a target sidewall profile on the substrate down to the underlying stop layer. Selected two or more plasma etch variables are controlled in the performance of the first plasma etch process, the second plasma etch process, and/or the third plasma etch process in order to achieve target sidewall profile objectives.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: February 21, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Elliott Franke, Vinayak Rastogi, Akiteru Ko, Kiyohito Ito
  • Patent number: 9564338
    Abstract: A method of etching exposed silicon on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with a hydrogen-containing precursor. The combination reacts with the patterned heterogeneous structures to remove an exposed silicon portion faster than a second exposed portion. The silicon selectivity results from the presence of an ion suppressor positioned between the remote plasma and the substrate processing region. The methods may be used to selectively remove silicon faster than silicon oxide, silicon nitride and a variety of metal-containing materials. The methods may be used to remove small etch amounts in a controlled manner and may result in an extremely smooth silicon surface.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: February 7, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jingchun Zhang, Hanshen Zhang
  • Patent number: 9443756
    Abstract: A method of forming a substrate opening includes forming a plurality of side-by-side openings in a substrate. At least some of immediately adjacent side-by-side openings are formed in the substrate to different depths relative one another. Walls that are laterally between the side-by-side openings are removed to form a larger opening having a non-vertical sidewall surface where the walls were removed in at least one straight-line vertical cross-section that passes through the sidewall surface orthogonally to the removed walls.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: September 13, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Mark Kiehlbauch
  • Patent number: 9343353
    Abstract: Disclosed is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure comprises a first portion of a trench extending through the top semiconductor layer and through a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a second portion of the trench, having sloped sidewalls, extends into the handle wafer. The sloped sidewalls are amorphized by an implant, for example, Xenon or Argon, to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: May 17, 2016
    Assignee: Newport Fab, LLC
    Inventors: Paul D. Hurwitz, Robert L. Zwingman
  • Patent number: 9337292
    Abstract: A semiconductor device with a very high aspect ratio contact has a deep trench in the substrate. A dielectric liner is formed on sidewalls and a bottom of the deep trench. A contact opening is formed through the dielectric liner at the bottom of the deep trench to expose the substrate, leaving the dielectric liner on the sidewalls. Electrically conductive material is formed in the deep trench to provide the very high aspect ratio contact to the substrate through the contact opening.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: May 10, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Abbas Ali
  • Patent number: 9114666
    Abstract: Methods and apparatus for processing a substrate in a multi-frequency plasma processing chamber are disclosed. The base RF signal pulses between a high power level and a low power level. Each of the non-base RF generators, responsive to a control signal, proactively switches between a first predefined power level and a second predefined power level as the base RF signal pulses. Alternatively or additionally, each of the non-base RF generators, responsive to a control signal, proactively switches between a first predefined RF frequency and a second predefined RF frequency as the base RF signal pulses. Techniques are disclosed for ascertaining in advance of production time the first and second predefined power levels and/or the first and second predefined RF frequencies for the non-base RF signals.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: August 25, 2015
    Assignee: Lam Research Corporation
    Inventors: John C. Valcore, Jr., Bradford J. Lyndaker
  • Patent number: 9105587
    Abstract: Methods of forming a semiconductor device structure and sulfur dioxide etch chemistries. The methods and chemistries, which may be plasma chemistries, include use of sulfur dioxide and a halogen-based compound to form a trimmed pattern of a patterning material, such as a resist material, at a critical dimension with low feature width roughness, with low space width roughness, without excessive height loss, and without substantial irregularities in the elevational profile, as compared to trimmed features formed using conventional chemistries and trimming methods.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: August 11, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Guangjun Yang
  • Patent number: 9082725
    Abstract: A pattern forming method is provided for forming a pattern of a multilayer film including insulative films and electrically conductive films stacked together and having a hole formed therein on a substrate with the electrically conductive film being selectively accurately indented from an inner peripheral surface of the hole. The pattern forming method includes the steps of: alternately stacking at least two insulative films and at least two polysilicon films on a substrate to form a multilayer film including the at least two insulative films and the at least two polysilicon films; forming a hole extending through the at least two insulative films and the at least two polysilicon films in the multilayer film; and selectively etching the polysilicon films from a side wall of the hole through isotropic etching by feeding into the hole an etching gas prepared by diluting fluorine-containing halogen gas with an inert gas.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: July 14, 2015
    Assignees: SCREEN Holdings Co., Ltd., Central Glass Company, Limited
    Inventors: Masahiro Kimura, Tomonori Umezaki, Akiou Kikuchi
  • Patent number: 9034772
    Abstract: A method of etching a substrate by plasma via a mask having a predetermined pattern at back of a silicon layer of the substrate, a semiconductor device being formed at front of which supported by a support substrate, includes a main etching step in which plasma is generated by supplying a process gas including a mixed gas whose flow ratio of fluorine compound gas, oxygen gas and silicon fluoride gas is 2:1:1.5 or a process gas including a mixed gas in which at least the ratio of one of the oxygen gas and the silicon fluoride gas, using the fluorine compound gas as a standard, is larger than the above ratio, and the substrate is etched by the plasma; and an over etching step in which the substrate is further etched by plasma while applying a high frequency for bias whose frequency is less than or equal to 400 kHz.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: May 19, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koji Maruyama, Mikio Yamamoto
  • Publication number: 20150126041
    Abstract: Methods for etching silicon using hydrogen radicals in a hot wire chemical vapor deposition process are provided herein. In some embodiments, a method of processing a substrate having a crystalline silicon layer atop the substrate and a patterned masking layer atop the crystalline silicon layer exposing portions of the crystalline silicon layer; the method may include (a) exposing the substrate to a plasma formed from an inert gas wherein ions from the plasma amorphize a first part of the exposed portions of the crystalline silicon layer; and (b) exposing the substrate to hydrogen radicals generated from a process gas comprising a hydrogen-containing gas in a hot wire chemical vapor deposition (HWCVD) process chamber to etch the amorphized first part of the exposed portion of the crystalline silicon layer.
    Type: Application
    Filed: November 5, 2014
    Publication date: May 7, 2015
    Inventors: SUKTI CHATTERJEE, SRINIVAS D. NEMANI
  • Publication number: 20150126039
    Abstract: Methods of selectively etching silicon relative to silicon germanium are described. The methods include a remote plasma etch using plasma effluents formed from a fluorine-containing precursor and a hydrogen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the silicon. The plasmas effluents react with exposed surfaces and selectively remove silicon while very slowly removing other exposed materials. The methods are useful for removing Si(1-X)GeX faster than Si(1-Y)GeY, for X<Y. In some embodiments, the silicon germanium etch selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region.
    Type: Application
    Filed: May 5, 2014
    Publication date: May 7, 2015
    Inventors: Mikhail Korolik, Nitin K. Ingle, Jingchun Zhang, Anchuan Wang, Jie Liu
  • Publication number: 20150118858
    Abstract: In one embodiment of the present invention, an etching method for a substrate to be processed comprises: (a1) a step in which etchant gas is supplied into a processing container than accommodates a substrate to be processed; (b1) a step in which the inside of the processing container is evacuated; (c1) a step in which a noble gas is supplied into the processing container; and (d1) a step in which microwaves are supplied into the processing container so as to excite the plasma of the noble gas inside the processing container. The sequential process including the step of supplying the etchant of supplying the etchant gas, the evacuating step, the step of supplying the noble gas, and the step of exciting the plasma of the noble gas may be repeated.
    Type: Application
    Filed: April 10, 2013
    Publication date: April 30, 2015
    Inventor: Hiroyuki Takaba
  • Patent number: 9017561
    Abstract: A piezo-resistive MEMS resonator comprising an anchor, a resonator mounted on the anchor, an actuator mounted to apply an electrostatic force on the resonator and a piezo-resistive read-out means comprising a nanowire coupled to the resonator.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: April 28, 2015
    Assignee: NXP, B.V.
    Inventors: Gerhard Koops, Jozef Thomas Martinus van Beek
  • Publication number: 20150099345
    Abstract: Embodiments of methods for forming features in a silicon containing layer of a substrate disposed on a substrate support are provided herein. In some embodiments, a method for forming features in a silicon containing layer of a substrate disposed on a substrate support in a processing volume of a process chamber includes: exposing the substrate to a first plasma formed from a first process gas while providing a bias power to the substrate support, wherein the first process gas comprises one or more of a chlorine-containing gas or a bromine containing gas; and exposing the substrate to a second plasma formed from a second process gas while no bias power is provided to the substrate support, wherein the second process gas comprises one or more of an oxygen-containing gas or nitrogen gas, and wherein a source power provided to form the first plasma and the second plasma is continuously provided.
    Type: Application
    Filed: October 3, 2014
    Publication date: April 9, 2015
    Inventors: BYUNGKOOK KONG, HOON SANG LEE, JINSU KIM, HO JEONG KIM, XIAOSONG JI, HUN SANG KIM, JINHAN CHOI
  • Patent number: 8999184
    Abstract: A method for forming via holes in an etch layer disposed below a patterned organic mask with a plurality of patterned via holes is provided. The patterned organic mask is treated by flowing a treatment gas comprising H2. A plasma is formed from the treatment gas. The patterned via holes are rounded to form patterned rounded via holes by exposing the patterned via holes to the plasma. The flow of the treatment gas is stopped. The plurality of patterned rounded via holes are transferred into the etch layer.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: April 7, 2015
    Assignee: Lam Research Corporation
    Inventors: Ming-Shu Kuo, Siyi Li, Yifeng Zhou, Ratndeep Srivastava, Tae Won Kim, Gowri Kamarthy
  • Patent number: 8999177
    Abstract: Out-of-plane microneedle manufacturing process comprising the simultaneous creation of a network of microneedles and the creation of a polygonal shaped hat (2) above each microneedle (1) under formation, said process comprising the following steps: providing bridges (3) between the hats (3), maintaining the bridges (3) during the remaining microneedle manufacturing steps, removing the bridges (3), together with the hats (2), when the microneedles (1) are formed.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: April 7, 2015
    Assignee: Debiotech S.A.
    Inventors: Astrid Cachemaille, Francois Cannehan
  • Patent number: 8999105
    Abstract: An etch mask is formed on a substrate. The substrate is positioned in an enclosure configured to shield an interior of the enclosure from electromagnetic fields exterior to the enclosure; and the substrate is etched in the enclosure, including removing a portion of the substrate to form a structure having at least a portion that is isolated and/or suspended over the substrate.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: April 7, 2015
    Assignee: President and Fellows of Harvard College
    Inventors: Marko Loncar, Mikhail D. Lukin, Michael J. Burek, Nathalie de Leon, Brendan Shields
  • Patent number: 8987141
    Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 24, 2015
    Assignee: Institute of Semiconductors, Chinese Academy of Sciences
    Inventors: Xuliang Zhou, Hongyan Yu, Shiyan Li, Jiaoqing Pan, Wei Wang
  • Patent number: 8975137
    Abstract: A process of forming a slit in a substrate is provided. A mask layer is formed on a substrate, wherein the mask layer does not include carbon. An etching process is performed to be substrate by using the mask layer as a mask, so as to form a slit in the substrate. The etching gas includes Cl2, CF4 and CHF3, a molar ratio of CF4 to CHF3 is about 0.5-0.8, and a molar ratio of F to Cl is about 0.4-0.8, for example. Further, the step of performing the etching process simultaneously removes the mask layer.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: March 10, 2015
    Assignee: Nanya Technology Corporation
    Inventors: Wen-Chieh Wang, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8975188
    Abstract: A plasma etching method is provided for forming a hole using a first processing gas to etch a silicon layer of a substrate to be processed including a silicon oxide film that is formed into a predetermined pattern. The method includes a first depositing step (S11) of depositing a protective film on a surface of the silicon oxide film using a second processing gas containing carbon monoxide gas, a first etching step (S12) of etching the silicon layer using the first processing gas, a second depositing step (S13) of depositing the protective film on a side wall of a hole etched by the first etching step using the second processing gas, and a second etching step (S14) of further etching the silicon layer using the first processing gas. The second depositing step (S13) and the second etching step (S14) are alternately repeated at least two times each.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: March 10, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Yusuke Hirayama, Kazuhito Tohnoe
  • Patent number: 8975191
    Abstract: There is provided a plasma etching method including a first process of etching an intermediate layer, which contains silicon and nitrogen and is positioned below a resist mask formed on a surface of a substrate, to cause a silicon layer positioned below the intermediate layer to be exposed through the resist mask and the intermediate layer, a second process of subsequently supplying a chlorine gas to the substrate to cause a reaction product to attach onto sidewalls of opening portions of the resist mask and the intermediate layer, and a third process of etching a portion of the silicon layer corresponding to the opening portion of the intermediate layer using a process gas containing sulfur and fluorine to form a recess in the silicon layer.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: March 10, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhito Tohnoe, Yusuke Hirayama, Yasuyoshi Ishiyama, Wataru Hashizume
  • Patent number: 8946076
    Abstract: Some embodiments include methods of forming vertically-stacked memory cells. An opening is formed to extend partially through a stack of alternating electrically insulative levels and electrically conductive levels. A liner is formed along sidewalls of the opening, and then the stack is etched to extend the opening. The liner is at least partially consumed during the etch and forms passivation material. Three zones occur during the etch, with one of the zones being an upper zone of the opening protected by the liner, another of the zones being an intermediate zone of the opening protected by passivation material but not the liner, and another of the zones being a lower zone of the opening which is not protected by either passivation material or the liner. Cavities are formed to extend into the electrically conductive levels along sidewalls of the opening. Charge blocking dielectric and charge-storage structures are formed within the cavities.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Aaron R. Wilson
  • Patent number: 8937019
    Abstract: Techniques for forming a three dimensional (3D) feature on a substrate are disclosed. In one exemplary embodiment, the technique may be realized as a method comprising: forming a resist structure on the substrate, the resist structure having a first resist portion with a first thickness, a second resist portion with a second thickness, and a third resist portion with a third thickness, where the first thickness may be less than the second thickness, and where the second thickness may be less than the third thickness; implanting charged particles into the substrate through the first and second resist portions and forming an implanted region in the substrate; and etching the substrate to form the 3D feature on the substrate.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: January 20, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Jonathan G. England, Patrick M. Martin, David Cox
  • Patent number: 8932947
    Abstract: Embodiments of the present invention provide methods to etching a recess channel in a semiconductor substrate, for example, a silicon containing material. In one embodiment, a method of forming a recess structure in a semiconductor substrate includes transferring a silicon substrate into a processing chamber having a patterned photoresist layer disposed thereon exposing a portion of the substrate, providing an etching gas mixture including a halogen containing gas and a Cl2 gas into the processing chamber, supplying a RF source power to form a plasma from the etching gas mixture, supplying a pulsed RF bias power in the etching gas mixture, and etching the portion of the silicon substrate exposed through the patterned photoresist layer in the presence of the plasma.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: January 13, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Joo Won Han, Kee Young Cho, Han Soo Cho, Sang Wook Kim, Anisul H. Khan
  • Patent number: 8932959
    Abstract: Etching of a thin film stack including a lower thin film layer containing an advanced memory material is carried out in an inductively coupled plasma reactor having a dielectric RF window without exposing the lower thin film layer, and then the etch process is completed in a toroidal source plasma reactor.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: January 13, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas D. Nemani, Mang-mang Ling, Jeremiah T. Pender, Kartik Ramaswamy, Andrew Nguyen, Sergey G. Belostotskiy, Sumit Agarwal
  • Patent number: 8927436
    Abstract: The present invention relates to a method for forming a trench that can remove residual particles in a trench using a metal mask, a method for forming a metal wire, and a method for manufacturing a thin film transistor array panel. The method for forming a trench includes: forming a first insulating layer on a substrate; forming a first metal layer on the first insulating layer; forming an opening by patterning the first metal layer; forming a trench by dry-etching the first insulating layer using the patterned first metal layer as a mask; and wet-etching the substrate. The dry-etching is performed using a main etching gas and a first auxiliary etching gas, and the first auxiliary etching gas includes argon.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: January 6, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dae Ho Kim, Bong-Kyun Kim, Yong-Hwan Ryu, Hong Sick Park, Wang Woo Lee, Shin Il Choi
  • Publication number: 20150004796
    Abstract: In some embodiments, a method of forming a three dimensional NAND structure atop a substrate may include providing to a process chamber a substrate having alternating nitride layers and oxide layers or alternating polycrystalline silicon layers and oxide layers formed atop the substrate and a photoresist layer formed atop the alternating layers; etching the photoresist layer to expose at least a portion of the alternating nitride layers and oxide layers or alternating polycrystalline silicon layers and oxide layers; providing a process gas comprising sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), and oxygen (O2) to the process chamber; providing an RF power of about 4 kW to about 6 kW to an RF coil to ignite the process gas to form a plasma; and etching through a desired number of the alternating layers to form a feature of a NAND structure.
    Type: Application
    Filed: June 24, 2014
    Publication date: January 1, 2015
    Inventors: SANG WOOK KIM, HAN SOO CHO, JOO WON HAN, KEE YOUNG CHO, KUAN-TING LIU, ANISUL KHAN
  • Patent number: 8921136
    Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Neng-Kuo Chen, Shao-Ming Yu, Gin-Chen Huang, Chia-Jung Hsu, Sey-Ping Sun, Clement Hsingjen Wann
  • Publication number: 20140377959
    Abstract: In some embodiments, methods for forming a three dimensional NAND structure include providing to a process chamber a substrate having alternating nitride layers and oxide layers or alternating polycrystalline silicon consisting layers and oxide layers formed atop the substrate and a photoresist layer formed atop the alternating layers; etching the photoresist layer to expose at least a portion of the alternating layers; providing a process gas comprising sulfur hexafluoride and oxygen to the process chamber; providing RF power of about 4 kW to about 6 kW to a first inductive RF coil and a second inductive RF coil disposed proximate the process chamber to ignite the process gas to form a plasma, wherein a current flowing through the first inductive RF coil is out of phase with RF current flowing through the second inductive RF coil; and etching through a desired number of the alternating layers to form a feature.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 25, 2014
    Inventors: HAN SOO CHO, SANG WOOK KIM, JOO WON HAN, KEE YOUNG CHO, ANISUL H. KHAN
  • Patent number: 8916477
    Abstract: Provided are methods and systems for removing polysilicon on a wafer. A wafer can include a polysilicon layer and an exposed nitride and/or oxide structure. An etchant with a hydrogen-based species, such as hydrogen gas, and a fluorine-based species, such as nitrogen trifluoride, can be introduced. The hydrogen-based species and the fluorine-based species can be activated with a remote plasma source. The layer of polysilicon on the wafer can be removed at a selectivity over the exposed nitride and/or oxide structure that is greater than about 500:1.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: December 23, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Bayu Thedjoisworo, Jack Kuo, David Cheung, Joon Park
  • Patent number: 8906809
    Abstract: A multi-chip electronic package and methods of manufacture are provided. The structure includes a lid encapsulating at least one chip mounted on a chip carrier; at least one seal shim fixed between the lid and the chip carrier, the at least one seal shim forming a gap between pistons of the lid and respective ones of the chips; and thermal interface material within the gap and contacting the pistons of the lid and respective ones of the chips.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Beaumier, Steven P. Ostrander, Kamal K. Sikka, Hilton T. Toy, Jeffrey A. Zitz
  • Patent number: 8906772
    Abstract: A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: December 9, 2014
    Assignee: UChicago Argonne, LLC
    Inventor: Anirudha V. Sumant
  • Publication number: 20140357056
    Abstract: A method of forming a ?-shaped trench is disclosed. The method includes: providing a silicon substrate; and performing a plasma etching process to form a ?-shaped trench in the silicon substrate. The plasma etching process includes: etching the silicon substrate using a first plasma etching gas including a sulphur-containing fluoride; and etching the silicon substrate using a second plasma etching gas including a sulphur-containing fluoride and a polymer gas. A method of forming a semiconductor device is also disclosed.
    Type: Application
    Filed: November 27, 2013
    Publication date: December 4, 2014
    Applicant: Shanghai Huali Microelectronics Corporation
    Inventors: Quanbo Li, Yu Zhang, Jun Huang, Shu Koon Pang
  • Publication number: 20140338744
    Abstract: The invention relates to a process for texturing the surface of a silicon substrate, comprising a step of exposing said surface to an MDECR plasma generated, at least from argon, using between 1.5 W/cm2 and 6.5 W/cm2 of plasma power in a matrix distributed electron cyclotron resonance plasma source, the substrate bias being between 100 V and 300 V.
    Type: Application
    Filed: December 20, 2012
    Publication date: November 20, 2014
    Inventors: Nada Habka, Pavel Bulkin, Pere Roca i Cabarrocas
  • Patent number: 8871105
    Abstract: A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: October 28, 2014
    Assignee: Lam Research Corporation
    Inventors: Jaroslaw W. Winniczek, Frank Y. Lin, Alan J. Miller, Qing Xu, Seongjun Heo, Jin Hwan Ham, Sang Joon Yoon, Camelia Rusu
  • Publication number: 20140308816
    Abstract: Methods of etching exposed silicon on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and a hydrogen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon while very slowly removing other exposed materials. The silicon selectivity results, in part, from a preponderance of hydrogen-containing precursor in the remote plasma which hydrogen terminates surfaces on the patterned heterogeneous structures. A much lower flow of the fluorine-containing precursor progressively substitutes fluorine for hydrogen on the hydrogen-terminated silicon thereby selectively removing silicon from exposed regions of silicon.
    Type: Application
    Filed: June 25, 2014
    Publication date: October 16, 2014
    Inventors: Anchuan Wang, Jingchun Zhang, Nitin K. Ingle, Young S. Lee
  • Publication number: 20140302683
    Abstract: The invention is directed to providing a dry etching agent having little effect on the global environment but having the required performance. Provided is a dry etching agent containing, each at a specific vol %: (A) a fluorine-containing unsaturated hydrocarbon represented by the formula CaFbHc (in the formula, a, b and c are each positive integers and satisfy the correlations of 2?a?5, c<b?1, 2a+2>b+c and b?a+c, excluding the case where a=3, b=4 or c=2); (B) at least one kind of gas selected from the group consisting of O2, O3, CO, CO2, COCl2, COF2, F2, NF3, Cl2, Br2, I2, and YFn (where Y is Cl, Br or I and n is an integer of 1 to 5); and (C) at least one kind of gas selected from the group consisting of N2, He, Ar, Ne, Xe, and Kr.
    Type: Application
    Filed: June 13, 2012
    Publication date: October 9, 2014
    Applicant: Central Glass Company, Limited
    Inventors: Akiou Kikuchi, Tomonori Umezaki, Yasuo Hibino, Isamu Mori, Satoru Okamoto