Silicon Patents (Class 438/719)
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Patent number: 8372752Abstract: Disclosed herein is a method for fabricating an ultra fine nanowire, which relates to a manufacturing technology of a microelectronic semiconductor transistor. This method obtains a suspended ultra fine nanowire base on a combination of a mask blocking oxidation process and a stepwise oxidation process. A diameter of the suspended ultra fine nanowire fabricated by this method is precisely controlled to 20 nm by controlling a thickness of a deposited silicon nitride film and a time and temperature of the two oxidation process. Since a speed of a dry oxidation process is slower, the size of the final nanowire may be precisely controlled. This method can be used to fabricate an ultra fine nanowire with a lower cost and a higher applicability.Type: GrantFiled: July 6, 2012Date of Patent: February 12, 2013Assignee: Peking UniversityInventors: Ru Huang, Shuai Sun, Yujie Al, Jiewen Fan, Runsheng Wang, Xiaoyan Xu
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Patent number: 8372756Abstract: A process for selectively etching a material comprising SiO2 over silicon, the method comprising the steps of: placing a silicon substrate comprising a layer of a material comprising SiO2 within a reactor chamber equipped with an energy source; creating a vacuum within the chamber; introducing into the reactor chamber a reactive gas mixture comprising a fluorine compound, a polymerizable fluorocarbon, and an inert gas, wherein the reactive gas mixture is substantially free of added oxygen; activating the energy source to form a plasma activated reactive etching gas mixture within the chamber; and selectively etching the material comprising SiO2 preferentially to the silicon substrate.Type: GrantFiled: July 16, 2009Date of Patent: February 12, 2013Assignee: Air Products and Chemicals, Inc.Inventors: Glenn Michael Mitchell, Stephen Andrew Motika, Andrew David Johnson
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Publication number: 20130029492Abstract: A plasma processing method and a plasma processing apparatus in which a stable process region can be ensured in a wide range, from low microwave power to high microwave power. The plasma processing method includes making production of plasma easy in a region in which production of plasma by continuous discharge is difficult, and plasma-processing an object to be processed, with the generated plasma, wherein the plasma is produced by pulsed discharge in which ON and OFF are repeated, radio-frequency power for producing the pulsed discharge, during an ON period, is a power to facilitate production of plasma by continuous discharge, and a duty ratio of the pulsed discharge is controlled so that an average power of the radio-frequency power per cycle is power in the region in which production of plasma by continuous discharge is difficult.Type: ApplicationFiled: February 1, 2012Publication date: January 31, 2013Inventors: Yoshiharu INOUE, Tetsuo ONO, Michikazu MORIMOTO, Masaki FUJII, Masakazu MIYAJI
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Patent number: 8349639Abstract: A method for manufacturing an image sensor includes forming circuitry including a metal line over a semiconductor substrate, forming a photodiode over the metal line, and forming a contact plug in the photodiode such that the contact plug is connected to the metal line. The forming of the contact plug includes performing a first etch process to etch a portion of the photodiode, and performing a second etch process to expose a portion of the metal line by using a byproduct generated in etching, to form a via hole for the contact plug in the photodiode.Type: GrantFiled: November 9, 2009Date of Patent: January 8, 2013Assignee: Dongbu HiTek Co., Ltd.Inventor: Ki-Jun Yun
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Publication number: 20120309204Abstract: A two piece ceramic showerhead includes upper and lower plates which deliver process gas to an inductively coupled plasma processing chamber. The upper plate overlies the lower plate and includes radially extending gas passages which extend inwardly from an outer periphery of the upper plate, axially extending gas passages in fluid communication with the radially extending gas passages and an annular recess forming a plenum between the upper and lower plates. The lower plate includes axially extending gas holes in fluid communication with the plenum. The upper plate can include eight radially extending gas passages evenly spaced around the periphery of the upper plate and the lower plate can include inner and outer rows of gas holes. The two piece ceramic showerhead forms a dielectric window of the chamber through which radiofrequency energy generated by an antenna is coupled into the chamber.Type: ApplicationFiled: May 31, 2011Publication date: December 6, 2012Applicant: Lam Research CorporationInventors: Michael Kang, Alex Paterson, Ian J. Kenworthy
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Patent number: 8318605Abstract: Formation of BPSG surface defects upon exposure to atmosphere is prevented by a plasma treatment method for converting boron and/or phosphorus materials separated from silicon near the surface of the doped glass layer to gas phase compounds. The treatment plasma is generated from a treatment process gas containing one of (a) a fluorine compound or (b) a hydrogen compound.Type: GrantFiled: July 15, 2008Date of Patent: November 27, 2012Assignee: Applied Materials, Inc.Inventors: Chien-Teh Kao, Haichun Yang, Xinliang Lu, Mei Chang
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Patent number: 8319295Abstract: A new, effective and cost-efficient method of introducing Fluorine into Hf-based dielectric gate stacks of planar or multi-gate devices (MuGFET), resulting in a significant improvement in both Negative and Positive Bias Temperature Instabilities (NBTI and PBTI) is provided. The new method uses an SF6 based metal gate etch chemistry for the introduction of Fluorine, which after a thermal budget within the standard process flow, results in excellent F passivation of the interfaces. A key advantage of the method is that it uses the metal gate etch for F introduction, requiring no extra implantations or treatments. In addition to the significant BTI improvement with the novel method, a better Vth control and increased drive current on MuGFET devices is achieved.Type: GrantFiled: January 9, 2008Date of Patent: November 27, 2012Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&DInventors: Nadine Collaert, Paul Zimmerman, Marc Demand, Werner Boullart, Adelina K. Shickova
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Patent number: 8298955Abstract: This invention relates to a method for conducting an etching process which uses a plasma of a process gas. This etching process is conducted on a wafer W including a substrate 101, an underlying film 102, 103 formed on the substrate, and a film 104 to be etched that is formed on the underlying film. A main etching gas formed up of a chlorine-containing gas and an oxygen-containing gas, and a nitrogen-containing gas are used as the process gas. In this etching method, etching is conducted under a condition that an N2+/N2 intensity ratio of N2+ to N2, derived from emission spectra of the plasma, is at least 0.6.Type: GrantFiled: March 13, 2007Date of Patent: October 30, 2012Assignee: Tokyo Electron LimitedInventor: Tetsuya Nishizuka
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Patent number: 8298959Abstract: Embodiments of the invention relate to a substrate etching method and apparatus. In one embodiment, a method for etching a substrate in a plasma etch reactor is provided that includes a) depositing a polymer on a substrate in an etch reactor, b) etching the substrate using a gas mixture including a fluorine-containing gas and oxygen in the etch reactor, c) etching a silicon-containing layer the substrate using a fluorine-containing gas without mixing oxygen in the etch reactor, and d) repeating a), b) and c) until an endpoint of a feature etched into the silicon-containing layer is reached.Type: GrantFiled: May 24, 2010Date of Patent: October 30, 2012Assignee: Applied Materials, Inc.Inventor: Alan Cheshire
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Patent number: 8293554Abstract: A luminous device and a method of manufacturing the luminous device are provided. The luminous device includes a light emitting layer and first and second electrodes connected to the light emitting layer. The light emitting layer is a strained nanowire.Type: GrantFiled: September 16, 2009Date of Patent: October 23, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-ha Hong, Sung-hoon Lee, Jong-seob Kim, Jai-kwang Shin
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Patent number: 8283255Abstract: A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.Type: GrantFiled: May 24, 2007Date of Patent: October 9, 2012Assignee: Lam Research CorporationInventors: Sangjun Cho, Tom Choi, Taejoon Han, Sean Kang, Prabhakara Gopaladasu, Bi-Ming Yen
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Patent number: 8277667Abstract: A magnetic element and its manufacturing method are provided. A magnetic element includes an actuation part having a first surface and a second surface, a torsion bar connected to the actuation part, and a frame connected to the first torsion bar, wherein the first surface of the actuation part is an uneven surface. The manufacturing method of the magnetic element starts with forming an passivation layer on a substrate and defining a special area by the mask method, then continues with forming the adhesion layer and electroplate-initializing layer on the substrate sequentially. The photoresist layer are formed and the magnetic-inductive material is electroformed on the electroplate area. Finally, the substrate is etched and the passivation layer is removed to obtain the magnetic element. The manufacturing method of magnetic element of the present invention can be applied in the microelectromechanical system field and other categories.Type: GrantFiled: January 14, 2008Date of Patent: October 2, 2012Assignee: National Tsing Hua UniversityInventors: Hsueh-An Yang, Weileun Fang, Tsung-Lin Tang
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Patent number: 8278222Abstract: This invention relates to a process for selective removal of materials, such as: silicon, molybdenum, tungsten, titanium, zirconium, hafnium, vanadium, tantalum, niobium, boron, phosphorus, germanium, arsenic, and mixtures thereof, from silicon dioxide, silicon nitride, nickel, aluminum, TiNi alloy, photoresist, phosphosilicate glass, boron phosphosilicate glass, polyimides, gold, copper, platinum, chromium, aluminum oxide, silicon carbide and mixtures thereof. The process is related to the important applications in the cleaning or etching process for semiconductor deposition chambers and semiconductor tools, devices in a micro electro mechanical system (MEMS), and ion implantation systems. Methods of forming XeF2 by reacting Xe with a fluorine containing chemical are also provided, where the fluorine containing chemical is selected from the group consisting of F2, NF3, C2F6, CF4, C3F8, SF6, a plasma containing F atoms generated from an upstream plasma generator and mixtures thereof.Type: GrantFiled: January 27, 2009Date of Patent: October 2, 2012Assignee: Air Products and Chemicals, Inc.Inventors: Dingjun Wu, Eugene Joseph Karwacki, Jr., Anupama Mallikarjunan, Andrew David Johnson
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Publication number: 20120214315Abstract: In a substrate processing method, a polysilicon layer 38 on a wafer W is etched with a bromine cation 45a and a bromine radical 45b in plasma generated from a processing gas containing a hydrogen bromide gas, an oxygen gas, and a nitrogen trifluoride gas, and then, is ashed with an oxygen radical 46 and a nitrogen radical 47 in plasma generated from a processing gas containing an oxygen gas and a nitrogen gas. Thereafter, the polysilicon layer 38 is etched with a fluorine cation 48a and a fluorine radical 48b in plasma generated from a processing gas containing an argon gas and a nitrogen trifluoride gas. While the polysilicon layer 38 is ashed, an oxidation process is performed on a silicon bromide generated by etching the polysilicon layer 38 with the bromine cation 45a.Type: ApplicationFiled: February 20, 2012Publication date: August 23, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Eiichi Nishimura, Takashi Sone, Fumiko Yamashita
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Patent number: 8246846Abstract: A method for fabricating integrated MEMS switches and filters includes forming cavities in a silicon substrate, metalizing a first pattern on a quartz substrate to form first switch and filter elements, bonding the quartz substrate to the silicon substrate so that the first switch and filter elements are located within one of the cavities, thinning the quartz substrate, forming conductive vias in the quartz substrate, metalizing a second pattern on a second surface of the quartz substrate to form second switch and filter elements, etching the quartz substrate to separate MEMS switches from filters, forming protrusions on a host substrate, metalizing a third metal pattern on the host substrate to form metal anchors and third switch elements, compression bonding the metal anchors on the host substrate to second switch and filter elements, forming signal lines to integrate the MEMS switches and filters and removing the silicon substrate.Type: GrantFiled: September 24, 2010Date of Patent: August 21, 2012Assignee: HRL Laboratories, LLCInventors: David T. Chang, Tsung-Yuan Hsu
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Patent number: 8236701Abstract: A plasma processing apparatus includes a processing chamber arranged in a vacuum vessel. A wafer placed on a sample stage in the processing chamber is processed using a plasma formed in the processing chamber. Before etching the film layers provided on the wafer composed of a metal substance and an underlying oxide film or a material having a high dielectric constant, another wafer, provided on a surface thereof a film composed of a metal of the same kind as the metal substance, is processed and particles of the metal are deposited on an inner wall of said processing chamber.Type: GrantFiled: February 26, 2009Date of Patent: August 7, 2012Assignee: Hitachi High-Technologies CorporationInventors: Masahiro Sumiya, Motohiro Tanaka, Kousa Hirota
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Patent number: 8232207Abstract: In a substrate processing method of processing a substrate that includes an oxide layer as a mask layer and a silicon layer as a target layer to be processed, the silicon layer is etched while depositing a deposit on a surface of the oxide layer by a plasma generated from a mixed gas of a fluorine-based gas, a bromine-based gas, O2 gas, and SiCl4 gas to secure a thickness of the mask layer.Type: GrantFiled: December 24, 2009Date of Patent: July 31, 2012Assignee: Tokyo Electron LimitedInventors: Kosuke Ogasawara, Kiyohito Ito
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Patent number: 8231851Abstract: An exhaust gas containing a perfluoride compound (PFC) and SiF4 is conducted into a silicon remover and brought into contact with water. A reaction water supplied from a water supplying piping and air supplied from an air supplying piping are mixed with the exhaust gas exhausted from the silicon remover. The exhaust gas containing water, air, and CF4 is heated at 700° C. by a heater. The exhaust gas containing PFC is conducted to a catalyst layer filled with an alumina group catalyst. The PFC is decomposed to HF and CO2 by the catalyst. The exhaust gas containing HF and CO2 at a high temperature exhausted from the catalyst layer is cooled in a cooling apparatus. Subsequently, the exhaust gas is conducted to an acidic gas removing apparatus to remove HF. In this way, the silicon component is removed from the exhaust gas before introducing the exhaust gas into the catalyst layer.Type: GrantFiled: September 16, 2002Date of Patent: July 31, 2012Assignees: Hitachi, Ltd., Hitachi Information & Control Solutions, Ltd., Hitachi Kyowa Engineering Co., Ltd.Inventors: Kazuyoshi Irie, Toshihiro Mori, Hisao Yokoyama, Takayuki Tomiyama, Toshihide Takano, Shin Tamata, Shuichi Kanno
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Patent number: 8222154Abstract: A semiconductor device is formed by providing a substrate and forming a semiconductor-containing layer atop the substrate. A mask having a plurality of openings is then formed atop the semiconductor-containing layer, wherein adjacent openings of the plurality of openings of the mask are separated by a minimum feature dimension. Thereafter, an angled ion implantation is performed to introduce dopants to a first portion of the semiconductor-containing layer, wherein a remaining portion that is substantially free of dopants is present beneath the mask. The first portion of the semiconductor-containing layer containing the dopants is removed selective to the remaining portion of semiconductor-containing layer that is substantially free of the dopants to provide a pattern of sublithographic dimension, and the pattern is transferred into the substrate to provide a fin structure of sublithographic dimension.Type: GrantFiled: February 10, 2009Date of Patent: July 17, 2012Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Kangguo Cheng, Geng Wang
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Patent number: 8216482Abstract: A method of manufacturing an inkjet printhead includes forming a chamber layer having multiple ink chambers on a substrate. A sacrificial layer is formed and is configured to fill a space associated with the ink chambers on the chamber layer. A nozzle layer is formed on the top surfaces of the chamber layer and the sacrificial layer and having multiple nozzles. An etching mask is prepared on the bottom surface of the substrate. The etching mask has at least one linear etching pattern configured to define a portion of the substrate in which an ink feed hole is to be formed. The substrate is etched through the linear etching pattern until the sacrificial layer is exposed and a through hole is formed. The through hole defines the portion of the substrate in which the ink feed hole is to be formed. The sacrificial layer and the portion of the substrate surrounded by the through hole are removed to form the ink feed hole.Type: GrantFiled: April 23, 2009Date of Patent: July 10, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Seok Kim, Yong-Seop Yoon, Moon-Chul Lee, Yong-Won Jeong, Dong-Sik Shim, Hyung Choi
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Patent number: 8211808Abstract: A method of etching silicon-and-carbon-containing material is described and includes a SiConi™ etch in combination with a flow of reactive oxygen. The reactive oxygen may be introduced before the SiConi™ etch reducing the carbon content in the near surface region and allowing the SiConi™ etch to proceed more rapidly. Alternatively, reactive oxygen may be introduced during the SiConi™ etch further improving the effective etch rate.Type: GrantFiled: August 31, 2009Date of Patent: July 3, 2012Assignee: Applied Materials, Inc.Inventors: Kedar Sapre, Jing Tang, Linlin Wang, Abhijit Basu Mallick, Nitin Ingle
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Patent number: 8207066Abstract: The invention provides a dry etching method capable of obtaining a good profile with little side etch without receiving the restriction of a micro loading effect. A dry etching method for etching a sample having formed on the surface thereof a pattern with an isolated portion and a dense portion using plasma comprises a first etching step using an etching gas containing a CF-based gas and a nitrogen gas in which an etching rate of a dense portion of the pattern is greater than the etching rate of the isolated portion of the mask pattern, and a second etching step in which the etching rate of the isolated portion of the pattern is greater than the etching rate of the dense portion of the pattern.Type: GrantFiled: July 30, 2009Date of Patent: June 26, 2012Assignee: Hitachi High-Technologies CorporationInventors: Yoshiharu Inoue, Hiroaki Ishimura, Hitoshi Kobayashi, Masunori Ishihara, Toru Ito, Toshiaki Nishida
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Patent number: 8202744Abstract: Provided are a wafer through silicon via (TSV) forming method and equipment therefor. The wafer TSV forming method includes the operations of arranging a wafer having a front surface having a circuit area patterned thereon; recognizing locations of bond pads in the circuit area of the front surface of the wafer by using an image recognition camera, and converting the recognition of the locations into bond pad location information with respect to a back surface of the wafer; flipping the wafer; forming etching holes with middle depth in the back surface of the wafer by using a laser in a manner to match the locations of the bond pads by using the bond pad location information from the image recognition camera; and performing a plasma isotropic etching on the back surface having formed therein the etching holes with middle depth, thereby forming TSVs penetrating the bond pads.Type: GrantFiled: July 30, 2009Date of Patent: June 19, 2012Assignee: STS Semiconductor & Telecommunications Co., Ltd.Inventors: Jung Hwan Chun, Gyu Han Kim
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Publication number: 20120146194Abstract: The invention relates to a method for texturing the surface of a gaseous phase silicon substrate, and to a textured silicon substrate for a solar cell. The method includes at least a step a) of exposing the surface to an SF6/O2 radiofrequency plasma for a duration of 2 to 30 minutes in order to produce a silicon substrate having a textured surface having pyramidal structures, the SF6/O2 ratio being 2 to 10. During step a) the power density generated using the radiofrequency plasma is greater than or equal to 2500 mW/cm2, and the SF6/O2 pressure in the reaction chamber is lower than or equal to 100 mTorrs, so as to produce a silicon substrate having a textured surface having inverted pyramidal structures.Type: ApplicationFiled: August 23, 2010Publication date: June 14, 2012Applicants: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, ECOLE POLYTECHNIQUEInventors: Pere Roca I Cabarrocas, Mario Moreno, Dimitri Daineka
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Patent number: 8198103Abstract: A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks.Type: GrantFiled: July 10, 2008Date of Patent: June 12, 2012Assignee: International Business Machines CorporationInventors: Timothy J. Dalton, Wesley C. Natzle, Paul W. Pastel, Richard S. Wise, Hongwen Yan, Ying Zhang
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Patent number: 8198197Abstract: The present invention is a plasma etching method for etching a surface of a substrate in which a metal nitride film and a silicon film have been respectively formed on a first base film and a second base film that had been side-by-side arranged, with surfaces of the metal nitride film and the silicon film being exposed. At least a surface area of the silicon film is nitrided. A first etching plasma is supplied onto the surface of the substrate so as to etch the metal nitride film and to expose the first base film. A second etching plasma is supplied onto the surface of the substrate so as to etch the silicon film and to expose the second base film.Type: GrantFiled: February 6, 2009Date of Patent: June 12, 2012Assignee: Tokyo Electron LimitedInventors: Yosuke Sakao, Hiroyuki Takahashi
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Publication number: 20120138139Abstract: Systems and methods for improving surface reflectance of silicon wafers are disclosed. The systems and methods improve surface reflectance by forming a textured surface on the silicon wafer by performing surface oxidation and dry etching processes. The surface oxidation maybe performed using a dry oxygen plasma process. A dry etch process is performed to remove the oxide layer formed by the surface oxidation step and etch the Silicon layer with oxide masking. Dry etching enables black silicon formation, which minimizes or eliminates light reflection or scattering, eventually leading to higher energy conversion efficiency.Type: ApplicationFiled: November 1, 2011Publication date: June 7, 2012Applicant: INTEVAC, INC.Inventor: Young Kyu CHO
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Patent number: 8187980Abstract: An etching method for forming a groove by etching a silicon layer of a substrate by using a mask which has a first region where an opening with a first opening width is formed and a second region where an opening with a second opening width larger than the first opening width is formed, the method includes: mounting the substrate on a mounting table in a processing chamber; converting a processing gas containing Cl2 gas, HBr gas, and one of CO gas and CO2 gas into a plasma; and etching the silicon layer by the plasma.Type: GrantFiled: January 29, 2008Date of Patent: May 29, 2012Assignee: Tokyo Electron LimitedInventor: Kosuke Ogasawara
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Patent number: 8187956Abstract: A method for forming a microcrystalline semiconductor film over a base formed of a different material, which has high crystallinity in the entire film and at an interface with the base, is proposed. Further, a method for manufacturing a thin film transistor including a microcrystalline semiconductor film with high crystallinity is proposed. Furthermore, a method for manufacturing a photoelectric conversion device including a microcrystalline semiconductor film with high crystallinity is proposed. By forming crystal nuclei with high density and high crystallinity over a base film and then growing crystals in a semiconductor from the crystal nuclei, a microcrystalline semiconductor film which has high crystallinity at an interface with the base film, which has high crystallinity in crystal grains, and which has high adhesion between the adjacent crystal grains is formed.Type: GrantFiled: November 25, 2008Date of Patent: May 29, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yasuhiro Jinbo, Hidekazu Miyairi, Koji Dairiki
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Patent number: 8178444Abstract: A substrate processing method that can eliminate unevenness in the distribution of plasma. The method is for a substrate processing apparatus that has a processing chamber in which a substrate is housed, a mounting stage that is disposed in the processing chamber and on which the substrate is mounted, and an electrode plate that is disposed in the processing chamber such as to face the mounting stage, the electrode plate being made of silicon and connected to a radio-frequency power source, and carries out plasma processing on the substrate. In the plasma processing, the temperature of the electrode plate is measured, and based on the measured temperature, the temperature of the electrode plate is maintained lower than a critical temperature at which the specific resistance value of the silicon starts changing.Type: GrantFiled: February 2, 2009Date of Patent: May 15, 2012Assignee: Tokyo Electron LimitedInventors: Chishio Koshimizu, Taichi Hirano, Masanobu Honda, Shinji Himori
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Patent number: 8173547Abstract: A method and apparatus for etching a silicon layer through a patterned mask formed thereon are provided. The silicon layer is placed in an etch chamber. An etch gas comprising a fluorine containing gas and an oxygen and hydrogen containing gas is provided into the etch chamber. A plasma is generated from the etch gas and features are etched into the silicon layer using the plasma. The etch gas is then stopped. The plasma may contain OH radicals.Type: GrantFiled: October 23, 2008Date of Patent: May 8, 2012Assignee: Lam Research CorporationInventors: Jaroslaw W. Winniczek, Robert P. Chebi
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Publication number: 20120108073Abstract: A method for fabricating a semiconductor device includes forming a plurality of patterns, forming an etch target layer to gap-fill the plurality of patterns, forming an impurity region in the etch target layer, and performing an etch-back process on the etch target layer using the impurity region as an etch stop barrier.Type: ApplicationFiled: December 30, 2010Publication date: May 3, 2012Inventors: Hae-Jung LEE, Eun-Mi Kim, Kyung-Bo Ko
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Publication number: 20120100720Abstract: A method of etching a silicon layer through a patterned mask is provided. The method uses an etch chamber in which the silicon layer is placed. The method includes (a) providing the silicon layer having the patterned mask formed thereon, (b) providing an etch gas comprising a fluorine containing gas and an oxygen and hydrogen containing gas into the etch chamber in which the silicon layer has been placed, (c) generating a plasma from the etch gas, (d) etching features into the silicon layer through the patterned mask using the plasma, and (e) stopping the etch gas. The oxygen and hydrogen containing gas contains water vapor.Type: ApplicationFiled: December 28, 2011Publication date: April 26, 2012Applicant: LAM RESEARCH CORPORATIONInventors: Jaroslaw W. WINNICZEK, Robert P. CHEBI
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Publication number: 20120094500Abstract: An object of the present invention is suppressing notches in dry etching of a processing object where an etched layer made of a silicon material is formed on an etching stop layer. A substrate has an etched layer made of a silicon material on an etching stop layer. SF6/C4F8 gas, as an etching gas, is supplied to generate plasma, and a portion of the etched layer exposed through a resist mask is etched. A sidewall protection layer made of polymer is formed on a sidewall of a trench or a hole.Type: ApplicationFiled: December 23, 2011Publication date: April 19, 2012Inventors: Mitsuhiro Okune, Hiroyuki Suzuki
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Patent number: 8138096Abstract: In a plasma etching method, a substrate including an underlying film, an insulating film and a resist mask is plasma etched to thereby form a number of holes in the insulating film including a dense region and a sparse region by using a parallel plate plasma etching apparatus for applying a plasma-generating high frequency electric power to a space between an upper and a lower electrode and a biasing high frequency electric power to the lower electrode. The plasma etching method includes mounting the substrate on a mounting table; supplying a first process gas containing carbon and fluorine to form the holes in the insulating film to a depth close to the underlying film; and supplying a second process gas including an inert gas and another gas contain carbon and fluorine to have the holes reach the underlying film while applying a negative DC voltage to the upper electrode.Type: GrantFiled: February 4, 2008Date of Patent: March 20, 2012Assignee: Tokyo Electron LimitedInventor: Ryoichi Yoshida
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Patent number: 8133814Abstract: Methods are provided for fabricating a semiconductor device. One embodiment includes forming an insulator layer overlying a semiconductor substrate and depositing a layer of polycrystalline silicon overlying the insulator layer. Conductivity determining impurity ions are implanted into at least an upper portion of the layer of polycrystalline silicon. At least the upper portion of the layer of polycrystalline silicon is etched using a first anisotropic etch chemistry to expose an edge portion of the upper portion. An oxide barrier is formed on the edge portion and a further portion of the layer of polycrystalline silicon is etched using the first anisotropic etch chemistry. Then a final portion of the layer of polycrystalline silicon is etched using a second anisotropic etch chemistry.Type: GrantFiled: December 3, 2010Date of Patent: March 13, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Steffen Laufer, Gunter Grasshoff
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Publication number: 20120050751Abstract: The invention relates to controllable Fabry-Perot interferometers which are produced with micromechanical (MEMS) technology. Producing prior art interferometers includes a risk of deterioration of mirrors during the etching of the sacrificial layer (123). According to the solution according to the invention at least one layer (103, 105, 114, 116) of the mirrors is made of silicon-rich silicon nitride. In the inventive Fabry-Perot interferometer it is possible to avoid or reduce using silicon oxide in the mirror layers whereby the risk of deterioration of the mirrors is reduced. It is also possible to use mirror surfaces with higher roughness, whereby the risk of the mirrors sticking to each other is reduced.Type: ApplicationFiled: May 28, 2010Publication date: March 1, 2012Applicant: TEKNOLOGIAN TUTKIMUSKESKUS VTTInventor: Martti Blomberg
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Patent number: 8124538Abstract: A method for selectively etching a high-k dielectric layer with respect to a polysilicon material is provided. The high-k dielectric layer is partially removed by Ar sputtering, and then the high-k dielectric layer is etched using an etching gas comprising BCl3. The high-k dielectric layer and the polysilicon material may be formed on a substrate. In order to partially remove the high-k dielectric layer, a sputtering gas containing Ar is provided into an etch chamber in which the substrate is placed, a plasma is generated from the sputtering gas, and then the sputtering gas is stopped. In order to etch the high-k dielectric layer, the etching gas is provided into the etch chamber, a plasma is generated from the etching gas, and then the etching gas is stopped.Type: GrantFiled: April 10, 2009Date of Patent: February 28, 2012Assignee: Lam Research CorporationInventors: In Deog Bae, Qian Fu, Wonchul Lee, Shenjian Liu
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Patent number: 8124540Abstract: A method for forming features in a polysilicon layer is provided. A hardmask layer is formed over the polysilicon layer. A photoresist mask is formed over the hardmask layer. The hardmask layer is etched through the photoresist mask to form a patterned hardmask. The patterned hardmask is trimmed by providing a non-carbon containing trim gas comprising oxygen and a fluorine containing compound, forming a plasma from the trim gas, and trimming the hardmask. Features are etched into the polysilicon layer through the hardmask.Type: GrantFiled: November 9, 2010Date of Patent: February 28, 2012Assignee: Lam Research CorporationInventor: Tom A. Kamp
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Patent number: 8124534Abstract: A process including forming a silicon layer over a semiconductor wafer having features thereon and then selectively ion implanting in the silicon layer to form ion implanted regions. The step of selectively ion implanting is repeated as many times as necessary to obtain a predetermined number and density of features. Thereafter, the silicon layer is etched to form openings in the silicon layer that were formerly occupied by the ion implanted regions. The opened areas in the silicon layer form a mask for further processing of the semiconductor wafer.Type: GrantFiled: July 22, 2008Date of Patent: February 28, 2012Assignee: International Business Machines CorporationInventors: Jin Wallner, Thomas A. Wallner, Ying Zhang
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Publication number: 20120028383Abstract: A processing method of a silicon substrate including forming a second opening in a bottom portion of a first opening using a patterning mask having a pattern opening by plasma reactive ion etching. The reactive ion etching is performed with a shield structure formed in or on the silicon substrate, the shield structure preventing inside of the first opening from being exposed to the plasma.Type: ApplicationFiled: July 20, 2011Publication date: February 2, 2012Applicant: CANON KABUSHIKI KAISHAInventors: Atsushi Hiramoto, Masahiko Kubota, Ryoji Kanri, Akihiko Okano, Yoshiyuki Fukumoto, Atsunori Terasaki
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Patent number: 8097478Abstract: The present invention provides a method for producing a light-emitting diode, the method comprising a lamination step of forming a laminated semiconductor layer by sequentially laminating an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer onto a substrate, as well as forming a plurality of reflective p-type electrodes on top of the p-type semiconductor layer, a plating step of forming a seed layer that covers the reflective p-type electrodes and the p-type semiconductor layer, and fowling a plating layer on top of the seed layer, a removal step of removing the substrate from the n-type semiconductor layer, thereby exposing a light extraction surface of the n-type semiconductor layer, and an electrode formation step of performing dry etching of the light extraction surface of the n-type semiconductor layer using an etching gas containing the same element as a dopant element within the n-type semiconductor layer, and subsequently forming an n-type electrode on the light extraType: GrantFiled: June 26, 2008Date of Patent: January 17, 2012Assignee: Showa Denko K.K.Inventor: Takashi Hodota
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Patent number: 8093154Abstract: In one embodiment of the invention, a method for finishing or treating a silicon-containing surface is provided which includes removing contaminants and/or smoothing the surface contained on the surface by a slow etch process (e.g., about <100 ?/min). The silicon-containing surface is exposed to an etching gas that contains an etchant and a silicon source. Preferably, the etchant is chlorine gas so that a relatively low temperature (e.g., <800° C.) is used during the process. In another embodiment, a method for etching a silicon-containing surface during a fast etch process (e.g., about >100 ?/min) is provided which includes removing silicon-containing material to form a recess in a source/drain (S/D) area on the substrate. In another embodiment, a method for cleaning a process chamber is provided which includes exposing the interior surfaces with a chamber clean gas that contains an etchant and a silicon source.Type: GrantFiled: October 3, 2005Date of Patent: January 10, 2012Assignee: Applied Materials, Inc.Inventors: Ali Zojaji, Arkadii V. Samoilov
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Patent number: 8084329Abstract: In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.Type: GrantFiled: January 26, 2010Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: John C. Arnold, Xuefeng Hua, Rangarajan Jagannathan, Stefan Schmitz
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Patent number: 8084190Abstract: A layer structure and process for providing sublithographic structures are provided. A first auxiliary layer is formed over a surface of a carrier layer. A lithographically patterned second auxiliary layer structure is formed on a surface of the first auxiliary layer. The first auxiliary layer is anisotropically etched using the patterned second auxiliary layer structure as mask to form an anisotropically patterned first auxiliary layer structure. The anisotropically patterned first auxiliary layer structure is isotropically etched back using the patterned second auxiliary layer structure to remove subsections below the second auxiliary layer structure and to form an isotropically patterned first auxiliary layer structure. A mask layer is formed over the carrier layer including the subsections beneath the second auxiliary layer structure and is anisotropically etched down to the carrier layer to form the sublithographic structures.Type: GrantFiled: August 27, 2009Date of Patent: December 27, 2011Assignee: Infineon Technologies AGInventors: Martin Gutsche, Harald Seidl
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Method of forming fine patterns and manufacturing semiconductor light emitting device using the same
Patent number: 8080480Abstract: A method of forming a fine pattern begins with providing a c-plane hexagonal semiconductor crystal. A mask having a predetermined pattern is formed on the semiconductor crystal. The semiconductor crystal is dry-etched by using the mask to form a first fine pattern on the semiconductor crystal. The semiconductor crystal including the first fine pattern is wet-etched to expand the first fine pattern in a horizontal direction to form a second fine pattern. The second fine pattern obtained in the wet-etching the semiconductor crystal has a bottom surface and a sidewall that have unique crystal planes, respectively. The present fine-pattern forming process can be advantageously applied to a semiconductor light emitting device, particularly, to a phonic crystal structure required to have fine patterns or a structure using a surface plasmon resonance principle.Type: GrantFiled: September 26, 2008Date of Patent: December 20, 2011Assignee: Samsung LED Co., Ltd.Inventors: Jong Ho Lee, Moo Youn Park, Soo Ryong Hwang, Il Hyung Jung, Gwan Su Lee, Jin Ha Kim -
Publication number: 20110294300Abstract: A method of etching patterned heterogeneous silicon-containing structures is described and includes a remote plasma etch with inverted selectivity compared to existing remote plasma etches. The methods may be used to conformally trim polysilicon while removing little or no silicon oxide. More generally, silicon-containing films containing less oxygen are removed more rapidly than silicon-containing films which contain more oxygen. Other exemplary applications include trimming silicon carbon nitride films while essentially retaining silicon oxycarbide. Applications such as these are enabled by the methods presented herein and enable new process flows. These process flows are expected to become desirable for a variety of finer linewidth structures. Methods contained herein may also be used to etch silicon-containing films faster than nitrogen-and-silicon containing films having a greater concentration of nitrogen.Type: ApplicationFiled: April 18, 2011Publication date: December 1, 2011Applicant: APPLIED MATERIALS, INC.Inventors: Jingchun Zhang, Anchuan Wang, Nitin K. Ingle
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Patent number: 8048787Abstract: Provided are a semiconductor device and a method of forming the same. The method may include forming a gate dielectric layer including a plurality of elements on a substrate; supplying a specific element to the gate dielectric layer; forming a product though reacting the specific element with at least one of the plurality of elements; and removing the product.Type: GrantFiled: September 14, 2009Date of Patent: November 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sangjin Hyun, Yugyun Shin, Hagju Cho, Hyung-seok Hong
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Patent number: 8034719Abstract: To fabricate high aspect ratio metal structures, a two-layer structure is provided on a conductive layer. The two-layer structure includes a first layer adjacent the conductive layer and a second layer adjacent the first layer where the second layer is etchable by a Deep Reactive Ion Etching (DRIE) process. Using the DRIE process, at least one selected region of the second layer is completely etched away with the selected region being at least partially aligned with a region of the conductive layer such that the first layer is then exposed thereover. The first layer so-exposed is then removed to expose the region of the conductive layer thereunder. Metal is electroplated onto the exposed conductive layer and any remaining portions of the two-layer structure are then removed.Type: GrantFiled: December 8, 2005Date of Patent: October 11, 2011Assignee: The United States of America as represented by the Secretary of the NavyInventors: Daniel L. Jean, Michael Deeds, Allen Keeney
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Patent number: 8012882Abstract: In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, bow will be a large ±40 ?m to ±100 ?m. Since with that bow device fabrication by photolithography is challenging, reducing the bow to +30 ?m to ?20 ?m is the goal. The surface deflected concavely is ground to impart to it a damaged layer that has a stretching effect, making the surface become convex. The damaged layer on the surface having become convex is removed by etching, which curtails the bow. Alternatively, the convex surface on the side opposite the surface having become convex is ground to generate a damaged layer. With the concave surface having become convex due to the damaged layer, suitably etching off the damaged layer curtails the bow.Type: GrantFiled: September 26, 2008Date of Patent: September 6, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventor: Naoki Matsumoto