Silicon Nitride Patents (Class 438/724)
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Patent number: 12178032Abstract: A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.Type: GrantFiled: July 22, 2022Date of Patent: December 24, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Chun Keng, Kuo-Hsiu Hsu, Chih-Chuan Yang, Lien Jung Hung, Ping-Wei Wang
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Patent number: 11875998Abstract: A substrate processing method uses a substrate processing apparatus including a process chamber defining a processing space in the process chamber, a substrate support mounted in the process chamber to place a substrate on the substrate support, a gas sprayer for supplying a process gas onto the substrate support in the processing space, and a remote plasma generator connected to the process chamber. The method includes placing the substrate on the substrate support, continuously supplying a surface processing gas through the remote plasma generator onto the substrate, continuously supplying a purge gas onto the substrate, supplying plasma power to the remote plasma generator to activate the surface processing gas and supply the activated surface processing gas onto the substrate, and cutting off the plasma power supplied to the remote plasma generator and supplying an etching gas onto the substrate.Type: GrantFiled: December 10, 2020Date of Patent: January 16, 2024Assignee: WONIK IPS CO., LTD.Inventors: Kwang Seon Jin, Jin Sung Chun, Sang Jun Park, Byung Chul Cho, Jun Hyuck Kwon
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Patent number: 11626289Abstract: A method for forming a semiconductor structure includes providing a substrate, forming a stop layer over a surface of the substrate, forming a dielectric layer over a surface of the stop layer, forming a first opening in the dielectric layer and exposing a portion of the stop layer, modifying the portion of the stop layer exposed at a bottom of the first opening to form a modification layer, and removing the modification layer to form a second opening from the first opening.Type: GrantFiled: July 17, 2020Date of Patent: April 11, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Xi Lin, Sheng Wang
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Patent number: 11121032Abstract: A method of forming an active device having self-aligned source/drain contacts and gate contacts, including, forming an active area on a substrate, where the active area includes a device channel; forming two or more gate structures on the device channel; forming a plurality of source/drains on the active area adjacent to the two or more gate structures and device channel; forming a protective layer on the surfaces of the two or more gate structures, plurality of source/drains, and active layer; forming an interlayer dielectric layer on the protective layer; removing a portion of the interlayer dielectric and protective layer to form openings, where each opening exposes a portion of one of the plurality of source/drains; forming a source/drain contact liner in at least one of the plurality of openings; and forming a source/drain contact fill on the source/drain contact liner.Type: GrantFiled: February 26, 2019Date of Patent: September 14, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
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Patent number: 10948825Abstract: A method of processing a substrate includes: providing a substrate with a layer of photosensitive material on a surface of the substrate; and removing at least part of the photosensitive material from around an outer edge of the layer of photosensitive material so as to generate an edge, having a radial width, around the layer of photosensitive material remaining on the surface of the substrate, wherein the photosensitive material varies in thickness forming a thickness profile across the radial width and the removing is controlled so as to generate variation in the thickness profile along the length of the edge, and/or wherein the removing is controlled so as to generate a rough edge around the layer of photosensitive material remaining on the surface of the substrate.Type: GrantFiled: December 22, 2016Date of Patent: March 16, 2021Assignee: ASML NETHERLANDS B.V.Inventors: Christianus Wilhelmus Johannes Berendsen, Güneş Nakibo{hacek over (g)}lu, Daan Daniel Johannes Antonius Van Sommeren, Gijsbert Rispens, Johan Franciscus Maria Beckers, Theodorus Johannes Antonius Renckens
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Patent number: 10790133Abstract: A precleaning apparatus includes a chamber having an internal space in which a substrate is cleaned, a substrate support disposed in the chamber and configured to support the substrate, a plasma generation unit disposed in the chamber and configured to generate plasma gas, a heating unit configured to heat the substrate on the substrate support, a cleaning gas supply unit configured to supply gas for oxide etching to the internal space of the chamber, and a hydrogen gas supply unit configured to supply hydrogen gas to the internal space of the chamber.Type: GrantFiled: January 26, 2017Date of Patent: September 29, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Keum Seok Park, Sun Jung Kim, Yi Hwan Kim, Pan Kwi Park, Dong Suk Shin, Hyun Kwan Yu, Seung Hun Lee
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Patent number: 10707128Abstract: A method of forming an active device having self-aligned source/drain contacts and gate contacts, including, forming an active area on a substrate, where the active area includes a device channel; forming two or more gate structures on the device channel; forming a plurality of source/drains on the active area adjacent to the two or more gate structures and device channel; forming a protective layer on the surfaces of the two or more gate structures, plurality of source/drains, and active layer; forming an interlayer dielectric layer on the protective layer; removing a portion of the interlayer dielectric and protective layer to form openings, where each opening exposes a portion of one of the plurality of source/drains; forming a source/drain contact liner in at least one of the plurality of openings; and forming a source/drain contact fill on the source/drain contact liner.Type: GrantFiled: February 27, 2019Date of Patent: July 7, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
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Patent number: 10541332Abstract: A semiconductor device includes: a sidewall insulating film; a gate electrode; source and drain regions; a first stress film; and a second stress film.Type: GrantFiled: September 7, 2017Date of Patent: January 21, 2020Assignee: Sony CorporationInventor: Yuki Miyanami
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Patent number: 10312131Abstract: Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.Type: GrantFiled: February 16, 2017Date of Patent: June 4, 2019Assignee: Efficient Power Converson CorporationInventors: Alexander Lidow, Jianjun Cao, Robert Beach, Johan T. Strydom, Alana Nakata, Guangyuan Zhao
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Patent number: 9865474Abstract: An etching method using plasma includes generating plasma by supplying process gases to at least one remote plasma source (RPS) and applying power to the at least one RPS, and etching an etching object by supplying water (H2O) and the plasma to a process chamber.Type: GrantFiled: November 9, 2016Date of Patent: January 9, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Gon-jun Kim, Vladimir Volynets, Sang-jin An, Hee-jeon Yang, Sangheon Lee, Sung-keun Cho, Xinglong Chen, In-ho Choi
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Patent number: 9799561Abstract: A method for fabricating a semiconductor device is disclosed.Type: GrantFiled: August 17, 2016Date of Patent: October 24, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan-Hoon Park, Dong-Chan Kim, Masayuki Tomoyasu, Je-Woo Han
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Patent number: 9343327Abstract: A method of selectively etching silicon nitride from a substrate comprising a silicon nitride layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the silicon nitride layer at a higher etch rate than the reactive gas etches the silicon oxide layer.Type: GrantFiled: April 6, 2015Date of Patent: May 17, 2016Assignee: Applied Materials, Inc.Inventors: Jingchun Zhang, Anchuan Wang, Nitin Ingle
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Patent number: 9318343Abstract: Techniques herein include methods to increase etching selectivity among materials. Techniques herein include a cyclical process of etching and oxidation of a silicon nitride (SiN) spacer and silicon (such as polycrystalline silicon). This technique can increase selectivity to the silicon so that silicon is less likely to be etched or damaged while silicon nitride is etched from sidewalls. Techniques and chemistries as disclosed herein can be more selective to silicon oxide and silicon as compared to silicon nitride. An oxidizing step creates an oxide protection film on silicon surfaces that is comparatively thicker to any oxide film formed on nitride surfaces. As such, techniques here enable better removal of silicon nitride and silicon nitride spacer materials.Type: GrantFiled: June 11, 2014Date of Patent: April 19, 2016Assignee: Tokyo Electron LimitedInventors: Alok Ranjan, Blake Parkinson
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Patent number: 9209012Abstract: A method of etching silicon nitride on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and a nitrogen-and-oxygen-containing precursor. Plasma effluents from two remote plasmas are flowed into a substrate processing region where the plasma effluents react with the silicon nitride. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon nitride while very slowly removing silicon, such as polysilicon. The silicon nitride selectivity results partly from the introduction of fluorine-containing precursor and nitrogen-and-oxygen-containing precursor using distinct (but possibly overlapping) plasma pathways which may be in series or in parallel.Type: GrantFiled: September 8, 2014Date of Patent: December 8, 2015Assignee: Applied Materials, Inc.Inventors: Zhijun Chen, Zihui Li, Anchuan Wang, Nitin K. Ingle, Shankar Venkataraman
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Patent number: 9209034Abstract: In a plasma etching method for etching a metal layer of a substrate to be processed through a hard mask by using a plasma etching apparatus, a first step in which a first etching gas comprising a mixed gas of O2, CF4 and HBr is used as an etching gas, and a second step in which a second etching gas comprising a mixed gas of O2 and CF4 is used as an etching gas, are continuously and alternately repeated a plurality of times. At this time, a first high-frequency power of a first frequency and a second high-frequency power of a second frequency, which is lower than the first frequency, are applied to a lower electrode, and the first high-frequency power is applied in a pulse form.Type: GrantFiled: January 31, 2013Date of Patent: December 8, 2015Assignee: TOKYO ELECTRON LIMITEDInventors: Akinori Kitamura, Kenta Yasuda, Shunsuke Ishida
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Patent number: 9190316Abstract: A stack that includes, from bottom to top, a nitrogen-containing dielectric layer, an interconnect level dielectric material layer, and a hard mask layer is formed on a substrate. The hard mask layer and the interconnect level dielectric material layer are patterned by an etch. Employing the patterned hard mask layer as an etch mask, the nitrogen-containing dielectric layer is patterned by a break-through anisotropic etch, which employs a fluorohydrocarbon-containing plasma to break through the nitrogen-containing dielectric layer. Fluorohydrocarbon gases used to generate the fluorohydrocarbon-containing plasma generate a carbon-rich polymer residue, which interact with the nitrogen-containing dielectric layer to form volatile compounds. Plasma energy can be decreased below 100 eV to reduce damage to physically exposed surfaces of the interconnect level dielectric material layer.Type: GrantFiled: October 26, 2011Date of Patent: November 17, 2015Assignees: GLOBALFOUNDRIES U.S. 2 LLC, ZEON CORPORATIONInventors: Markus Brink, Robert L. Bruce, Sebastian U. Engelmann, Nicholas C. M. Fuller, Hiroyuki Miyazoe, Masahiro Nakamura
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Patent number: 9165765Abstract: Techniques include a plasma oxidation treatment to modify a material to a predetermined thickness around a mandrel or spacer or other structure. This plasma oxidation is then followed by a chemical oxide removal treatment. With only a portion of the structures being oxidized, or by selective masking a portion of oxidized structures, the chemical oxide removal treatment essentially shrinks only a portion of the structures, thereby yielding structures having differing critical dimensions which can function as etch masks to transfer patterns into one or more underlying layers. Accordingly, structures having differing critical dimensions can be fabricated at sub-resolution scales.Type: GrantFiled: September 9, 2014Date of Patent: October 20, 2015Assignee: Tokyo Electron LimitedInventors: Angelique D. Raley, Akiteru Ko
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Patent number: 9123654Abstract: Improved sidewall image transfer (SIT) techniques are provided. In one aspect, a SIT method includes the following steps. An oxide layer is formed on a substrate. A transfer layer is formed on a side of the oxide layer opposite the substrate. A mandrel layer is formed on a side of the transfer layer opposite the oxide layer. The mandrel layer is patterned to form at least one mandrel. Sidewall spacers are formed on opposite sides of the at least one mandrel. The at least one mandrel is removed, wherein the transfer layer covers and protects the substrate during removal of the at least one mandrel. The transfer layer is etched using the sidewall spacers as a hardmask to form a patterned transfer layer. The oxide layer and the sidewall spacers are removed from the substrate. The substrate is etched using the patterned transfer layer as a hardmask.Type: GrantFiled: February 15, 2013Date of Patent: September 1, 2015Assignee: International Business Machines CorporationInventor: Effendi Leobandung
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Patent number: 9099118Abstract: Methods of forming a write pole are disclosed. A structure comprising a bottom insulating layer and a top insulating layer is provided. A top damascene trench is formed in the top insulating layer, and a bottom damascene trench is formed in the bottom insulating layer. The bottom damascene trench and a portion of the top damascene trench are filled with a pole material. The top insulating layer and a portion of the pole material located above the bottom damascene trench are removed.Type: GrantFiled: May 26, 2009Date of Patent: August 4, 2015Assignee: Western Digital (Fremont), LLCInventors: Ronghui Zhou, Ming Jiang, Guanghong Luo, Yun-Fei Li
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Patent number: 9040423Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first area with a first poly layer and a second area with a second poly layer is provided. A nitride HM film is then deposited above the first poly layer of a first device in the first area and above the second poly layer in the second area. Afterwards, a first patterned passivation is formed on the nitride HM film in the first area to cover the nitride HM film and the first device, and a second patterned passivation is formed above the second poly layer in the second area. The second poly layer in the second area is defined by the second patterned passivation.Type: GrantFiled: July 17, 2013Date of Patent: May 26, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wan-Fang Chung, Ping-Chia Shih, Hsiang-Chen Lee, Che-Hao Chang, Jhih-Long Lin, Wei-Pin Huang, Shao-Nung Huang, Yu-Cheng Wang, Jaw-Jiun Tu, Chung-Che Huang
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Publication number: 20150099345Abstract: Embodiments of methods for forming features in a silicon containing layer of a substrate disposed on a substrate support are provided herein. In some embodiments, a method for forming features in a silicon containing layer of a substrate disposed on a substrate support in a processing volume of a process chamber includes: exposing the substrate to a first plasma formed from a first process gas while providing a bias power to the substrate support, wherein the first process gas comprises one or more of a chlorine-containing gas or a bromine containing gas; and exposing the substrate to a second plasma formed from a second process gas while no bias power is provided to the substrate support, wherein the second process gas comprises one or more of an oxygen-containing gas or nitrogen gas, and wherein a source power provided to form the first plasma and the second plasma is continuously provided.Type: ApplicationFiled: October 3, 2014Publication date: April 9, 2015Inventors: BYUNGKOOK KONG, HOON SANG LEE, JINSU KIM, HO JEONG KIM, XIAOSONG JI, HUN SANG KIM, JINHAN CHOI
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Patent number: 8999856Abstract: A method of selectively etching silicon nitride from a substrate comprising a silicon nitride layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the silicon nitride layer at a higher etch rate than the reactive gas etches the silicon oxide layer.Type: GrantFiled: March 9, 2012Date of Patent: April 7, 2015Assignee: Applied Materials, Inc.Inventors: Jingchun Zhang, Anchuan Wang, Nitin Ingle
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Patent number: 8986921Abstract: A lithographic material stack including a metal-compound hard mask layer is provided. The lithographic material stack includes a lower organic planarizing layer (OPL), a dielectric hard mask layer, and the metal-compound hard mask layer, an upper OPL, an optional anti-reflective coating (ARC) layer, and a photoresist layer. The metal-compound hard mask layer does not attenuate optical signals from lithographic alignment marks in underlying material layers, and can facilitate alignment between different levels in semiconductor manufacturing.Type: GrantFiled: January 15, 2013Date of Patent: March 24, 2015Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Bryan G. Morris, Tuan A. Vo, Christopher J. Waskiewicz, Yunpeng Yin
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Patent number: 8980758Abstract: Methods for etching an etching stop layer disposed on the substrate using a cyclical etching process are provided. In one embodiment, a method for etching an etching stop layer includes performing a treatment process on the substrate having a silicon nitride layer disposed thereon by supplying a treatment gas mixture into the processing chamber to treat the silicon nitride layer, and performing a chemical etching process on the substrate by supplying a chemical etching gas mixture into the processing chamber, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride, wherein the chemical etching process etches the treated silicon nitride layer.Type: GrantFiled: September 17, 2013Date of Patent: March 17, 2015Assignee: Applied Materials, Inc.Inventors: Mang-Mang Ling, Sean S. Kang, Jeremiah T. P. Pender, Srinivas D. Nemani, Bradley Howard
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Patent number: 8975185Abstract: During formation of a charge trap separation in a semiconductor device, a polymer deposition is formed in a reactor using a first chemistry. In a following step, a second chemistry can be used to etch the polymer deposition in the reactor. The same or similar second chemistry can be used in a second etching step to expose a first oxide layer in each of the cells of the semiconductor device and to form a flat upper surface. This additional etch step can also be performed by the reactor, thereby reducing the number of machines required in the formation process.Type: GrantFiled: November 26, 2012Date of Patent: March 10, 2015Assignee: Spansion, LLCInventor: Angela Tai Hui
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Patent number: 8975190Abstract: A plasma processing method includes a surface improving step of improving a surface of the photoresist film by performing plasma processing using a hydrogen-containing gas as a processing gas and an etching step of etching the SiON film by performing plasma processing using a processing gas including a gas containing a CHF-based gas and a chlorine-containing gas while using as a mask the photoresist film having the improved surface.Type: GrantFiled: September 25, 2013Date of Patent: March 10, 2015Assignee: Tokyo Electron LimitedInventor: Ryoichi Yoshida
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Patent number: 8969212Abstract: A method of etching exposed patterned heterogeneous structures is described and includes a remote plasma etch formed from a reactive precursor. The plasma power is pulsed rather than left on continuously. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents selectively remove one material faster than another. The etch selectivity results from the pulsing of the plasma power to the remote plasma region, which has been found to suppress the number of ionically-charged species that reach the substrate. The etch selectivity may also result from the presence of an ion suppression element positioned between a portion of the remote plasma and the substrate processing region.Type: GrantFiled: March 15, 2013Date of Patent: March 3, 2015Assignee: Applied Materials, Inc.Inventors: He Ren, Jang-Gyoo Yang, Jonghoon Baek, Anchuan Wang, Soonam Park, Saurabh Garg, Xinglong Chen, Nitin K. Ingle
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Patent number: 8956980Abstract: A method of etching silicon nitride on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and a nitrogen-and-oxygen-containing precursor. Plasma effluents from two remote plasmas are flowed into a substrate processing region where the plasma effluents react with the silicon nitride. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon nitride while very slowly removing silicon, such as polysilicon. The silicon nitride selectivity results partly from the introduction of fluorine-containing precursor and nitrogen-and-oxygen-containing precursor using distinct (but possibly overlapping) plasma pathways which may be in series or in parallel.Type: GrantFiled: November 25, 2013Date of Patent: February 17, 2015Assignee: Applied Materials, Inc.Inventors: Zhijun Chen, Zihui Li, Anchuan Wang, Nitin K. Ingle, Shankar Venkataraman
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Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells
Patent number: 8946076Abstract: Some embodiments include methods of forming vertically-stacked memory cells. An opening is formed to extend partially through a stack of alternating electrically insulative levels and electrically conductive levels. A liner is formed along sidewalls of the opening, and then the stack is etched to extend the opening. The liner is at least partially consumed during the etch and forms passivation material. Three zones occur during the etch, with one of the zones being an upper zone of the opening protected by the liner, another of the zones being an intermediate zone of the opening protected by passivation material but not the liner, and another of the zones being a lower zone of the opening which is not protected by either passivation material or the liner. Cavities are formed to extend into the electrically conductive levels along sidewalls of the opening. Charge blocking dielectric and charge-storage structures are formed within the cavities.Type: GrantFiled: March 15, 2013Date of Patent: February 3, 2015Assignee: Micron Technology, Inc.Inventors: Fatma Arzum Simsek-Ege, Aaron R. Wilson -
Patent number: 8932959Abstract: Etching of a thin film stack including a lower thin film layer containing an advanced memory material is carried out in an inductively coupled plasma reactor having a dielectric RF window without exposing the lower thin film layer, and then the etch process is completed in a toroidal source plasma reactor.Type: GrantFiled: March 6, 2013Date of Patent: January 13, 2015Assignee: Applied Materials, Inc.Inventors: Srinivas D. Nemani, Mang-mang Ling, Jeremiah T. Pender, Kartik Ramaswamy, Andrew Nguyen, Sergey G. Belostotskiy, Sumit Agarwal
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Patent number: 8932406Abstract: The molecular etcher carbonyl fluoride (COF2) or any of its variants, are provided for, according to the present invention, to increase the efficiency of etching and/or cleaning and/or removal of materials such as the unwanted film and/or deposits on the chamber walls and other components in a process chamber or substrate (collectively referred to herein as “materials”). The methods of the present invention involve igniting and sustaining a plasma, whether it is a remote or in-situ plasma, by stepwise addition of additives, such as but not limited to, a saturated, unsaturated or partially unsaturated perfluorocarbon compound (PFC) having the general formula (CyFz) and/or an oxide of carbon (COx) to a nitrogen trifluoride (NF3) plasma into a chemical deposition chamber (CVD) chamber, thereby generating COF2. The NF3 may be excited in a plasma inside the CVD chamber or in a remote plasma region upstream from the CVD chamber.Type: GrantFiled: March 15, 2013Date of Patent: January 13, 2015Assignee: Matheson Tri-Gas, Inc.Inventors: Glenn Mitchell, Ramkumar Subramanian, Carrie L. Wyse, Robert Torres, Jr.
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Patent number: 8921232Abstract: A method of taper-etching a layer to be etched that is made of a dielectric material and has a top surface. The method includes the steps of: forming an etching mask with an opening on the top surface of the layer to be etched; and taper-etching a portion of the layer to be etched, the portion being exposed from the opening, by reactive ion etching so that a groove having two wall faces intersecting at a predetermined angle is formed in the layer to be etched. The step of taper-etching employs an etching gas containing a first gas contributing to the etching of the layer to be etched and a second gas contributing to the deposition of a sidewall protective film, and changes, during the step, the ratio of the flow rate of the second gas to the flow rate of the first gas so that the ratio increases.Type: GrantFiled: February 25, 2014Date of Patent: December 30, 2014Inventors: Hironori Araki, Yoshitaka Sasaki, Hiroyuki Ito, Shigeki Tanemura
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Patent number: 8921136Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.Type: GrantFiled: January 17, 2013Date of Patent: December 30, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Neng-Kuo Chen, Shao-Ming Yu, Gin-Chen Huang, Chia-Jung Hsu, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 8889024Abstract: A plasma etching method that can improve an etching selection ratio of a film to be etched to a film different from the film to be etched compared with the related art is provided. The present invention provides a plasma etching method for selectively etching a film to be etched against a film different from the film to be etched, in which plasma etching of the film to be etched is performed using a gas that can cause to generate a deposited film containing similar components as components of the different film.Type: GrantFiled: April 9, 2014Date of Patent: November 18, 2014Assignee: Hitachi High-Technologies CorporationInventors: Tomoyuki Watanabe, Michikazu Morimoto, Mamoru Yakushiji, Tetsuo Ono
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Patent number: 8884288Abstract: The present invention provides a semiconductor structure for testing MIM capacitors. The semiconductor structure comprises: a first metal layer comprising at least a first circuit area and a second circuit area; a second metal layer located below the first metal layer with a first dielectric layer lying therebetween and connected with the second circuit area; a top plate located within the first dielectric layer closer to the first metal layer and connected with the first circuit area; a bottom plate located within the first dielectric layer closer to the second metal layer and separated from the top plate with an insulation layer therebetween and connected with the second circuit area. The second metal layer is connected with the substrate through a first electric pathway so as to form a second electric pathway from the top plate to the substrate when an electric leakage region exists in the insulation layer.Type: GrantFiled: September 30, 2013Date of Patent: November 11, 2014Assignee: Shanghai Huali Microelectronics CorporationInventors: Qiang Li, Zhuanlan Sun, Changhui Yang
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Patent number: 8877646Abstract: A method of manufacturing a plurality of spacers in a film stack includes forming at least one electrically-conductive element having sidewalls on a substrate, depositing a plurality of passivation layers proximate to the substrate, and performing etching on one of the plurality of passivation layers to form a plurality of spacers substantially across from the sidewalls of the at least one electrically-conductive element.Type: GrantFiled: April 19, 2010Date of Patent: November 4, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Valerie J Marty, Galen P. Cook
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Patent number: 8871651Abstract: A mask for use in fabricating one or more semiconductor devices is fabricated by: providing sacrificial spacing structures disposed over a substrate structure, and including protective hard masks at upper surfaces of the spacing structures; disposing a sidewall spacer layer conformally over the sacrificial spacing structures; selectively removing the sidewall spacer layer from above the sacrificial spacing structures to expose the protective hard masks of the spacing structures, the selectively removing including leaving sidewall spacers along sidewalls of the sacrificial spacing structures; providing a protective material over the substrate structure; and removing the exposed protective hard masks from the sacrificial spacing structures, and thereafter, removing remaining sacrificial spacing structures and the protective material, leaving the sidewall spacers over the substrate structure as a mask.Type: GrantFiled: July 12, 2013Date of Patent: October 28, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Dae Han Choi, Zhuangfei Chen, Fangyu Wu
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Publication number: 20140302683Abstract: The invention is directed to providing a dry etching agent having little effect on the global environment but having the required performance. Provided is a dry etching agent containing, each at a specific vol %: (A) a fluorine-containing unsaturated hydrocarbon represented by the formula CaFbHc (in the formula, a, b and c are each positive integers and satisfy the correlations of 2?a?5, c<b?1, 2a+2>b+c and b?a+c, excluding the case where a=3, b=4 or c=2); (B) at least one kind of gas selected from the group consisting of O2, O3, CO, CO2, COCl2, COF2, F2, NF3, Cl2, Br2, I2, and YFn (where Y is Cl, Br or I and n is an integer of 1 to 5); and (C) at least one kind of gas selected from the group consisting of N2, He, Ar, Ne, Xe, and Kr.Type: ApplicationFiled: June 13, 2012Publication date: October 9, 2014Applicant: Central Glass Company, LimitedInventors: Akiou Kikuchi, Tomonori Umezaki, Yasuo Hibino, Isamu Mori, Satoru Okamoto
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Patent number: 8828880Abstract: A method for manufacturing a semiconductor device by etching a SiN film on a surface of a substrate by using a gas containing a halogen element includes supplying a gas containing a basic gas at the initial stage of a process for supplying the gas containing the halogen element to the surface of the SiN film. By supplying the gas containing the basic gas at the initial stage of the etching, a SiNO film covering the surface of the SiN film is changed to a film of reaction products mainly including water (H2O) and ammonium hexafluorosilicate ((NH4)2SiF6).Type: GrantFiled: November 10, 2011Date of Patent: September 9, 2014Assignee: Tokyo Electron LimitedInventor: Hiroyuki Takahashi
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Publication number: 20140242803Abstract: A dry etching agent according to the present invention contains (A) a fluorinated propyne represented by the chemical formula: CF3C?CX where X is H, F, Cl, Br, I, CH3, CFH2 or CF2H; and either of: (B) at least one kind of gas selected from the group consisting of O2, O3, CO, CO2, COCl2 and COF2; (C) at least one kind of gas selected from the group consisting of F2, NF3, Cl2, Br2, I2 and YFn where Y is Cl, Br or I; and n is an integer of 1 to 5; and (D) at least one kind of gas selected from the group consisting of CF4, CHF3, C2F6, C2F5H, C2F4H2, C3F8, C3F4H2, C3ClF3H and C4F8. This dry etching agent has a small environmental load and a wide process window and can be applied for high-aspect-ratio processing without special operations such as substrate excitation.Type: ApplicationFiled: May 7, 2014Publication date: August 28, 2014Applicant: Central Glass Company, LimitedInventors: Yasuo HIBINO, Tomonori UMEZAKI, Akiou KIKUCHI, Isamu MORI, Satoru OKAMOTO
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Patent number: 8809141Abstract: A silicon nitrate layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.Type: GrantFiled: February 1, 2007Date of Patent: August 19, 2014Assignee: Texas Instruments IncorporatedInventors: Haowen Bu, Rajesh Khamankar, Douglas T. Grider
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Patent number: 8809199Abstract: A processing method is provided for plasma etching features in a silicon nitride (SiN) film covered by a mask pattern. The method includes preparing a film stack on a substrate, the film stack containing a SiN film on the substrate and a mask pattern on the SiN film, forming a plasma from a process gas containing HBr gas, O2 gas, and a carbon-fluorine-containing gas, applying pulsed RF bias power to the substrate, and transferring the mask pattern to the SiN film by exposing the film stack to the plasma.Type: GrantFiled: February 12, 2011Date of Patent: August 19, 2014Assignee: Tokyo Electron LimitedInventor: Tetsuya Nishizuka
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Publication number: 20140220785Abstract: A plasma etching method that can improve an etching selection ratio of a film to be etched to a film different from the film to be etched compared with the related art is provided. The present invention provides a plasma etching method for selectively etching a film to be etched against a film different from the film to be etched, in which plasma etching of the film to be etched is performed using a gas that can cause to generate a deposited film containing similar components as components of the different film.Type: ApplicationFiled: April 9, 2014Publication date: August 7, 2014Applicant: Hitachi High-Technologies CorporationInventors: Tomoyuki Watanabe, Michikazu Morimoto, Mamoru Yakushiji, Tetsuo Ono
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Patent number: 8796147Abstract: Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.Type: GrantFiled: December 17, 2010Date of Patent: August 5, 2014Assignee: STMicroelectronics, Inc.Inventors: Nicolas Loubet, Qing Liu, Prasanna Khare
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Patent number: 8790530Abstract: A method and manufacture for charge storage layer separation is provided. A layer, such as a polymer layer, is deposited on top of an ONO layer so that the polymer layer is planarized, or approximately planarized. The ONO includes at least a first region and a second region, where the first region is higher than the second region. For example, the first region may be the portion of the ONO that is over the source/drain region, and the second region may be the portion of the ONO that is over the shallow trench. Etching is performed on the polymer layer to expose the first region of the ONO layer, leaving the second region of the ONO unexposed. The etching continues to occur to etch the exposed ONO at the first region so that the ONO layer is etched away in the first region and the second region remains unexposed.Type: GrantFiled: February 10, 2010Date of Patent: July 29, 2014Assignee: Spansion LLCInventors: Angela T. Hui, Gang Xue
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Publication number: 20140199851Abstract: Methods of patterning silicon nitride dielectric films are described. For example, a method of isotropically etching a dielectric film involves partially modifying exposed regions of a silicon nitride layer with an oxygen-based plasma process to provide a modified portion and an unmodified portion of the silicon nitride layer. The method also involves removing, selective to the unmodified portion, the modified portion of the silicon nitride layer with a second plasma process.Type: ApplicationFiled: January 13, 2014Publication date: July 17, 2014Applicant: APPLIED MATERIALS, INC.Inventors: Srinivas D. Nemani, Jeremiah T. Pender, Qingjun Zhou, Dmitry Lubomirsky, Sergey G. Belostotskiy
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Patent number: 8753953Abstract: A capacitor and method for fabricating the same. In one configuration, the capacitor has a silicon substrate, a first and a second silicon dioxide layer over the silicon substrate, and silicon nitride fins between the silicon dioxide layers. The capacitor further includes a dielectric layer over the silicon nitride fins and metal vias in the dielectric layer.Type: GrantFiled: March 15, 2013Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
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Patent number: 8748298Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.Type: GrantFiled: January 31, 2008Date of Patent: June 10, 2014Assignee: International Rectifier CorporationInventors: Edwin L. Piner, John C. Roberts, Pradeep Rajagopal
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Patent number: 8741166Abstract: A plasma etching method that can improve an etching selection ratio of a film to be etched to a film different from the film to be etched compared with the related art is provided. The present invention provides a plasma etching method for selectively etching a film to be etched against a film different from the film to be etched, in which plasma etching of the film to be etched is performed using a gas that can cause to generate a deposited film containing similar components as components of the different film.Type: GrantFiled: October 31, 2012Date of Patent: June 3, 2014Assignee: Hitachi High-Technologies CorporationInventors: Tomoyuki Watanabe, Michikazu Morimoto, Mamoru Yakushiji, Tetsuo Ono
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Publication number: 20140141621Abstract: A method of etching exposed patterned heterogeneous structures is described and includes a remote plasma etch formed from a reactive precursor. The plasma power is pulsed rather than left on continuously. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents selectively remove one material faster than another. The etch selectivity results from the pulsing of the plasma power to the remote plasma region, which has been found to suppress the number of ionically-charged species that reach the substrate. The etch selectivity may also result from the presence of an ion suppression element positioned between a portion of the remote plasma and the substrate processing region.Type: ApplicationFiled: March 15, 2013Publication date: May 22, 2014Applicant: Applied Materials, Inc.Inventors: He Ren, Jang-Gyoo Yang, Jonghoon Baek, Anchuan Wang, Soonam Park, Saurabh Garg, Xinglong Chen, Nitin K. Ingle