Silicon Nitride Patents (Class 438/724)
  • Patent number: 8728945
    Abstract: A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Steven Alan Lytle
  • Patent number: 8722547
    Abstract: Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 100° C. and 350° C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: May 13, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Radhika Mani, Nicolas Gani, Wei Liu, Meihua Shen, Shashank C. Deshmukh
  • Patent number: 8709944
    Abstract: A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: April 29, 2014
    Assignee: TEL Epion Inc.
    Inventors: Noel Russell, John J. Hautala, John Gumpher
  • Patent number: 8703607
    Abstract: A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: April 22, 2014
    Assignee: TEL Epion Inc.
    Inventors: Noel Russell, John J. Hautala, John Gumpher
  • Patent number: 8679982
    Abstract: A method of suppressing the etch rate for exposed silicon-and-oxygen-containing material on patterned heterogeneous structures is described and includes a two stage remote plasma etch. Examples of materials whose selectivity is increased using this technique include silicon nitride and silicon. The first stage of the remote plasma etch reacts plasma effluents with the patterned heterogeneous structures to form protective solid by-product on the silicon-and-oxygen-containing material. The plasma effluents of the first stage are formed from a remote plasma of a combination of precursors, including a nitrogen-containing precursor and a hydrogen-containing precursor. The second stage of the remote plasma etch also reacts plasma effluents with the patterned heterogeneous structures to selectively remove material which lacks the protective solid by-product. The plasma effluents of the second stage are formed from a remote plasma of a fluorine-containing precursor.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: March 25, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Yunyu Wang, Anchuan Wang, Jingchun Zhang, Nitin K. Ingle, Young S. Lee
  • Publication number: 20140080310
    Abstract: A method of etching exposed silicon-nitrogen-and-carbon-containing material on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and an oxygen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon-nitrogen-and-carbon-containing material. The plasma effluents react with the patterned heterogeneous structures to selectively remove silicon-nitrogen-and-carbon-containing material from the exposed silicon-nitrogen-and-carbon-containing material regions while very slowly removing selected other exposed materials. The silicon-nitrogen-and-carbon-containing material selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element controls the number of ionically-charged species that reach the substrate.
    Type: Application
    Filed: March 15, 2013
    Publication date: March 20, 2014
    Applicant: Applied Materials Inc.
    Inventors: Zhijun Chen, Jingchun Zhang, Anchuan Wang, Nitin K. Ingle
  • Patent number: 8673770
    Abstract: One method disclosed herein includes the steps of forming a ULK material layer, forming a hard mask layer above the ULK material layer, forming a patterned photoresist layer above the hard mask layer, performing at least one etching process to define an opening in at least the ULK material layer for a conductive structure to be positioned in at least the ULK material layer, forming a fill material such that it overfills the opening, performing a process operation to remove the patterned photoresist layer and to remove the fill material positioned outside of the opening, removing the fill material from within the opening and, after removing the fill material from within the opening, forming a conductive structure in the opening.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: March 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Torsten Huisinga, Jens Heinrich, Ronny Pfuetzner
  • Patent number: 8668837
    Abstract: A method for etching a substrate includes etching at least one first layer of the substrate with a non-uniform substrate temperature and etching at least one second layer of the substrate with uniform substrate temperatures.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: March 11, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Kenny Linh Doan, Jong Mun Kim
  • Patent number: 8669185
    Abstract: A method of tailoring conformality of a film deposited on a patterned surface includes: (I) depositing a film by PEALD or pulsed PECVD on the patterned surface; (II) etching the film, wherein the etching is conducted in a pulse or pulses, wherein a ratio of an etching rate of the film on a top surface and that of the film on side walls of the patterns is controlled as a function of the etching pulse duration and the number of etching pulses to increase a conformality of the film; and (III) repeating (I) and (II) to satisfy a target film thickness.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: March 11, 2014
    Assignee: ASM Japan K.K.
    Inventors: Shigeyuki Onizawa, Woo-Jin Lee, Hideaki Fukuda, Kunitoshi Namba
  • Patent number: 8664119
    Abstract: A semiconductor device manufacturing method, comprising: providing a semiconductor substrate, on which a gate conductor layer as well as a source region and a drain region positioned on both sides of the gate conductor layer are provided, forming an etch stop layer on the semiconductor substrate, forming an LTO layer on the etch stop layer, chemical mechanical polishing the LTO layer, forming an SOG layer on the polished LTO layer, the etch stop layer, LTO layer and SOG layer forming a front metal insulating layer, back etching the SOG layer and etch stop layer of the front metal insulating layer to expose the gate conductor layer, and removing the gate conductor layer.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: March 4, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Qiuxia Xu, Lingkuan Meng, Dapeng Chen
  • Patent number: 8642481
    Abstract: A method of etching exposed silicon-and-nitrogen-containing material on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and an oxygen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon-and-nitrogen-containing material. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon-and-nitrogen-containing material from the exposed silicon-and-nitrogen-containing material regions while very slowly removing other exposed materials. The silicon-and-nitrogen-containing material selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: February 4, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Yunyu Wang, Anchuan Wang, Jingchun Zhang, Nitin K. Ingle, Young S. Lee
  • Patent number: 8617998
    Abstract: Methods of forming integrated circuit devices utilize fine width patterning techniques to define conductive or insulating patterns having relatively narrow and relative wide lateral dimensions. A target material layer is formed on a substrate and first and second mask layers of different material are formed in sequence on the target material layer. The second mask layer is selectively etched to define a first pattern therein. Sidewall spacers are formed on opposing sidewalls of the first pattern. The first pattern and sidewall spacers are used collectively as an etching mask during a step to selectively etch the first mask layer to define a second pattern therein. The first pattern is removed to define an opening between the sidewall spacers. The first mask layer is selectively re-etched to convert the second pattern into at least a third pattern, using the sidewall spacers as an etching mask. The target material layer is selectively etched using the third pattern as an etching mask.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: December 31, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-ho Min, Seong-soo Lee, Ki-jeong Kim
  • Publication number: 20130344702
    Abstract: A processing method is provided for plasma etching features in a silicon nitride (SiN) film covered by a mask pattern. The method includes providing a film stack on a substrate, the film stack containing a SiN film on the substrate and a mask pattern on the SiN film, transferring the mask pattern to the SiN film by exposing the film stack to a first plasma containing a carbon-fluorine-containing gas, O2 gas, and optionally HBr gas, and exposing the film stack to a second plasma containing a carbon-fluorine-containing gas, O2 gas, a silicon-fluorine-containing gas, and optionally HBr gas.
    Type: Application
    Filed: March 3, 2012
    Publication date: December 26, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Tetsuya Nishizuka
  • Patent number: 8580131
    Abstract: It is an object of the present invention to provide a plasma etching method that can improve a selection ratio of a film to be etched to a film different from the film to be etched than that in the related art. The present invention provides a plasma etching method for selectively etching a film to be etched with respect to another film different from the film to be etched, the plasma etching method including etching, using gas that can generate a deposited film containing components same as components of the another film different from the film to be etched, the film on which generation of the deposited film is suppressed.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: November 12, 2013
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Tomoyuki Watanabe, Mamoru Yakushiji, Michikazu Morimoto, Tetsuo Ono
  • Patent number: 8557621
    Abstract: A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: October 15, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong-Hyun Choung, Yang Ho Bae, Jean Ho Song, O Sung Seo, Sun-Young Hong, Hwa Yeul Oh, Bong-Kyun Kim, Nam Seok Suh, Dong-Ju Yang, Wang Woo Lee
  • Patent number: 8551886
    Abstract: A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: October 8, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Kyle P. Hunt, Leila Elvira Noriega, Billy Alan Wofford, Asadd M. Hosein, Binghua Hu, Xinfen Chen
  • Patent number: 8536061
    Abstract: According to one embodiment, a semiconductor device manufacturing method includes collectively etching layers of a multilayered film including silicon layers and silicon oxide films alternately stacked on a semiconductor substrate. The etching gas of the etching contains at least two types of group-VII elements and one of a group-III element, a group-IV element, a group-V element, and a group-VI element, the energy of ions entering the semiconductor substrate when performing the etching is not less than 100 eV, and an addition ratio of the group-III element, the group-IV element, the group-V element, the group-VI element, and the group-VII element to the group-VII element is 0.5 (inclusive) to 3.0 (inclusive).
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: September 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisataka Hayashi, Yusuke Kasahara, Tsubasa Imamura
  • Patent number: 8536059
    Abstract: Etching equipment and methods are disclosed herein for more efficient etching of sacrificial material from between permanent MEMS structures. An etching head includes an elongate etchant inlet structure, which may be slot-shaped or an elongate distribution of inlet holes. A substrate is supported in proximity to the etching head in a manner that defines a flow path substantially parallel to the substrate face, and permits relative motion for the etching head to scan across the substrate.
    Type: Grant
    Filed: February 18, 2008
    Date of Patent: September 17, 2013
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Khurshid Syed Alam, Evgeni Gousev, Marc Maurice Mignard, David Heald, Ana R. Londergan, Philip Don Floyd
  • Patent number: 8513086
    Abstract: Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching material on a microfeature workpiece includes providing a microfeature workpiece including a doped oxide layer and a nitride layer adjacent to the doped oxide layer. The method include selectively etching the doped oxide layer with an etchant comprising DI:HF and an acid to provide a pH of the etchant such that the etchant includes (a) a selectivity of phosphosilicate glass (PSG) to nitride of greater than 250:1, and (b) an etch rate through PSG of greater than 9,000 ?/minute.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: August 20, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Niraj Rana
  • Patent number: 8502286
    Abstract: A semiconductor device includes a MOSFET, and a plurality of stress layers disposed on the MOSFET, wherein the stress layers include a first stress layer disposed on the MOSFET and a second stress layer disposed on the first stress layer, the first stress layer has a first stress and the second stress layer has a second stress, and the first stress is different from the second stress.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: August 6, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ha-Jin Lim, Dong-Suk Shin, Pan-Kwi Park
  • Patent number: 8501630
    Abstract: A method for selectively etching a substrate is described. The method includes preparing a substrate comprising a silicon nitride layer overlying a silicon-containing contact region, and patterning the silicon nitride layer to expose the silicon-containing contact region using a plasma etching process in a plasma etching system. The plasma etching process uses a process composition having as incipient ingredients a process gas containing C, H and F, and a non-oxygen-containing additive gas, wherein the non-oxygen-containing additive gas includes H, or C, or both H and C, and excludes a halogen atom.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: August 6, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Andrew W. Metz, Hongyun Cottle
  • Patent number: 8486840
    Abstract: A method includes making a target feature of an integrated circuit by providing a main layer over a substrate, depositing a first mask layer over the main layer, patterning the first mask layer, forming sidewall spacers with a width (w) in adjoining sidewalls of the patterned first mask layer and exposing a top area of the patterned first mask layer, selectively removing the first mask layer and exposing a portion of the main layer between the sidewall spacers, depositing a second mask layer over the main layer between the sidewall spacers, selectively removing the sidewall spacers to form an opening and exposing another portion of the main layer in the opening, etching the main layer through the opening to form the target feature.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: July 16, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Publication number: 20130157470
    Abstract: A plasma etching method that can improve an etching selection ratio of a film to be etched to a film different from the film to be etched compared with the related art is provided. The present invention provides a plasma etching method for selectively etching a film to be etched against a film different from the film to be etched, in which plasma etching of the film to be etched is performed using a gas that can cause to generate a deposited film containing similar components as components of the different film.
    Type: Application
    Filed: October 31, 2012
    Publication date: June 20, 2013
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventor: Hitachi High-Technologies Corporation
  • Publication number: 20130130507
    Abstract: A method of etching exposed silicon-and-nitrogen-containing material on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and an oxygen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon-and-nitrogen-containing material. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon-and-nitrogen-containing material from the exposed silicon-and-nitrogen-containing material regions while very slowly removing other exposed materials. The silicon-and-nitrogen-containing material selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate.
    Type: Application
    Filed: January 18, 2013
    Publication date: May 23, 2013
    Applicant: APPLIED MATERIALS, INC.
    Inventor: Applied Materials, Inc.
  • Patent number: 8435890
    Abstract: A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: May 7, 2013
    Assignee: TEL Epion Inc.
    Inventors: Noel Russell, John J. Hautala, John Gumpher
  • Patent number: 8404597
    Abstract: A method for etching a layer assembly, the layer assembly including an intermediate layer sandwiched between an etch layer and a stop layer, the method including a step of etching the etch layer using a first etchant and a step of etching the intermediate layer using a second etchant. The first etchant includes a first etch selectivity of at least 5:1 with respect to the etch layer and the intermediate layer. The second etchant includes a second etch selectivity of at least 5:1 with respect to the intermediate layer and the stop layer. The first etchant being different from the second etchant.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: March 26, 2013
    Assignee: Infineon Technologies AG
    Inventors: Lothar Brencher, Dirk Meinhold, Michael Hartenberger, Georg Seidemann, Wolfgang Dickenscheld
  • Patent number: 8399361
    Abstract: A semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, and a protective insulating film composed of silicon nitride, which is formed over a surface of the compound semiconductor layer and whose film density in an intermediate portion is lower than that in a lower portion.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: March 19, 2013
    Assignee: Fujitsu Limited
    Inventor: Kozo Makiyama
  • Patent number: 8383001
    Abstract: There is provided a plasma etching method capable of achieving a sufficient organic film modifying effect by high-velocity electrons. In forming a hole in an etching target film by plasma etching, a first condition of generating plasma within a processing chamber by way of turning on a plasma-generating high frequency power application unit and a second condition of not generating the plasma within the processing chamber by way of turning off the plasma-generating high frequency power application unit are repeated alternately. Further, a negative DC voltage is applied from a first DC power supply such that an absolute value of the applied negative DC voltage during a period of the second condition is greater than an absolute value of the applied negative DC voltage during a period of the first condition.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: February 26, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Hiromasa Mochiki, Yoshinobu Ooya, Fumio Yamazaki, Toshio Haga
  • Publication number: 20130045605
    Abstract: A method of etching exposed silicon-and-nitrogen-containing material on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and an oxygen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon-and-nitrogen-containing material. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon-and-nitrogen-containing material from the exposed silicon-and-nitrogen-containing material regions while very slowly removing other exposed materials. The silicon-and-nitrogen-containing material selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate.
    Type: Application
    Filed: April 17, 2012
    Publication date: February 21, 2013
    Applicant: Applied Materials, Inc.
    Inventors: Yunyu Wang, Anchuan Wang, Jingchun Zhang, Nitin K. Ingle, Young S. Lee
  • Patent number: 8366953
    Abstract: A plasma cleaning method is performed in a plasma CVD apparatus for depositing a silicon nitride film on a surface of a target substrate, and includes a stage (S1) of supplying a cleaning gas containing NF3 gas into a process container, thereby removing extraneous deposits formed on portions inside the process container; a stage (S2) of supplying a gas containing hydrogen gas into the process container and generating plasma thereof, thereby removing residual fluorine inside the process container; and a stage (S3) of supplying a gas containing a rare gas into the process container and generating plasma thereof, thereby removing residual hydrogen inside the process container.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: February 5, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Masayuki Kohno, Tatsuo Nishita, Toshio Nakanishi
  • Publication number: 20130029494
    Abstract: Provided is a plasma etching method increasing the selectivity of a silicon nitride film in relation to the silicon oxide film or silicon functioning as a base. In a plasma etching method setting a pressure in a processing container as a predetermined level by exhausting a processing gas while supplying the processing gas into the processing container, generating plasma by supplying external energy to the processing container, and setting a bias applied to a holding stage holding a substrate in the processing container as predetermined value to selectively etch the silicon nitride film with respect to a silicon and/or silicon oxide film, the processing gas includes a plasma excitation gas, a CHxFy gas, and at least one oxidizing gas selected from the group consisting of O2, CO2, CO, and a flow rate of the oxidizing gas with respect to the CHxFy gas is set to be 4/9 or greater.
    Type: Application
    Filed: March 3, 2011
    Publication date: January 31, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Masaru Sasaki, Kazuki Moyama, Masaki Inoue, Yoko Noto
  • Publication number: 20130029493
    Abstract: A plasma etching method, for plasma-etching a target substrate including at least a film to be etched, an organic film to become a mask of the to-be-etched film, and a Si-containing film which are stacked in order from bottom, includes the first organic film etching step, the treatment step and the second organic film etching step when the organic film is etched to form a mask pattern of the to-be-etched film. In the first organic film etching step, a portion of the organic film is etched. In the treatment step, the Si-containing film and the organic film are exposed to plasma of a rare gas after the first organic film etching step. In the second organic film etching step, the remaining portion of the organic film is etched after the treatment step.
    Type: Application
    Filed: October 4, 2012
    Publication date: January 31, 2013
    Inventors: Masahiro OGASAWARA, Sungtae Lee
  • Patent number: 8343780
    Abstract: The invention relates to a method for straining or deforming a pattern or a thin layer (24), starting from an initial component comprising the said thin layer and a prestressed layer (20), this method comprising: an etching step of the prestressed layer, perpendicular to its surface.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: January 1, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Jean-Charles Barbe, Thomas Ernst
  • Patent number: 8338309
    Abstract: A method for forming a deep trench in a semiconductor device includes: forming a hard mask over a substrate, forming a hard mask pattern over the substrate through etching the hard mask to thereby expose an upper portion of the substrate, forming a first trench through a first etching the exposed substrate using a gas containing bromide and a gas containing chloride and forming a second trench through a second etching the first trench using of a gas containing sulfur and fluorine, wherein a depth of the second trench is deeper than a depth of the first trench.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: December 25, 2012
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Won-Kwon Lee
  • Patent number: 8278180
    Abstract: A method of forming a semiconductor device having a contact structure includes forming an insulating layer on a semiconductor substrate, and selectively implanting impurity ions into a predetermined region of the insulating layer to generate lattice defects in the predetermined region of the insulating layer. A thermal treatment, such as quenching the insulating layer at a temperature change rate of at least ?20° C./minute, is performed on the insulating layer having the lattice defects to accelerate generation of the lattice defects in the predetermined region such that a conductive region results from the generated lattice defects to provide current paths in the predetermined region.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: October 2, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changhun Lee, Keemoon Chun
  • Publication number: 20120208369
    Abstract: A processing method is provided for plasma etching features in a silicon nitride (SiN) film covered by a mask pattern.
    Type: Application
    Filed: February 12, 2011
    Publication date: August 16, 2012
    Applicant: Tokyo Electron Limited
    Inventor: Tetsuya Nishizuka
  • Patent number: 8216434
    Abstract: A micromachined sensor for measuring vascular parameters, such as fluid shear stress, includes a substrate having a front-side surface, and a backside surface opposite the front-side surface. The sensor includes a diaphragm overlying a cavity etched within the substrate, and a heat sensing element disposed on the front-side surface of the substrate and on top of the cavity and the diaphragm. The heat sensing element is electrically couplable to electrode leads formed on the backside surface of the substrate. The sensor includes an electronic system connected to the backside surface and configured to measure a change in heat convection from the sensing element to surrounding fluid when the sensing element is heated by applying an electric current thereto, and further configured to derive from the change in heat convection vascular parameters such as the shear stress of fluid flowing past the sensing element.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: July 10, 2012
    Assignee: University of Southern California
    Inventors: Tzung K. Hsiai, Gopikrishnan Soundararajan, Eun Sok Kim, Hongyu Yu, Mahsa Rouhanizadeh, Christina Tiantian Lin
  • Patent number: 8187971
    Abstract: A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: May 29, 2012
    Assignee: TEL Epion Inc.
    Inventors: Noel Russell, John J. Hautala, John Gumpher
  • Patent number: 8178444
    Abstract: A substrate processing method that can eliminate unevenness in the distribution of plasma. The method is for a substrate processing apparatus that has a processing chamber in which a substrate is housed, a mounting stage that is disposed in the processing chamber and on which the substrate is mounted, and an electrode plate that is disposed in the processing chamber such as to face the mounting stage, the electrode plate being made of silicon and connected to a radio-frequency power source, and carries out plasma processing on the substrate. In the plasma processing, the temperature of the electrode plate is measured, and based on the measured temperature, the temperature of the electrode plate is maintained lower than a critical temperature at which the specific resistance value of the silicon starts changing.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: May 15, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Chishio Koshimizu, Taichi Hirano, Masanobu Honda, Shinji Himori
  • Patent number: 8173532
    Abstract: A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) first and second semiconductor body regions. The method further includes forming (i) a gate divider region and (ii) a gate electrode layer on top of the semiconductor substrate. The gate divider region is in direct physical contact with gate electrode layer. A top surface of the gate electrode layer and a top surface of the gate divider region are essentially coplanar. The method further includes patterning the gate electrode layer resulting in a first gate electrode region and a second gate electrode region. The gate divider region does not overlap the first and second gate electrode regions in the reference direction.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: May 8, 2012
    Assignee: International Business Machines Corporation
    Inventors: Robert C. Wong, Haining S. Yang
  • Patent number: 8163653
    Abstract: A semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, and a protective insulating film composed of silicon nitride, which is formed over a surface of the compound semiconductor layer and whose film density in an intermediate portion is lower than that in a lower portion.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: April 24, 2012
    Assignee: Fujitsu Limited
    Inventor: Kozo Makiyama
  • Patent number: 8148270
    Abstract: A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: April 3, 2012
    Assignee: Taiwan Semiconductor Manufactuiring Co., Ltd.
    Inventors: Hun-Jan Tao, Ryan Chia-Jen Chen, Mong-Song Liang
  • Publication number: 20120077347
    Abstract: A method for selectively etching a substrate is described. The method includes preparing a substrate comprising a silicon nitride layer overlying a silicon-containing contact region, and patterning the silicon nitride layer to expose the silicon-containing contact region using a plasma etching process in a plasma etching system. The plasma etching process uses a process composition having as incipient ingredients a process gas containing C, H and F, and a non-oxygen-containing additive gas, wherein the non-oxygen-containing additive gas includes H, or C, or both H and C, and excludes a halogen atom.
    Type: Application
    Filed: September 28, 2010
    Publication date: March 29, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Andrew W. METZ, Hongyun COTTLE
  • Patent number: 8138096
    Abstract: In a plasma etching method, a substrate including an underlying film, an insulating film and a resist mask is plasma etched to thereby form a number of holes in the insulating film including a dense region and a sparse region by using a parallel plate plasma etching apparatus for applying a plasma-generating high frequency electric power to a space between an upper and a lower electrode and a biasing high frequency electric power to the lower electrode. The plasma etching method includes mounting the substrate on a mounting table; supplying a first process gas containing carbon and fluorine to form the holes in the insulating film to a depth close to the underlying film; and supplying a second process gas including an inert gas and another gas contain carbon and fluorine to have the holes reach the underlying film while applying a negative DC voltage to the upper electrode.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: March 20, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Ryoichi Yoshida
  • Patent number: 8114781
    Abstract: A substrate processing method capable of selectively removing a nitride film. Oxygen plasma containing plasmarized oxygen gas is made to be in contact with a silicon nitride film, which is made of SiN, of a wafer to thereby cause the silicon nitride film to be changed to a silicon monoxide film. The silicon monoxide film is selectively etched by hydrofluoric acid generated from HF gas supplied toward the silicon monoxide film.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: February 14, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Eiichi Nishimura, Koichi Yatsuda
  • Publication number: 20110318936
    Abstract: A method for selectively etching a substrate is described. The method includes disposing a substrate comprising a silicon nitride (SiNy) layer overlying silicon in a plasma etching system, and transferring a pattern to the silicon nitride layer using a plasma etch process, wherein the plasma etch process utilizes a process composition having as incipient ingredients a process gas containing C, H and F, and an additive gas including CO2. The method further includes: selecting an amount of the additive gas in the plasma etch process to achieve: (1) a silicon recess formed in the silicon having a depth less than 10 nanometers (nm), and (2) a sidewall profile in the pattern having an angular deviation from 90 degrees less than 2 degrees.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 29, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Akiteru KO, Christopher COLE
  • Patent number: 8043921
    Abstract: A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions. At least one of the sidewall spacers, LDD regions and S/D regions include an exposed silicon nitride layer. The LDD or S/D regions include a protective dielectric layer formed directly on the semiconductor surface. Ion implanting implants the LDD regions or S/D regions using the sidewall spacers as implant masks. The exposed silicon nitride layer is selectively removed, wherein the protective dielectric layer when the sidewall spacers include the exposed silicon nitride layer, or a replacement protective dielectric layer formed directly on the semiconductor surface after ion implanting when the LDD or S/D regions include the exposed silicon nitride layer, protects the LDD or S/D regions from dopant loss due to etching during selectively removing.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: October 25, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Brian K. Kirkpatrick, Deborah J. Riley
  • Patent number: 8034720
    Abstract: A substrate processing method that can remove a silicon nitride film without damaging a thermally-oxidized film. A substrate having at least a thermally-oxidized film and a silicon nitride film formed on the thermally-oxidized film is heated to a temperature of not less than 60° C. Then, hydrogen fluoride gas is supplied toward the substrate.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: October 11, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Eiichi Nishimura, Chie Kato, Jun Yamawaku
  • Publication number: 20110223770
    Abstract: A method for selectively etching a nitride layer with respect to a silicon oxide based layer over a substrate is provided. The substrate is placed in a plasma processing chamber. The nitride layer is etched, comprising the steps of flowing a nitride etch gas comprising a hydrocarbon species, an oxygen containing species and a fluorocarbon or hydrofluorocarbon species into the plasma chamber, forming a plasma from the nitride etch gas, and using the plasma from the nitride etch gas to selectively etch the nitride layer with respect to the silicon oxide based layer.
    Type: Application
    Filed: March 15, 2010
    Publication date: September 15, 2011
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Alan Jensen, Mayumi Block
  • Patent number: RE44292
    Abstract: There are included steps of forming a silicon nitride layer on a silicon layer or a silicon oxide layer, loading the silicon layer or the silicon oxide layer and the silicon nitride layer in a dry etching atmosphere, and selectively etching the silicon nitride layer with respect to the silicon layer or the silicon oxide layer by flowing a fluorine gas consisting of any one of CH2F2, CH3F, or CHF3 and an inert gas to the dry etching atmosphere. Hence, in the etching process of the silicon nitride layer, the etching selectivity of the silicon nitride layer to Si or SiO2 can be enhanced and also etching anisotropy can be enhanced.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: June 11, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tadashi Oshima