Abstract: The dimensional precision and accuracy of sub-micron-sized, in-laid metallization patterns, e.g., of electroplated copper or copper alloy, formed in the surface of a dielectric layer are significantly improved by utilizing a layer of a sputter-resistant mask material formed of a high atomic mass metallic element or compound thereof during reactive ion etching of the dielectric layer by a fluorine-containing plasma for forming sub-micron-dimensioned recesses therein. After filling of the recesses, planarization, as by CMP, is conducted wherein excess thickness of the metal layer is removed, together with underlying portions of the sputter-resistant mask layer.

Abstract: The reliability of in-laid metallization patterns, e.g., of copper or a copper-based alloy is significantly enhanced by voidlessly filling recesses formed in the dielectric layer surface by an electroplating process. Embodiments of the present invention include preventing "pinching-off" of the recess opening due to formation of overhanging nucleation/seed layer deposits at the corners of the opening as a result of locally increased rates of deposition. Embodiments of the present invention also include providing a dual-layered dielectric layer comprising dielectric materials having different lateral etching rates when subjected to a preselected etching process, for selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface, which tapered width profile effectively prevents formation of overhanging deposits, which overhanging deposits can result in occlusion and void formation during electroplating to fill the recesses.

Abstract: A substrate has an insulating surface; a fine wire region disposed on the insulating surface of the substrate and extending long in one direction; a first insulating film formed on the fine wire region at least at a partial area along the longitudinal direction of the fine wire region; and a first micro box region formed on the first insulating film over the fine wire region at a partial area along the longitudinal direction of the fine wire region a semiconductor device. The semiconductor device has a fine wire region and a micro box region to realize control of a single electron level. The manufacturing method for the semiconductor device is also disclosed.

Abstract: A method for forming a semiconductor device includes providing a semiconductor body having source and drain regions therein and a gate electrode on a portion of a surface of such body between the source and drain regions. A dielectric layer is provided on the surface of the semiconductor body over the source and drain regions. A dielectric material is formed over the dielectric layer and over the gate electrode. An inorganic, dielectric layer is formed over the semiconductor body dielectric material. The inorganic, dielectric layer is patterned into a mask to expose selected portions of the dielectric material, such portions being over the source and drain regions. An etch is brought into contact with the mask. The etch removes the exposed underlying portions of the dielectric material and exposed underling portions of the dielectric layer to thereby expose the portions of the source and drain regions.

Abstract: In-laid metallization patterns, e.g., of copper or copper alloy, are formed in the surface of a dielectric layer with significantly improved reliability by voidlessly filling recesses formed in the dielectric layer surface by electroplating. Embodiments include preventing "pinching-off" of the recess opening due overhanging nucleation/seed layer deposits at the corners of the opening as a result of localized increased rates of deposition. Embodiments also include providing a dual-layered dielectric layer comprising different dielectric materials and performing a first, isotropic etching process of the upper (sacrificial) lamina of the dielectric layer for selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface, followed by a second, anisotropic etching process for extending the recess at a substantially constant width for a predetermined depth into the lower lamina of the dielectric layer.

Abstract: The reliability of in-laid metallization patterns, e.g., of copper or copper alloy, is significantly enhanced by voidlessly filling recesses in a substrate by an electroplating process, wherein "pinching-off" of the recess opening due to earlier formation of overhanging nucleation/seed layer deposits at the corners of the opening as a result of increased rates of deposition thereat is prevented. Embodiments include selectively tapering the width of the recess mouth opening to provide a wider opening at the substrate surface by means of a directed beam etching or ablation process while rotating the substrate, which tapered width profile effectively prevents formation of overhanging deposits thereat which can result in occlusion and void formation during filling of the recesses by electroplating.

Abstract: A method for fabricating a capacitor for a semiconductor memory configuration. In this case, a selectively etchable material is applied to a conductive support, which is connected to a semiconductor body via a contact hole in an insulator layer, and patterned. A first conductive layer is applied thereon and patterned. A hole is introduced into the first conductive layer, through which hole the selectively etchable material is etched out. A cavity is produced under the first conductive layer in the process. The inner surface of the cavity and the outer surface of the first conductive layer are provided with a dielectric layer, to which a second conductive layer is applied and patterned.

Abstract: The invention discloses a split polycilicon process for forming poly gate and polycide gate with an almost equal height in a CMOS image integrated circuit fabricated on a substrate to reduce the sheet resistance of the poly gate electrode. First, a gate oxide layer is formed on a substrate, and then a polysilicon layer and a capped dielectric layer are sequentially deposited. Next, a poly gate is patterned by using a first photoresist layer, and then the capped dielectric layer and a portion of the polycilison layer are etched. Next, the first photoresist layer is removed. Thereafter, a silicide layer is deposited. Then, a polycide gate is patterned by using a second photoresist layer, and the silicide layer and the polysilicon layer is etched. Finally, the second photoresist layer is removed.

Abstract: A method for forming a single cavity in a substrate, which may extend approximately the length of a device located on top of the substrate, and device produced thereby. The device has a length and a width, and may extend approximately the length of the substrate. After locating the device on the surface of the substrate, a first etchant is applied through openings on the surface of the substrate. Subsequently, a second etchant is applied through the same openings on the surface of the substrate. As a result, a single cavity is formed beneath the surface of the device, suspending the device and minimizing electrical coupling.

Abstract: FET devices are manufactured using STI on a semiconductor substrate coated with a pad from which are formed raised active silicon device areas and dummy active silicon mesas capped with pad structures on the doped silicon substrate and pad structure. A conformal blanket silicon oxide layer is deposited on the device with conformal projections above the mesas. Then a polysilicon film on the blanket silicon oxide layer is deposited with conformal projections above the mesas. The polysilicon film projections are removed in a CMP polishing step which continues until the silicon oxide layer is exposed over the pad structures. Selective RIE partial etching of the conformal silicon oxide layer over the mesas is next, followed in turn by CMP planarization of the conformal blanket silicon oxide layer which converts the silicon oxide layer into a planar silicon oxide layer, using the pad silicon nitride as an etch stop.

Abstract: A multi-step dry-etching method that sequentially employs plasma etching and reactive ion etching process steps to form the pairs of adjacent, doped polysilicon gate electrodes of a twin-well CMOS device. The initial dry-etching process step uses to best advantage the speed of plasma etching to rapidly form pairs of adjacent p- and n-type gate-precursor features with substantially vertical sidewalls from the upper 50-80% of a doped polysilicon layer which lies on an insulating film. The gate-precursor features and, subsequently, the gate electrodes are formed from pairs of adjacent p- and n-type regions within the doped polysilicon layer which lie over pairs of adjacent n- and p-wells (the twin wells of the CMOS device), respectively, within a substrate. The subsequent dry-etching process step uses reactive ion etching to complete the formation of the pairs of adjacent, doped polysilicon gate electrodes from the remaining 50-20% of the etched, doped polysilicon layer without over-etching the insulating film.

Abstract: A new method of cleaning metal precipitates after the etching of metal lines using a two-step process is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer. A metal layer is deposited overlying the barrier metal layer wherein metal precipitates form at the interface between the barrier metal layer and the metal layer. The metal layer is covered with a layer of photoresist which is exposed to actinic light and developed and patterned to form the desired photoresist mask. The metal layer is etched away where it is not covered by the photoresist mask to form metal lines whereby the metal precipitates are exposed on the surface of the barrier metal layer.

Abstract: A chemical vapor deposition (CVD) method for forming a doped silicate glass dielectric layer within a microelectronics fabrication. There is first positioned within a reactor chamber a substrate employed within a microelectronics fabrication. There is then stabilized within the reactor chamber with respect to the substrate a first flow of a silicon source material absent a flow of a dopant source material. There is then deposited upon the substrate within the reactor chamber a doped silicate glass dielectric layer through a chemical vapor deposition (CVD) method. The doped silicate glass dielectric layer is formed employing a second flow of the silicon source material, a flow of an oxidant source material and the flow of the dopant source material. There may subsequently be formed through the doped silicate glass dielectric layer an anisotropically patterned via through an anisotropic patterning method.

Abstract: A method is disclosed for forming a spacer, wherein said formation is preferably performed in a single dry etch sequence in a single dry etch tool. In this single dry etch sequence subsequently polysilicon spacers are defined, used as an etch mask and removed. Said etch sequence comprises at least one dry etching step. In case said etch sequence comprises more than one dry etching step, then these etching steps are performed subsequently in the same etch tool without breaking vacuum in said etch tool. In an embodiment of the invention the capability of using a single dry etch sequence for the formation of nitride spacers, using polysilicon spacer masking and the in-situ removal of the remaining polysilicon spacers, is demonstrated.

Abstract: A method is provided for eliminating the dishing effect of the chemical mechanical polishing (CMP) process on wide inlaid conductor leads in the layer of dielectric on a semiconductor device. A silicon dioxide dielectric having narrow and wide trenches is first coated with a blanket deposition of conductor material. The conductor material is coated with a photoresist and patterned with a reverse photo image of the trenches. The photoresist is etched leaving the photoresist over the trenches and the conductor material exposed between the trenches. The conductor material is etched removing the conductor material between the trenches and leaving the original thickness of conductor material over the trenches. The remaining photoresist is removed and the conductor material subject to CMP with the original thickness of conductor material acting to prevent dishing.

Abstract: A method for fabricating an SOI substrate is provided, which has an active substrate formed as a thin film. The method comprises the steps of: using a both-side polishing apparatus to polish both sides of a supporting substrate 1; bonding an active substrate 2 onto the supporting substrate 1. to form a bonded-wafer; removing an unbonded portion formed at the circumference of the bonded-wafer; flat grinding the active substrate 2 to reduce the thickness thereof; etching the active substrate 2 by spin etching; and processing the active substrate to be a thin film by PACE processing.

Abstract: An etching method used in the high density plasma etching system to etch a silicon oxide dielectric layer to form openings of different depths. The method uses a mixture of C.sub.4 H.sub.8, CH.sub.2 F.sub.2, and Ar as an etching gas source to etch the silicon oxide dielectric layer, forming a plurality of openings of a first depth. A mixture of C.sub.4 H.sub.8, CO, and Ar is used as an etching gas source to etch the silicon oxide dielectric layer exposed by the first opening, so that the opening is deepened to the second depth. Using a mixture of C.sub.4 H.sub.8, CH.sub.2 F.sub.2, CO, and Ar as the etching gas source, the silicon oxide dielectric layer exposed by the opening is etched, so that the openings are deepened to the third depth and the fourth depth.

Abstract: A wiring pattern forming method includes the step of: forming resist patterns on an aluminum or aluminum alloy conductive layer, the resist patterns including a low density pattern area and a high density pattern area; etching and removing a portion of a thickness of the conductive layer by an etching process presenting anti-microloading effect by using the resist patterns as an etching mask, and etching and removing another portion of the thickness of the conductive layer by an etching process presenting microloading effect by using the resist patterns as an etching mask. A method of forming an aluminum or aluminum alloy wiring pattern is provided which can maintain a high etching rate and reduce electron shading damage.

Abstract: A method for forming multi-level contact holes in a semiconductor structure is disclosed. The semiconductor structure includes a dielectric layer overlying a silicon substrate, a silicon nitride layer within the dielectric layer, the silicon nitride layer overlying a first conductive layer, a silicon oxynitride layer within the dielectric layer, the silicon oxynitride layer overlying a second conductive layer, and a plate poly layer. The method comprises: using a first etching step to etch through the dielectric layer to reach the silicon nitride layer as well as reach the silicon oxynitride layer, the first etching step using a combination of a first gas mixture and a first gas, the first gas mixture comprising a combination of N.sub.2, CO and Ar. The first gas includes C.sub.4 F.sub.8, CH.sub.3 F and O.sub.2, the flow rate ratio of the first gas C.sub.4 F.sub.8 /CH.sub.3 F/O.sub.2 is about 6:1:3. The flow rate of each component of the first gas mixture is that, the flow rate of N.sub.

Abstract: A method for forming a passivation layer with improved planarity includes patterning a top interconnect metal layer through two steps of etching, in which the metal layer is formed over a substrate that has device elements already formed thereon. The first etching process is isotropic etching, which undercuts an etching mask layer. The upper sharp corners of the metal layer are removed. The second etching process in anisotropic etching to complete an opening that exposes the substrate. A PSG layer and a silicon nitride layer are sequentially formed to serve as a passivation layer. Since the aspect ratio is reduced due to undercutting, a void within the opening is avoided, and a crack in the passivation layer within the opening is also avoided.

Abstract: Methods of forming contact openings and methods of controlling the degree of taper of contact openings are described. In one implementation, a layer is first etched through a contact mask opening using a first set of etching conditions. The etching conditions provide a first degree of sidewall taper from vertical, if etching completely through the layer. After the first etching, the layer is second etched through the contact mask opening using a second set of etching conditions. The second set of etching conditions provide a second degree of sidewall taper from vertical, if etching completely through the layer. The second degree of sidewall taper is different from the first degree of taper. In another embodiment, a material through which a contact opening is to be etched to a selected depth is formed over a substrate. A masking layer having an opening therein is formed over the material.

Abstract: A semiconductor device that includes a recessed portion formed by isotropic-etching through an opening in an oxide layer on a surface of the semiconductor substrate, an opening formed in an oxide layer formed on the inner surface of the recessed portion by anisotropic etching, a recessed portion formed adjacent another recessed portion by isotropic etching through the opening. An overhang portion in the oxide layers at the opening is used as a mask in successive etching steps, and the isotropic and anistropic etching steps are repeated through the same mask, to eliminate errors in stacking masks and obtaining a deep notched gate structure within a short period. A cross-sectional shape of the recessed portion includes a plurality of curved recessed portions of different curvatures. A semiconductor device thus formed includes a recessed portion having a high aspect (length/width) ratio, and a depth larger than the width.

Abstract: A method to fabricate bottle-shaped deep trench in a semiconductor substrate which mainly involves two substitute plasma etching steps from the conventional approach. After a neck profile is formed, instead of raising the plasma gas pressure while keeping the etching composition constant, as in the conventional approach, the plasma gas pressure is first maintained the same, then decreased substantially. On the other hand, the concentrations of HBr and NF.sub.3 are increased substantially in both new steps. The first substitute plasma etching step is conducted at a pressure of 100 mtorr an RF power of about 1,000 W, a magnetic field of 65 Gauss. The plasma gas composition consists of HBr, NF.sub.3, and (He/O.sub.2) a at a ratio of about 200:20:20. The second substitute plasma etching step is conducted at plasma gas pressure of 30 mtorr, an RF power of 600 W, a magnetic field of 65 Gauss. The plasma gas composition consists of HBr, NF.sub.3, and (He/O.sub.2) a at a ratio of about 150:13:20.

Abstract: A method for increasing chip yield by reducing black silicon deposition in accordance with the present invention includes the steps of providing a silicon wafer suitable for fabricating semiconductor chips, depositing a first layer over an entire surface of the wafer, removing a portion of the first layer to expose a region suitable for forming semiconductor devices and etching the wafer such that a remaining portion of the first layer prevents redeposition of etched material on the wafer. A semiconductor assembly for reducing black silicon deposition thereon, includes a silicon wafer suitable for fabricating semiconductor chips, the wafer having a front surface for forming semiconductor devices, a back surface and edges. A deposited layer is formed on the wafer for covering the back surface and the edges such that redeposition of silicon on the back surface and edges of the wafer during etching is prevented.

Abstract: A masking and etching technique during the formation of a memory cell capacitor which utilizes an etching technique to utilize a maximum surface area over the memory cell and to form thin spacers to pattern separation walls between capacitors. This technique results in efficient space utilization which, in turn, results in an increase in the surface area of the capacitor for an increased memory cell capacitance.

Abstract: The process produces a semiconductor body with a first region that has a self-aligning structure and with a further second region. The insulation layer lying on a semiconductor layer in the first region is fully removed in the second region using a photographic technique and a subsequent etching process. Subsequently, or at the same time, the requisite structuring of the semiconductor layer and of the insulation layer is carried out in the first region. This leads to substantially lesser topography changes and steps and thus higher packing density in the further region of the semiconductor body.

Abstract: A method for fabricating a semiconductor device according to the present invention includes the steps of: forming an oxide film on a substrate having a silicon region at least on the surface thereof; defining a resist pattern on the oxide film; placing the substrate on an electrode provided inside a reaction chamber of a plasma etching apparatus, and etching the oxide film by using plasma generated from a gas including a fluorocarbon gas with a bias voltage applied to the substrate; and removing fluorine from the reaction chamber by generating oxygen plasma inside the reaction chamber with substantially no bias voltage applied to the substrate.

Abstract: The present invention relates to a method of forming an interconnection for a semiconductor device using copper. The method of the invention, including the steps of forming an insulating layer having a groove on a semiconductor substrate containing active elements; forming and depositing a copper thin film on the insulating layer including the groove; and reflowing the copper thin film, may reflow the copper thin film deposited on the semiconductor substrate having a high-step surface for less than 30 min. below 450.degree. C., which show improved annealing conditions as compared with the conventional art. In addition, by reducing consumption of thermal energy in accordance with a low-temperature process, copper is restrained from being rapidly diffused through a silicon substrate, electrodes, etc. when forming the interconnection for the semiconductor device, thus improving productivity of the semiconductor devices.

Abstract: A method of removing an outer layer from an inner surface during semiconductor fabrication. A portion of the outer layer (50) may be anisotropically etched. A remaining portion of the outer layer (55) may then be wet etched without impairing the inner surface (12).

Abstract: Ashing process of a resist pattern used in a semiconductor device manufacturing method is conducted by exposing the resist, the wirings, and their peripheral regions to a first atmosphere which includes a first product obtained by plasmanizing a gas containing water at a rate of more than 30 flow rate %, and placing the resist in a second atmosphere which includes a second product obtained by plasmanizing an oxygen mixed gas which contains an oxygen gas as a principal component before or after or before and after the exposing step.

Abstract: A method for ultra-fine patterning of a semiconductor device performs a first, anisotropic etching of a hard mask layer according to a pattern created by lithographic techniques to create lines in the hard mask layer having an initial width. A second, anisotropic etching is performed on the hard mask layer to narrow the lines further than otherwise possible with a single etching according to the patterns created by lithography. Using the narrowed lines created in the hard mask layer, a third, anisotropic etching is performed, this time on the conductor layer shadowed by the narrow lines of the hard mask layer. The third etching creates narrow lines in the conductor layer in accordance with the narrow lines of the hard mask layer.

Abstract: A method of etching a platinum electrode layer disposed on a substrate. The method comprises providing a substrate supporting a platinum electrode layer, an insulation layer on the platinum electrode layer, and a resist layer on the insulation layer. A portion of the insulation layer is etched by employing a plasma of an etchant gas to break through and to remove the portion of the insulation layer from the platinum electrode layer to expose part of the platinum electrode layer. The exposed part of the platinum electrode layer is then etched by employing a plasma of an etchant gas comprising argon. The etched platinum electrode layer is subsequently overetched by employing a high density plasma of an etchant gas to remove redeposited veils from the etched platinum electrode layer. The etched platinum electrode layer is employed in a semiconductor device.

Abstract: A process for intermetal SOG/SOP dielectric planarization without having effect is described. First, a silicon-rich oxide (SRO) layer is formed on a substrate surface. Next, a metal layer and an antireflective coating (ARC) layer are sequentially deposited over the SRO layer. The metal layer and ARC layer are then etched to define metal patterns by the conventional lithography and etching techniques. Next, an Ozone-TEOS (O.sub.3 -TEOS) layer and a SOG layer are then formed over the entire substrate surface. Next, the O.sub.3 -TEOS layer and SOG layer are subjected to etching back treatment to obtain a planar substrate surface which only has a small portion of the O.sub.3 -TEOS layer covered on the substrate surface. The etching back treatment can be PEB, TEB or CMP techniques. Finally, a passivation layer is deposited over the remaining of O.sub.3 -TEOS layer.

Abstract: The invention relates to calibration standards which are used chiefly for the calibration of profilometers and in atomic force- and scanning probe microscopes. The calibration standard has one step of defined height H or a multi-step system formed of several steps of the same step-height H and consisting of exactly one material. The manufacturing procedure for the calibration standard requires only a single masking layer for each of the different versions in the form of a one-step standard or a multi-step system.

Abstract: The practice of forming self-aligned contacts in MOSFETs using a silicon nitride gate sidewall and a silicon nitride gate cap has found wide acceptance, particularly in the manufacture of DRAMs, where bitline contacts are formed between two adjacent wordlines, each having a nitride sidewall. The contact etch requires a an RIE etch having a high oxide/nitride selectivity. Current etchants rely upon the formation of a polymer over nitride surfaces which enhances oxide/nitride selectivity. However, for contact widths of less than 0.35 microns, as are encountered in high density DRAMs, the amount of polymer formation required to attain a high selectivity causes the contact opening to close over with polymer before the opening is completely etched. This results in opens or unacceptably resistive contacts. On the other hand, if the etchant is adjusted to produce too little polymer, the nitride cap and sidewalls are thinned or etched through, producing gate to source/drain shorts.

Abstract: A method fabricating salicide. A substrate having a polysilicon gate and a source/drain region is provided. A silicon oxide layer is formed on the polysilicon gate and the substrate. Using dry etch, a part of the silicon oxide layer is removed to leave a spacer with a waistline on a side wall of the polysilicon gate. A metal layer is formed on the polysilicon gate and the source/drain region.

Abstract: An improved and new method for forming a planarized integrated cirsuit structure has been developed. The method uses a combination of etchback and chemical/mechanical polishing (CMP), in which the etchback process uses a tailored mask to compensate for non-unifomity of material removal by the subsequent chemical/mechanical (CMP) process, thereby resulting in improved planarization and superior thickness uniformity.

Abstract: Semiconductor processing methods of forming substrate features, e.g. openings, and in particular, methods of forming contact openings are described. In one embodiment, a pair of openings are formed in a first layer over a substrate to first selected depths defined by respective opening bases. A second layer is formed within the openings and over the opening bases. The second layer has different thicknesses relative to the bases over which it is formed. A portion of the base of only one of the openings is exposed through the second layer, and material elevation ally there below is removed. In another embodiment, the openings are defined by sidewalls which join with the respective bases. The second layer is formed within the openings and over at least some of the sidewalls of each opening and has a different thickness over sidewall portions of each opening which are disposed at common substrate elevations.

Abstract: A micromachining method is disclosed for forming a suspended micromechanical structure from {111} crystalline silicon. The micromachining method is based on the use of anisotropic dry etching to define lateral features of the structure which are etched down into a {111}-silicon substrate to a first etch depth, thereby forming sidewalls of the structure. The sidewalls are then coated with a protection layer, and the substrate is dry etched to a second etch depth to define a spacing of the structure from the substrate. A selective anisotropic wet etchant (e.g. KOH, EDP, TMAH, NaOH or CsOH) is used to laterally undercut the structure between the first and second etch depths, thereby forming a substantially planar lower surface of the structure along a {111} crystal plane that is parallel to an upper surface of the structure.

Abstract: A method for forming a patterned layer within a microelectronics fabrication. There is first provided a substrate. There is then formed over the substrate a blanket chlorine containing plasma etchable layer. There is then formed upon the blanket chlorine containing plasma etchable layer a blanket hard mask layer. There is then formed upon the blanket hard mask layer a patterned photoresist layer. There is then etched the blanket hard mask layer to form a patterned hard mask layer while employing a first plasma etch method in conjunction with the patterned photoresist layer as a first etch mask layer. There is then etched the blanket chlorine containing plasma etchable layer to form a patterned chlorine containing plasma etchable layer while employing a second plasma etch method in conjunction with at least the patterned hard mask layer as a second etch mask layer.

Abstract: A method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as an plasma treatment, on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densified surface of the dielectric layer is able to efficiently prevent the occurrence of poisoned trenches and vias caused by the outgassing phenomena.

Abstract: A self-aligned via process to prevent the via poisoning includes forming a hydrogen silsesquioxane layer on the substrate and over a pre-formed metal layer, forming an etching stop layer on the hydrogen silsesquioxane layer, forming an oxide layer on the etching stop layer, and then proceeding with a two-step etching process to form a via. The two-step etching process first patterns the oxide layer using a patterned photoresist layer as a mask, and then patterns the etching stop layer together with the hydrogen silsesquioxane layer using the patterned oxide layer as a mask. Because the etching stop layer prevents the hydrogen silsesquioxane layer from reacting with the oxygen plasma during the photoresist layer removal process, via poisoning is eliminated.

Abstract: A method for microscopically smoothing a surface of a wafer made of silicon single crystal having a low resistivity. In the method, a native oxide film grown on a surface of a wafer having polished by an ordinary mirror polishing process is removed at a temperature of less than 100.degree. C. with use of a mixture gas of HF and H.sub.2, and then an organic substance deposited thereon is removed at a temperature of less than 800.degree. C. with use of a mixture gas of HCl and H.sub.2. Re-growth of an oxide film is suppressed in a consistent H.sub.2 atmosphere, during which the wafer is substantially not varied in its surface roughness. Then the wafer is thermally treated in an H.sub.2 gas atmosphere at a temperature of not less than 800.degree. C. and less than 1000.degree. C.

Abstract: A plasma etch method for forming a patterned silicon nitride layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket silicon nitride layer. There is then formed upon the blanket silicon nitride layer a patterned photoresist layer. Finally, there is etched through a plasma etch method while employing the patterned photoresist layer as an etch mask layer the blanket silicon nitride layer to form a patterned silicon nitride layer. The plasma etch method employs an etchant gas composition comprising a perfluorocarbon etchant gas, a hydrofluorocarbon etchant gas and an oxygen etchant gas at a perfluorocarbon etchant gas flow rate, a hydrofluorocarbon etchant gas flow rate and an oxygen etchant gas flow rate which yields substantially no plasma etch bias of the patterned silicon nitride layer with respect to the patterned photoresist layer.

Abstract: A wafer having an interlayer insulating film on a silicon substrate and an Al alloy layer on the interlayer insulating film coated with a resist pattern is introduced into an etching chamber where the Al alloy layer is selectively etched in etchant gas plasma. A main etching process is performed under the etching conditions of a high plasma density until the interlayer insulating film 12 is exposed, and a succeeding over etching process is performed under the etching conditions of a low plasma density. A dry etching method and system is provided which can suppress generation of an abnormal shape or notch of a wiring pattern etched in low pressure and high density plasma, without sacrificing etching selectivity and with productivity being maintained high.

Abstract: The semiconductor masking device of the invention includes a first semiconductor mask for forming an interconnection on a semiconductor substrate and a second semiconductor mask for forming a resist pattern on an insulating film. The first semiconductor mask has three masking areas and the second semiconductor mask has two masking areas. Masking area intervals, that is, the distances between the three masking areas of the first semiconductor mask and the two masking areas of the second semiconductor mask, are all equal to one another.

Abstract: A method for minimizing the dimension of a contact forms a thick dielectric layer on a provided substrate first, and then forms a contact on the first dielectric layer and expose the substrate by performing a slope etching process. The contact with the target contact size is obtained by partially removing the thick dielectric layer. Since the target contact size is obtained by a self-aligned method, the upper diameter of the contact is not limited by a conventional fabrication process. Furthermore, after a contact is formed, it is optional to fill the contact with filler. Even after a desired contact is formed in the case that filler is used, the remains of the filler can be either kept or removed depending on the conductivity of the filler.

Abstract: A semiconductor processing method of forming a contact opening to a substrate includes forming at least one conductive line over the substrate adjacent a substrate contact area to which electrical connection is to be made. A first oxide layer is formed over the substrate to cover at least part of the contact area. A second oxide layer is formed over the first oxide layer and is formed from a different oxide than the first oxide layer. A first etch is conducted over the contact area and through the second oxide layer to a degree sufficient to leave at least a portion of the first oxide layer over the contact area. A second etch is conducted to a degree sufficient to remove substantially all of the first oxide layer left behind and to remove a desired amount of the second oxide layer laterally outwardly of the contact area.

Abstract: A method and an apparatus for depositing a dielectric layer to fill in a gap between adjacent metal lines. In preferred embodiments of the method, a first dielectric layer is deposited over the lines and subsequently etched using both chemical and physical etchback steps. After the etchback steps are completed, a second dielectric layer is deposited over the first dielectric layer to fill in the gap.

Abstract: A novel anisotropic plasma etching process for forming patterned silicon nitride (Si.sub.3 N.sub.4) layers with improved critical dimension (CD) control while minimizing the Si.sub.3 N.sub.4 footing at the bottom edge of the Si.sub.3 N.sub.4 pattern is achieved. A pad oxide/silicon nitride layer is deposited on a silicon substrate. A patterned photoresist layer is used as an etching mask for etching the silicon nitride layer. By this invention, a chlorine (Cl.sub.2) breakthrough plasma pre-etch forms a protective polymer layer on the sidewalls of the patterned photoresist and removes residue in the open areas prior to etching the Si.sub.3 N.sub.4. The Si.sub.3 N.sub.4 is then aniso-tropically plasma etched using an etch gas containing SF.sub.6. The polymer layer, formed during the Cl.sub.2 pre-etch, reduces the lateral recessing of the photoresist when the Si.sub.3 N.sub.4 is etched, and results in improved patterned Si.sub.3 N.sub.4 profiles with reduced CD bias, and minimizes Si.sub.3 N.sub.