Abstract: A fine pattern forming method of a semiconductor device sequentially deposits an etch-target layer to be formed as the fine pattern, an anti-reflective layer and a photoresist film on a prepared semiconductor substrate and forms a photoresist pattern by performing photolithography for the photoresist film with an ArF exposure source. Then, two etching processes are performed to form the fine pattern. In one etching process, there are etched the anti-reflective layer and a portion of a non-pattern area of the etch-target layer at a first substrate temperature with fluorine-based gas and argon gas by using the photoresist pattern as an etching mask. In the other etching process, there is etched a remaining portion of the non-pattern area of the etch-target layer at a second substrate temperature higher than the first substrate temperature with fluorine-based gas and argon gas.

Abstract: A method for manufacturing a field effect transistor includes a first step for etching 70%˜90% of the thickness of an insulating film (SiO2 or Si3N4) formed covering a gate electrode formed on a silicon semiconductor substrate; and a second step for etching a remaining insulating film to remove an unnecessary portion, other than sidewall spacers, of the remaining insulating film. The two etching steps are respectively for the purpose of vertical processing of the sidewall spacers formed on each side of the gate electrode and securing a high etch selectivity ratio of the insulating film to the silicon substrate.

Abstract: A method of etching a metallic layer having an anti-reflection layer thereon. The method includes performing a first etching operation using a fixed set of processing parameters to etch the anti-reflection layer and remove a specified thickness of the metallic layer. Thereafter, a second etching operation is conducted to etch the remaining metallic layer.

Abstract: A method and apparatus provide for etching a semiconductor wafer using a two step physical etching and a chemical etching process in order to create vertical sidewalls required for high density DRAMs and FRAMs.

Abstract: A method of smoothing a silicon surface formed on a substrate. According to the present invention a substrate having a silicon surface is placed into a chamber and heated to a temperature of between 1000°-1300° C. While the substrate is heated to a temperature between 1000°-1300° C., the silicon surface is exposed to a gas mix comprising H2 and HCl in the chamber to smooth the silicon surface.

Abstract: A substrate having a patterned mask and exposed openings is provided in a process chamber having process electrodes. In a plasma ignition stage, a process gas is provided in the process chamber and is energized by maintaining the process electrodes at a plasma ignition bias power level. In an etch-passivating stage, an etch-passivating material is formed on at least portions of the substrate by maintaining the process electrodes at an etch-passivating bias power level. In an etching stage, the exposed openings on the substrate are etched by maintaining the process electrodes at an etching bias power level.

Abstract: A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness.

Abstract: A method for fabricating a floating gate in a non-volatile memory device and a floating gate fabricated using the same are provided. A conductive layer having upper and lower portions is formed over a substrate with field regions formed therein. A hard mask layer is formed over the conductive layer. Next, a photoresist pattern is formed over the hard mask layer. The hard mask layer is etched to form a hard mask pattern, using the photoresist pattern as an etching mask. The upper portion of the conductive layer is slope-etched, leaving the lower portion of the conductive layer intact, using the photoresist pattern as an etching mask. The slope-etched upper portion of the conductive layer is again vertically etched and the lower portion of the conductive layer is concurrently slope-etched, using the hard pattern as an etching mask. With the present invention, a bridge between floating gates can be reduced, and field loss can be reduced during processing steps such as an ONO etching process.

Abstract: Method and apparatus for etching a tapered trench in a layer of material with a highly controllable wall profile. The layer of material has a mask adjacent a surface thereof having an opening which defines a location on the layer of material at which the trench is to be formed. Vertical etch process steps and opening enlarging process steps are then performed in an alternating manner until the trench has been etched to a desired depth. The method permits very deep tapered trenches of up to 80-100 um or more to be formed in a silicon substrate or other layer of material in a highly controllable manner. The method can be incorporated into processes for manufacturing numerous devices including MEMS devices and high power RF devices such as LDMOS and VDMOS devices.

Abstract: In a process of preparing a via in a semiconductor substrate wafer in which vias are landed on tungsten, and in which resist is stripped using plasma or chemical based processes that do not remove the veils formed during the etch, the improvement of concurrently removing veil material, controlling the interface of the tungsten, and stripping the resist, comprising: a) depositing and patterning tungsten on a substrate; b) depositing an oxide as an interlevel dielectric on the tungsten; c) patterning the oxide using photolithography and a photoresist; d) etching the oxide using a plasma generated etching method in which veils made up of metals, carbon based materials and oxide based materials are formed on the tungsten and sidewalls of the vias; and e) stripping the resist using a dry polymer removal method employing process gases and reducing gases to concurrently cause resist stripping, removal of the veils, and control of the tungsten interface.

Abstract: A structure of an amorphous-silicon thin film transistor array comprises a substrate, a gate electrode, a gate insulating layer, an amorphous-silicon active layer, an n+ amorphous-silicon layer and a metal layer. The metal layer defines a source electrode and a drain electrode. The structure simplifies the photolithography process by using a less number of masks to manufacture thin film transistors. It also reduces the occurrence of open circuits in the first metal (MI) layer or short circuits between the MI layer and the second metal (MII) layer caused by the photoresist residue or particle contamination. The manufacturing method combines a conventional back-channel-etched (BCE) reduced mask process and a two-step exposure technology. The two-step exposure technology uses two photoresist pattern masks. One is a pattern mask for complete exposure with higher light intensity and the other is a pattern mask for incomplete exposure with lower light intensity.

Abstract: A process increases the etch control on the thin gate oxidation near the edges of a poly-silicon or amorphous silicon gate stack, minimizing the formation of micro-trenches while achieving nearly vertical profiles. In an example embodiment, a method for manufacturing a semiconductor gate stack a gate stack having an anti-reflective coating, has a pattern defined with a photoresist mask The unmasked areas of the gate stack are etched with a first etch. The first etch removes the anti-reflective layer and a majority of the poly or amorphous silicon from the unmasked areas. After the first etch, the photoresist mask is removed. Using the anti-reflective coating as a hard mask the poly or amorphous silicon is removed with a second etch from unmasked areas until the gate oxide exposed. An over etch removes any poly or amorphous silicon residues.

Abstract: A method of forming a dual damascene opening, comprising the following steps. A semiconductor structure having at least one exposed metal line is provided. A spin-on-polymer layer is formed over the semiconductor structure and the metal line. A CVD low-k material layer is formed over the spin-on-polymer layer. The CVD low-k material layer is patterned to form a CVD low-k material layer via over the metal line. The spin-on-polymer layer is patterned to form a spin-on-polymer layer via opening continuous and contiguous with the CVD low-k material layer via and exposing a portion of the metal line. The CVD low-k material layer adjacent the CVD low-k material layer via is patterned to form a CVD low-k material layer trench. The spin-on-polymer layer via opening and the CVD low-k material layer trench forming a dual damascene opening.

Abstract: After making a GaN FET by growing GaN semiconductor layers on the surface of a sapphire substrate, the bottom surface of the sapphire substrate is processed by lapping, using an abrasive liquid containing a diamond granular abrasive material and reducing the grain size of the abrasive material in some steps, to reduce the thickness of the sapphire substrate to 100 &mgr;m or less. Thereafter, the bottom surface of the sapphire substrate is processed by etching using an etchant of phosphoric acid or phosphoric acid/sulfuric acid mixed liquid to remove a strained layer by lapping followed by making a via hole by etching the bottom surface of the sapphire substrate by using a similar etchant.

Abstract: A method for manufacturing a contact hole in a semiconductor device which includes the steps of preparing an active matrix provided with a substrate and word lines formed on the substrate, forming an etching barrier layer on the word lines and the substrate, forming an interlayer insulating layer on the etching barrier layer, forming a photoresist pattern on the interlayer insulating layer for defining a contact hole, etching the interlayer insulating layer under conditions of low polymerization until the etching barrier layer on the word lines is exposed, etching the interlayer insulating layer under conditions of high polymerization, and etching the interlayer insulating layer under conditions of low polymerization until the etching barrier layer in a bottom of the contact hole is exposed.

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: Etching method applicable to a semiconductor device fabrication and an MEMS(Micro-Electro-Mechanical System) process, including the steps of forming an etching mask on a substrate, forming a plurality of patterns in the etching mask corresponding to depths of the plurality of trenches; and etching the substrate using the etching mask having the plurality of patterns formed therein, whereby eliminating an alignment error in respective photolithography, that permits to form a precise structure, simplify a fabrication process, and reduce a production cost.

Abstract: A method of forming a shallow trench within a trench capacitor structure. This method can be used, for example, in the construction of a DRAM device.

Abstract: A method of fabricating a gate. A gate dielectric layer is formed, and a lower portion of a floating gate is formed encompassed by a first dielectric layer. Second dielectric layers with different etching rates are formed to cover the upper portion of the floating gate and the first dielectric layer. Using an etching mask, an opening is formed within the second dielectric layer to expose the floating gate and a portion of the second dielectric layers by performing an anisotropic etching process. Using the same etching mask, the second dielectric layers exposed within the opening is further etched by performing an isotropic etching process. Due to the different etching rates, a dielectric layer with an uneven and enlarged surface is formed. A conformal conductive layer is formed on the exposed lower portion of the floating gate and the exposed second dielectric layers as an upper portion of the floating gate.

Abstract: A method for fabricating an MOM capacitor (10) includes forming a first conductive layer (18) on an insulating support (12, 14), depositing a dielectric film (20) on the conductive layer, and patterning the dielectric film to define the capacitor feature. The dielectric film may comprise a stack of oxide and nitride layers (22, 24, 26). The dielectric is etched anisotropically with a fluorocarbon plasma to remove unwanted dielectric material (38) around the capacitor feature. Sidewalls (40), built up during the anisotropic etch as a result of sputtering the first conductive layer during the necessary overetch, are removed in a low power, higher pressure etch with an SF6 plasma, which is substantially isotropic in character. The process allows a sidewall-free capacitor to be formed in a single reactor without the need for solvent cleaning to remove the sidewall material.

Abstract: A method of cleaning polycide gates after an etching step. A gate oxide layer, a polysilicon layer, a titanium nitride layer, a silicide layer, an anti-reflection layer and a patterned photoresist layer are sequentially formed over a substrate. An etching operation is next carried out to form a gate structure. The gate structure is formed by patterning the polysilicon layer, the titanium nitride layer and the silicide layer. The gate structure is subsequently cleaned in a three-step cleaning operation. In the first cleaning step, minute amount of fluoride-containing compound, hydrogen and inert gas are used as gaseous reactants in a plasma-cleaning operation. The fluoride-containing compound is capable of initiating a free radical chain reaction. In the second cleaning step, a solvent containing ammonium ions is applied to the gate structure. In the third cleaning step, a solution formed by dissolving oxidizing agent in de-ionized water is applied.

Abstract: Disclosed is a novel method for fabricating a stencil mask comprising the formation of an absorber pattern, including an alignment key or target, on the topside of an SOI wafer having a transparent buried insulating layer. The formation of the absorber pattern is followed by the formation of an alignment window from the backside of the SOI wafer using the insulating layer as a lens. The alignment window allows the alignment between the absorber pattern and the frame pattern to be verified, using light passing through the window lens and illuminating the alignment key, before initiating the frame etch, thereby improving the quality and/or throughput of the stencil mask manufacturing process.

Abstract: There is described a method of manufacturing a semiconductor device for accurately and anisotropically etching desired locations on a semiconductor wafer at high selectivity. A polysilicon layer which is to act as a floating gate is embedded in the surface of an oxide film insulating layer. Control gates are formed in a direction orthogonal to the polysilicon layer. Exposed portions of the polysilicon layer are subjected to dry-etching, thereby forming a floating gate. Residues remaining in the channels formed in the oxide film insulating layer are removed by means of wet etching.

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: The present invention discloses the method of forming the bottom electrode with HSG (hemispherical grain) layer on substrate, said substrate comprising a word line and an active region, said method comprising the steps of: depositing a confomal etch stop layer on said active region and said word line; forming a dielectric layer on said etch stop layer with planar top surface; forming a contact hole in said. dielectric layer and said etch stop layer to expose portions of said active region and said word line; depositing a first conductive layer on the surface of the contact hole; forming a hemishperical grain (HSG) layer on said first conductive layer; and removing said dielectric layer.

Abstract: A method of profile control in metal etching, wherein a metal layer is positioned on a dielectric layer comprising an aluminum-alloy layer on the dielectric and an anti-reflection layer on the aluminum-alloy layer. The method of the present invention includes a step of performing a breakthrough step of a first etch recipe to remove the anti-reflection layer and a certain thickness of the aluminum-alloy layer until a predetermined depth is reached. The method then further includes a step of performing a main etch step of a second etch recipe having a higher etch rate than the first etch recipe to remove the remaining residue of the aluminum-alloy layer. The main object of the present invention is to achieve formations of metal lines with smooth and tapered sidewalls. Thereby, the method of the present invention reduces the possibility of forming voids during the subsequent deposition process, which improves the reliability of the IC devices made.

Abstract: The present invention relates to a method of etching tungsten or tungsten nitride in semiconductor structures, and particularly to the etching of gate electrodes which require precise control over the etching process. We have discovered a method of etching tungsten or tungsten nitride which permits precise etch profile control while providing excellent selectivity, of at least 175:1, for example, in favor of etching tungsten or tungsten nitride rather than an adjacent oxide layer. Typically, the oxide is selected from silicon oxide, silicon oxynitride, tantalum pentoxide, zirconium oxide, and combinations thereof. The method appears to be applicable to tungsten or tungsten nitride, whether deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

Abstract: A method for forming a protection device with slope laterals is provided. Firstly, providing a semiconductor substrate having a plurality of alternative first sacrificial layers and second sacrificial layers formed thereon. A first etching step is performed to remove one portion of each of the first sacrificial layers and thereby expose one portion of each lateral of each of the second sacrificial layers. Subsequently, performing a second etching step to remove one portion of the lateral of the second sacrificial layer. Then, repeatedly and alternately performing the first etching step and the second etching step until completely removing the first sacrificial layers and then obtaining a plurality of protection devices formed of the second sacrificial layers each of which having slope laterals.

Abstract: A method for forming a storage node contact plug of a dynamic random access memory includes forming insulating layers on an overall surface of a semiconductor substrate having a plurality of buried contact plugs, etching the insulating layers down to a top surface of the buried contact plugs to form first contact holes on the buried contact plugs, forming a photoresist pattern on the insulating layers and the first contact holes, etching the insulating layers to form second contact holes on the second insulating layer, and filling the first and second contact holes with conductive material.

Abstract: A method of manufacturing a template having through-holes for attracting and supporting electrically conductive balls by vacuum suction is disclosed. The through-holes are formed by etching and the side walls of the through-holes are smoothed by irradiation, with laser beams, of the side walls of the through-holes. A template and metallic bumps can be formed using this method. Alternatively, the template can be formed in a two-layered structure.

Abstract: A charge transfer device is provided, capable of preventing degradation of the charge transfer efficiency when the channel width becomes narrower due to the narrow channel effect. The charge transfer device of the present invention is obtained by forming a charge transfer electric field in a channel below a boundary portion between a terminal storage electrode and a terminal barrier electrode, which constitute a pair of charge transfer electrodes located closest to the output electrode, to be higher than a charge transfer electric field in a channel below a boundary portions of pairs of storage electrodes and barrier electrodes, which constitute pairs of storage electrodes and barrier electrodes other than the pair of the terminal electrodes.

Abstract: A second interlayer film is etched by an etching gas including fluorocarbon gas after a switch box is switched so that high frequency electricity is applied to an upper electrode. Then, the switch box is switched so that low power electricity is applied only to a lower-electrode/wafer-holder to generate plasma with using only fluorocarbon gas. The generated plasma etches a first interlayer film, and fluorine radicals dissociated from the fluorocarbon removes a hardened resist surface layer. It realizes etching with less damage on bases, because energy of incident ions is low.

Abstract: A method for manufacturing a trench gate structure of a power metal-oxide-semiconductor field-effect transistor. A substrate is provided, which substrate has a epitaxial layer thereon, a base region formed in the epitaxial layer, a source region formed in a portion of the base region, a first dielectric layer on the base region and the source region, a second dielectric layer on the first dielectric layer and a trench penetrating through the second and the first dielectric layers, the source region and the base region and into the epitaxial layer. A third dielectric layer is formed on the bottom of the trench. A conformal gate oxide layer is formed in the trench. A conformal polysilicon layer is formed on the second dielectric layer and in the trench. A fourth dielectric layer is formed on the polysilicon layer to fill the trench.

Abstract: The present invention relates to a method of etching tungsten or tungsten nitride in semiconductor structures, and particularly to the etching of gate electrodes which require precise control over the etching process. We have discovered a method of etching tungsten or tungsten nitride which permits precise etch profile control while providing excellent selectivity, of at least 175:1, for example, in favor of etching tungsten or tungsten nitride rather than an adjacent oxide layer. Typically the oxide is selected from silicon oxide, silicon oxynitride, tantalum oxide, zirconium oxide, and combinations thereof. The method appears to be applicable to tungsten or tungsten nitride, whether deposited by physical vapor deposition (PVD) of chemical vapor deposition (CVD).

Abstract: In one embodiment, a process for reducing the step height of shallow trench isolation structures includes the acts of (a) forming a hard mask on a semiconductor substrate to define a trench, (b) forming the trench, (c) filling the trench with a dielectric material, (d) planarizing the dielectric material,(e) replacing the hard mask with a resist mask, (f) etching back the dielectric material to reduce its step height, and (g) removing the resist mask. In another embodiment, the hard mask used to define the trench is used during the etch back of the dielectric material. In another embodiment, the hard mask used to define the trench is partially stripped before the dielectric material is planarized to reduce its step height.

Abstract: The method of the present invention applies to any semiconductor structure provided with polysilicon filled deep trenches formed in a silicon substrate coated by a Si3N4 pad layer both in the “array” and “kerf” areas. First, a photoresist mask is formed onto the structure and patterned to expose the deep trenches only in the “array” areas. Deep trenches are then anisotropically dry etched to create recesses having a determined depth. Next, the photoresist mask is removed only in the “array” areas. A step of anisotropic dry etching is now performed to extend said recesses down to the desired depth to create the shallow isolation trenches. The photoresist mask is totally removed. A layer of oxide (STI oxide) is conformally deposited by LPCVD onto the structure to fill said shallow isolation trenches in excess. The structure is planarized to create the STI oxide regions and expose deep trenches in the “kerf” areas.

Abstract: A method of manufacturing a semiconductor substrate can effectively prevent a chipping phenomenon and the production of debris from occurring in part of the insulation layer and the semiconductor by removing a outer peripheral portion of the semiconductor substrate so as to make the outer peripheral extremity of the insulation layer to be located between the outer peripheral extremity of the semiconductor layer and that of the support member and hence the semiconductor layer and the insulation layer produce a stepped profile.

Abstract: A method of manufacturing a semiconductor device having a trench isolation structure includes patterning a mask film on a semiconductor substrate, forming a trench by etching the semiconductor substrate by use of the mask film, filling the trench with an insulating film by repeating depositing the insulating film in the trench and etching the insulating film by sputter etching, removing the mask film, and removing the insulating film by etching a predetermined amount of the insulating film filled in the trench. According to the sputter etching in the step of filling the trench with the insulating film, an edge between a surface of the substrate and an inner wall surface of the trench forms an inclined surface to the surface of the substrate.

Abstract: A system and method for reducing contamination in a semiconductor device formed on a substrate is disclosed. The method and system include providing a barrier metal layer on the substrate. A first portion of the barrier metal layer is thinner than a second portion of the barrier metal layer. The method and system further include removing the first portion of the barrier metal layer.

Abstract: A method for forming a patterned silicon containing layer. There is first provided a substrate. There is then formed over the substrate a blanket silicon containing layer. There is then formed over the blanket silicon containing layer a patterned photoresist layer. There is then etched, while employing a first plasma etch method in conjunction with the patterned photoresist layer as a first etch mask layer, the blanket silicon containing layer to form a partially etched blanket silicon containing layer. The first plasma etch method employs a first etchant gas composition comprising an etchant gas which upon plasma activation forms an active fluorine containing etchant species. There is then etched, while employing a second plasma etch method in conjunction with the patterned photoresist layer as a second etch mask layer the partially etched blanket silicon containing layer to form a fully patterned silicon containing layer.

Abstract: A method of manufacturing a contact of a semiconductor device includes a series of pretreatment processes each performed in a plasma pretreatment module. A semiconductor substrate has an interlayer formed on an underlayer of a material containing silicon. A contact hole is formed in the interlayer to expose a surface of the underlayer. Subsequently, the semiconductor substrate is loaded into a plasma pretreatment module. The photoresist pattern is removed by ashing in the plasma pretreatment module. A damaged layer at the surface exposed by the contact hole is then removed in the plasma pretreatment module. Subsequently, the semiconductor substrate is pre-cleaned in the plasma pretreatment module. The semiconductor substrate is then transferred, while in a vacuum, to a deposition module. There, an upper layer is formed on the substrate to fill the contact hole. SEC.

Abstract: A method of selective epitaxial growth performed by sequentially and repeatedly introducing a source gas, an etching gas, and a reducing gas in the reaction chamber, wherein controlled epitaxial layer doping may be obtained by introducing a dopant source gas during introducing any one of the source gas, an etching gas, and a reducing gas, and thereby producing a smooth and uniform epitaxial layer on a predetermined region of a semiconductor substrate.

Abstract: Within a method for forming an aperture fill layer within a aperture, there is first provided a topographic substrate having an aperture formed therein. There is then formed over the topographic substrate and filling the aperture a blanket aperture fill layer. There is then planarized, while employing a first chemical mechanical polish (CMP) planarizing method, the blanket aperture fill layer to form a blanket planarized aperture fill layer while not reaching the topographic substrate. Finally, there is then planarized, while employing a second planarizing method, the blanket planarized aperture fill layer to form within the aperture a patterned planarized aperture fill layer. The two step planarizing method may be employed for forming with enhanced planarity and attenuated topographic substrate erosion a patterned planarized aperture fill layer, such as a patterned planarized trench isolation region, within a topographic substrate, such as a topographic semiconductor substrate.

Abstract: A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.

Abstract: A method of manufacturing a semiconductor device by forming layers of materials on a semiconductor substrate and utilizing a series of etch chemistries to remove portions of the layers of materials to form a metal stack. A patterned layer of photoresist determines the portions of the layers that will be etched. An etch process etches a hardmask material, a breakthrough etch process etches an antireflection layer, a conventional main etch process etches approximately 80 percent of the metal film, a first overetch process for a first selected period of time and a second overetch process for a second selected period of time provides a metal film stack having straight profiles and smooth sidewalls.

Abstract: A method is disclosed for fabricating a semiconductor device structure which include a thin foot charge drain beneath the device on a silicon substrate. The structures retain high speed operation of SOI devices. In various embodiments, the invention includes forming a first diffusion-barrier layer on a semiconductor substrate, patterning the said first diffusion-barrier layer and the said silicon substrate to certain depth to form a trench, forming a second diffusion-barrier layer and patterning the said second diffusion-barrier layer to form a first spacer on the sidewall of the trench. Performing a directional etching to expose a portion of the sidewall of the trench. Introducing dopants into the said exposed sidewall to form a doped regions near the sidewall. Performing an isotropic etching using halogen gas plasma.

Abstract: Two-step process to improve low-K dielectric etch uniformity, apparatus to perform the method, and semiconductor devices formed in accordance with the method. In a first etching step, an insulating hot edge ring is provided. When the photoresist clearing signal is observed using end-point software, the insulating cover is moved aside to expose the conductive edge ring for the remainder of the etch. One aspect of this invention contemplates an insulator cover over a conductive edge ring at the start of wafer etching, which cover is removed after end-pint detection. The present invention contemplates a number of physical configurations whereby the insulator ring is urged into, and away from, its masking of the conductive edge ring. Alternatively, the etching of a wafer bearing low-K material may be conducted using two edge rings, where the first etch step is conducted using an insulating hot edge ring, and a second etch step is conducted using a conductive hot edge ring.

Abstract: A circuit device is disclosed comprising at least two circuit layers or circuit devices vertically interconnected with a plurality of parallel and substantially equi-length nanowires disposed therebetween. The nanowires may comprise composites, e.g., having a heterojunction present along the length thereof, to provide for a variety of device applications. Also disclosed is a method for making the circuit device comprising growing a plurality of nanowires on a dissolvable or removable substrate, equalizing the length of the nanowires (e.g., so that each one of the plurality of nanowires is substantially equal in length), transferring and bonding exposed ends of the plurality of nanowires to a first circuit layer; and removing the dissolvable substrate. The nanowires attached to the first circuit layer then can be further bonded to a second circuit layer to provide the vertically interconnected circuit device.

Abstract: An improved etch of thick protective topside stack films, which cover metal pads of a semiconductor device. The invention uses a downstream plasma isotropic etch to etch the topside stack film. In one embodiment, the downstream plasma isotropic etch is used to etch only part of the topside stack films. A subsequent anisotropic oxide plasma etch is used to etch the remaining topside stack film to the metal pads. In another embodiment, the downstream plasma isotropic etch is used to etch completely through the topside stack films to the metal pad. The invention allows the etching through topside stack films greater than 5 microns.

Abstract: In a wafer treatment apparatus, a hydrofluoric acid gas supply pipe and an evacuation pipe are connected to a chamber storing a wafer for performing prescribed treatment. A control part is provided for controlling supply of hydrofluoric acid gas. The control part sets a time for supplying the hydrofluoric acid gas into the chamber to be longer than a time up to starting of etching of a reaction product and shorter than a time up to starting of etching of a gate insulator film. Thus, only the reaction product can be substantially etched without etching the gate insulator film.