Abstract: A dry etch using CFx in an O2-rich environment will clean the contact/via at the same time it retracts a layer of TiN enclosed in the dielectric layer, such as the plate layer in a Capacitor-Under-Bitline DRAM cell.

Abstract: Disclosed are improved and simplified methods of forming trench isolation regions. A photoresist pattern having an opening therein is directly formed on a bare semiconductor substrate. The bare semiconductor substrate is etched through the opening in the photoresist pattern to form a trench in the substrate. The photoresist pattern is then isotropically etched to enlarge the size of the opening. A spin-on material layer is coated overlying the substrate surface to fill the trench and the enlarged opening, and then etched back until the photoresist pattern is exposed. After removing the photoresist pattern, the spin-on material layer is cured to form a trench isolation region which are less susceptible to edge defects.

Abstract: A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000 watts under a pressure of 50-400 mTorr. The gas mixture includes 2-30 sccm of C4F8, 20-80 sccm of CO, 2-30 sccm of O2 and 50-400 sccm of Ar. Gas flow can be adjusted to an optimum level, thereby achieving a high degree of uniformity. Wafers falling below a selected uniformity may be reworked. A damascene wiring layer formed in the trenches with an acceptable flow exhibit a high degree of sheet resistance uniformity and improved line to line shorts yield.

Abstract: An improved method for forming a dual damascene structure is described. A via opening of the dual damascene structure is formed in a dielectric layer. A non-conformal cap layer is then formed on the substrate before the step of defining the photoresist layer. The non-conformal cap layer only covers the top region of the trench but does not fill the trench. A patterned photoresist layer is then formed on the substrate followed by an etching procedure so as to form a trench. The photoresist layer is then removed. The trench and via opening are filled with a conductive layer. Thereafter, redundant portions of the conductive layer are removed by a planarization process.

Abstract: A method of limiting surface damage during reactive ion etching of an organic polymer layer on a semiconductor substrate combines particular choices of process gases and plasma conditions with a post-etch passivation treatment. According to the method, a low density plasma etcher is used with a process gas mixture of one or more of an inert gas such as argon, helium, or nitrogen; methane; hydrogen; and oxygen, where the percentage of oxygen is up to about 5%. Typically a parallel plate plasma etcher is used. The reactive ion etching is followed by a post-etch passivation treatment in a which a gas containing hydrogen is flowed over the etched layer at an elevated temperature. The method is particularly useful in reactive ion etching of fluorinated organic polymer layers such as films formed from parylene AF4, and layers of poly(arylene ethers) and TEFLON®.

Abstract: The present invention provides a method of forming a self-aligned contact hole on a semiconductor wafer. The semiconductor wafer comprises a substrate, two gates positioned on the substrate, at least a doped area between the gates on the substrate and spacers on each of two opposite walls of each gate wherein the spacers between the gates are joined and cover the doped area. The method comprises forming a dielectric layer on the surface of the semiconductor wafer, the dielectric layer covering the gates and the spacers. A first etching process is performed to remove the dielectric layer above the doped area down to a predetermined depth to form an opening, the bottom of the opening comprising the spacers and an upper portion of the gates. Poly-silicon spacers are then formed on the interior walls of the opening, the poly-silicon spacers covering an upper portion of the spacers and the upper portion of the gates.

Abstract: A method for forming an ink jet nozzle plate includes providing a structure having a top substrate layer, a bottom substrate layer, and a buried layer disposed between the top substrate layer and the bottom substrate layer; providing a patterned bore mask having openings which extend to the top substrate layer; anisotropically etching through the openings through the top substrate layer, the buried layer, and into a portion of the bottom substrate layer; providing a bore liner into the openings formed through the top substrate layer, the buried layer, and into the etched portion of the bottom substrate layer; removing the bore mask and providing a cavity mask having openings aligned with the bore liners; anisotropically etching the top substrate layer to expose the bore liners; and removing the cavity mask and providing an ink jet nozzle plate layer over the top substrate layer and extending to be in contact with the bore liners to form bore regions in the ink jet nozzle plate layer; attaching the ink jet noz

Abstract: In but one aspect of the invention, a plasma etching method includes forming polymer material over at least some internal surfaces of a dual powered plasma etch chamber while first plasma etching an outer surface of a semiconductor wafer received by a wafer holder within the chamber. After the first plasma etching, second plasma etching is conducted of polymer material from the chamber internal surfaces while providing a bias power at the wafer holder effective to produce an ac peak voltage at the wafer surface of greater than zero and less than 200 Volts. In one implementation, second plasma etching is conducted of polymer material from the chamber internal surfaces while providing a bias power at the wafer holder of greater than zero Watts and less or equal to about 1 Watt/cm2 of wafer surface area on one side.

Abstract: In modern sub-micron technologies with aggressive design rules, it is not always possible to have complete overlap of conductive lines with underlying vias. A process for manufacturing a semiconductor device having metal interconnects reduces or eliminates the recessing of metal in the vias, particularly when the metal in the vias is aluminum or an aluminum alloy. By manipulating the etch chemistry so that the etch rates of the aluminum alloy, the surrounding barrier metals, and the dielectric are comparable, it is possible to perform the metal over etch without forming voids in the exposed portion of the via. By eliminating the voids, thinning of the vias due to the presence of recesses is minimized, and electrical connections are less susceptible to electromigration. Consequently, device yield and reliability are increased.

Abstract: A method for forming a square oxide structure or a square floating gate without a rounding effect at its corners. A first dielectric layer is formed on a pad layer for a square oxide structure or a polysilicon layer overlying a gate oxide layer for a floating gate, and a second dielectric layer is formed on the first dielectric layer. The second dielectric layer is patterned to form parallel openings in a first direction using a first photosensitive mask. A second photosensitive mask, having a plurality of parallel openings in a second direction perpendicular to the first direction is formed over the second dielectric layer and the first dielectric layer. The first dielectric layer is etched through square openings where the openings in the second photosensitive mask and the openings in the second dielectric layer intersect, thereby forming square openings in the first dielectric layer. The second photosensitive mask and the second dielectric layer are removed.

Abstract: A method for removing residual photoresist and polymer residues from silicon wafers after a polysilicon plasma etch with minimal gate oxide loss is described. The method is particularly useful for cleaning wafers after polysilicon or polycide gate etching in MOSFET with when very thin gate oxides (<100Å). In order to etch the final portion of the polysilicon gate structure including an over etch to removed isolated polysilicon patches, an etchant containing HBr is used to provide a high polysilicon to gate oxide selectivity. This etch component causes a polymer veil to form over the surface of the photoresist which is difficult to remove except by aqueous etchants which also cause significant gate oxide loss. The method of the invention addresses the removal of the veil polymer, the photoresist, and a sidewall polymer by an all dry etching process.

Abstract: The present invention relates to the reduction of poisoned vias in a submicron process technology semiconductor wafer by reducing the occurrence of over-etched vias through the inclusion of an etch-stop layer. Vias are created to connect conductive portions of a semiconductor wafer and if the vias are over-etched, the connection may be poor. In order to prevent the over-etching of vias, a three-step etch process is completed on a semiconductor wafer having an insulating layer, an etch-stop layer, a low dielectric constant layer, a conductive layer and a foundation layer. A via is first non-selectively etched such that the etch terminates within the insulating layer. The via is subsequently selectively etched such that the etch terminates at the etch-stop layer. Lastly, the via is again non-selectively etched through the etch-stop layer and the low dielectric constant layer such that the etch terminates at the conductive layer.

Abstract: A method of improving an etch back process. A substrate having a metal layer formed thereon is provided. A main etching is performed over the metal layer to form an interconnect. A first over etching is performed over a metal residue left after the main etching. A gas flush and second over etch are performed.

Abstract: A method for providing semiconductor openings having a substantially straight wall or other desired etch profile. An etchable material layer is formed having target dopant levels or other etch rate varying characteristics to compensate for the characteristics of a selected etching process to achieve the desired etch profile. The etching process may also be varied to further match the characteristics of the etchable material layer.

Abstract: A method for fabricating a semiconductor device according to the present invention includes the steps of: a) forming an insulator film having Si—H bonds; b) forming a resist mask over a selected region of the insulator film; c) etching part of the insulator film that is not covered with the resist mask, thereby forming a recess in the insulator film; and d) removing the resist mask. The step d) includes the step of e) ashing the resist mask by using plasma produced from a gas comprising water vapor as a main component.

Abstract: The poor uniformity of Interlevel Dielectric Deposition (ILD) thickness for High Aspect Ratio (HAR) contact after Chemical Mechanical Planarization (CMP) will cause serious underlayer loss due to the longer over-etching time that is required to compensate for thickness differences within the wafer. Prior Art uses 1.5K Plasma Enhanced Tetra-Ethyl-Ortho-Silicate (PETEOS) to serve as a stop layer and thus reduce underlayer loss. The present invention teaches using a non-silicon oxide containing SiN/SiON or Si3N4/SiON as a stop layer. The present invention therefore is aimed at reducing underlayer loss and thereby improving the uniformity of the underlayer thickness upon completion of the hole etching process. Concurrently, the over-etch time can be reduced to less than 10% of the time required for Prior Art contact hole etching.

Abstract: A method or process for etching a trench in an IC structure is disclosed. The IC structure might be comprised of a plurality of different component materials arranged proximate to one another, all of which need to be etched down to a target level. A first etching chemistry is applied which preferentially etches a one type of component material. A second etching chemistry is applied which preferentially etches another type of component material. The method or process toggles back and forth between the etching chemistries until the target level is reached. The toggling techniques serves to maintain the profiles of the different component materials. One component material might also be embedded, as a collar or otherwise, around another component material. The toggling technique can serve to modulate the height, level, or shape of one material relative to another material. The toggling steps can be performed in situ or ex situ.

Abstract: A method of forming a PE-CVD silicon nitride spacer having a good profile in the fabrication of a self-aligned contact wherein a two-step etching process forms the spacer is described. Semiconductor device structures are formed on a semiconductor substrate. A layer of silicon nitride is deposited by plasma-enhanced chemical vapor deposition over the surface of the substrate and overlying the semiconductor device structures. The silicon nitride layer is etched away using a two-step etching process to leave silicon nitride spacers on the side surfaces of the semiconductor device structures. The two-step process comprises a first etching away of 70% of the silicon nitride layer using Cl2/He chemistry and a second etching away of the remaining silicon nitride on top surface of the semiconductor device strucutures using SF6/CHF3/He chemistry.

Abstract: This invention teaches methods and apparatus for forming self-aligned photosensitive material spacers about protruding structures in semiconductor devices. One embodiment of the invention is a method for forming a lightly doped drain (LDD) structure, utilizing disposable photosensitive material spacers. A second embodiment of the invention comprises a method for forming a transistor, having salicided source/drain regions, utilizing photosensitive polyimide spacers for forming the salicided source/drain regions, without disposing of the spacers. A third embodiment of the invention comprises a method for creating an offset from a protruding structure on a semiconductor substrate, using disposable photosensitive material spacers.

Abstract: A method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as an implantation process, on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densified surface of the dielectric layer is able to efficiently prevent the occurrence of poisoned trenches and vias caused by the outgassing phenomena.

Abstract: This invention teaches methods and apparatus for forming self-aligned photosensitive material spacers about protruding structures in semiconductor devices. One embodiment of the invention is a method for forming a lightly doped drain (LDD) structure, utilizing disposable photosensitive material spacers. A second embodiment of the invention comprises a method for forming a transistor, having salicided source/drain regions, utilizing photosensitive polyimide spacers for forming the salicided source/drain regions, without disposing of the spacers. A third embodiment of the invention comprises a method for creating an offset from a protruding structure on a semiconductor substrate, using disposable photosensitive material spacers.

Abstract: A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multi-level metal integrated circuits.

Abstract: A method that teaches the formation of deep trenches within the surface of a semiconductor wafer, these deep trenches are used to separate the wafer into individual chips by applying stress to the wafer. The formation of the deep trenches uses exposing a thick layer of photoresist followed by etching. The etching is a two step etch, a stabilization etch and a main etch. The stress used to separate the wafer into individual chips can be invoked by applying physical force to the wafer.

Abstract: A method for forming an ink jet nozzle plate includes providing a buried layer over a bottom substrate layer; providing and patterning a top substrate layer over the buried layer and having openings having inclined walls; providing an ink jet nozzle plate layer over the patterned top substrate layer and into the openings formed in the patterned top substrate layer, the ink jet nozzle plate layer contacting the buried layer; attaching the ink jet nozzle plate layer to a base having ink delivery channels; removing by etching the bottom substrate layer; and providing bore regions into the ink jet nozzle plate layer with each bore region corresponding to a delivery channel.

Abstract: A method for improving the efficiency of a plasma process such as a sputter process. A low partial pressure of a gas such as oxygen liberated from a substrate in a reaction chamber is maintained. The low partial pressure may be maintained by providing a plasma gas having a mass that is about equal to or greater than the liberated gas to the reaction chamber at a rate so that the steady state ratio of the plasma gas to the liberated gas is at least 1. The plasma gas is preferably argon. Alternatively a low partial pressure may be maintained by providing an in situ getter or a reactive, condensation or selective pump in the chamber. The method is applicable to a sputter etch or a sputter deposition process.

Abstract: Methods and compositions for treating a wafer's layer stack following metal etching are provided. The methods involve providing a semiconductor wafer layer stack in a plasma processing system following metal etch, and treating the layer stack with one or more process gases in a plasma processing system, where at least one of the process gases contains helium and water and/or oxygen, or comparable gases. The methods and compositions reduce corrosion and polymer fence for a wafer's layer stack relative to conventional passivation and strip processes without helium, decrease the time necessary for passivation, increase the strip rate, and/or improve strip uniformity.

Abstract: A method for forming a self-align stop layer for borderless contact process is disclosed. In one embodiment, the present invention provides a semiconductor device which can simplify borderless contact fabrication, which includes providing a substrate incorporating a device. Sequentially, a pad oxide, a pad polysilicon, and a first dielectric layer are formed over the substrate. A first photoresist layer is formed over the first dielectric layer and then the first dielectric layer, the pad polysilicon, the pad oxide, and the substrate are etched using the photoresist layer as a mask to form an isolation inside said substrate. Consequentially, a second dielectric layer is deposited over the device and the isolation inside the substrate. The second dielectric layer is removed wherein the surface of the second dielectric layer is lower than the top surface of the substrate by a chemical mechanical polishing (CMP) and etching back.

Abstract: A method for producing an electronic device, comprises the steps of: depositing a thin film on a substrate; etching a portion of the thin film by a reactive ion etching so as to leave a remaining portion of the thin film behind; and removing the remaining thin film by a physical etching using an inert gas.

Abstract: The present invention relates to semiconductor manufacturing field, more particularly, to a process of forming a charge storage electrode to which a selective hemispherical grains (HSG) silicon film is applied. The object of the present invention is to provide a method of forming a charge storage electrode having the selective HSG silicon film in semiconductor device which can secure a sufficient capacitor effective surface area by obtaining desired grain size at the time of selective HSG silicon film formation. The present invention prevents remaining of carbon component which obstructs the growth of HSG silicon film after dry etching process by limiting the carbon halide gas used in dry etching process of amorphous silicon film for defining the charge storage electrode at the time of process of forming the charge storage electrode having selective HSG silicon film.

Abstract: A process to obtain a level top surface topography, for a semiconductor chip comprised with high step height, DRAM crown shaped capacitor structures, as well as comprised with lower step height, peripheral logic devices, has been developed. The process features the use of selective vapor HF procedures, removing insulator layers only from regions located between individual DRAM crown shaped storage node structures. The polysilicon layer, used for the upper plate structure, fills the space between individual crown shaped storage node structures, allowing a level top surface topography for the semiconductor chip to be realized, featuring an upper plate structure, as the top surface of the DRAM region, while the peripheral, logic device region, at the same level as the top of the DRAM crown shaped capacitor structures, is encased in insulator layers.

Abstract: A method of manufacturing a semiconductor device includes: a step of forming a conductive layer on a semiconductor substrate, the conductive layer being made of aluminum or aluminum alloy; a step of forming a resist pattern on the conductive layer, the resist pattern having an opening pattern including a narrow space having a high aspect ratio and an open space having a low aspect ratio; a main etching step of dry-etching the conductive layer by using the resist mask as an etching mask, wherein the conductive layer is almost etched in the open space having the low aspect ratio and not fully etched in the narrow space having the high aspect ratio; and an over etching step of further dry-etching the conductive layer by using the resist mask as an etching mask and by using as etchant a mixed gas of HCl gas and at least one species of gas selected from the group consisting of He, Ar, Ne and H2.

Abstract: In a semiconductor device manufacturing method includes the steps of uniformly applying a first photoresist onto a first layer on a semiconductor substrate, a first resist pattern is formed out of the first photoresist by using a first photomask. The first layer is etched by using the resist pattern, thereby forming a first pattern. A second photoresist is uniformly applied onto the semiconductor substrate where the first pattern is formed. A second resist pattern is formed out of the second photoresist by using a second photomask. The first pattern is etched by using the second photoresist, thereby forming a second pattern constituted by the first layer. A semiconductor device fabricated by this method is also disclosed.

Abstract: A method of forming a multi-layered dual-polysilicon structure that forms a polysilicon gate prior to formation of an ion implantation barrier and that requires fewer steps, is more economical, and permits fabrication of more compact semiconductor circuits and devices than prior art methods.

Abstract: A method of etching a silicon layer in a plasma etching reactor to form an ultra deep opening is disclosed. The method includes the steps of providing a semiconductor substrate including the silicon layer into the plasma etching reactor and flowing an etching gas that includes an oxygen reactant gas, a helium gas, and an inert bombardment-enhancing gas into the plasma etching reactor. The method further includes striking a plasma using the etchant gas chemistry, and then providing an additive gas having SF6 into the plasma etching reactor subsequent to striking the plasma. The method continues with etching an opening at least partially through the silicon layer using this plasma.

Abstract: The present invention provides a method for monitoring a self-aligned contact (SAC) etching process. A wafer with an oxide layer serves as an oxide control wafer. The oxide layer is formed on the substrate. The oxide control wafer and a SAC wafer with SAC structure are simultaneously treated with a SAC etching process in an etching chamber with the same etching recipe. A contact hole is formed by etching the oxide layer of the oxide control wafer after the SAC etching process. The depth of a profile transition point and the depth of etching stop for the oxide control wafer can be observed by cross-section SEM. The profile transition depth in the oxide control wafer corresponds to the etching thickness of SiN corner loss in the SAC wafer. Therefore, the profile transition depth and the depth of etching stop in the oxide control wafer can be used to monitor the etching chamber condition.

Abstract: A new method is provided for the creation of spacers for the CMOS gate electrode. A layer of a spacer material is deposited over the gate structure; a layer of photoresist is deposited over the layer of spacer material. The layer of photoresist of the invention is partially stripped removing the photoresist from above the gate structure and providing a thinner layer of photoresist over the surrounding layer of spacer material. The layer of spacer material is partially etched whereby the layer of photoresist serves as a partial etch stop layer. The remainder of the photoresist is removed, the spacer material is further etched using a dry etch whereby a thin layer of spacer material (oxide) remains deposited over the surface of the substrate. As a final step the thin layer of spacer material (oxide) is removed from the surface of the substrate using a wet etch.

Abstract: A method for producing at least one semiconductor body by metal organic vapor phase epitaxy (MOVPE). The semiconductor body is formed of a layer sequence with an active zone applied to a semiconductor wafer. By dry etching, the layer sequence is provided with at least one mesa trench whose depth is at least great enough that the active zone of the layer sequence is severed. Next, the composite including the semiconductor wafer and the layer sequence is severed in such a way that the at least one semiconductor body is created with at least one mesa edge.

Abstract: A method for treating a film of material, which can be defined on a substrate, e.g., silicon. The method includes providing a substrate comprising a cleaved surface, which is characterized by a predetermined surface roughness value. The substrate also has a distribution of hydrogen bearing particles defined from the cleaved surface to a region underlying said cleaved surface. The method also includes increasing a temperature of the cleaved surface to greater than about 1,000 Degrees Celsius while maintaining the cleaved surface in a etchant bearing environment to reduce the predetermined surface roughness value by about fifty percent and greater. Preferably, the value can be reduced by about eighty or ninety percent and greater, depending upon the embodiment.

Abstract: In a plasma processing chamber, a method for etching through a selected portion of an oxide layer of a wafer's layer stack to create a self-aligned contact opening is described. The wafer stack includes a substrate, a polysilicon layer disposed above the substrate, a nitride layer disposed above said polysilicon layer and the oxide layer disposed above the nitride layer. The method for etching includes etching through the oxide layer of the layer stack with a chemistry and a set of process parameters. The chemistry essentially includes C.sub.2 HF.sub.5 and CH.sub.2 F.sub.2 and the set of process parameters facilitate etching through the oxide layer without creating a spiked etch and etching the oxide layer through to the substrate without substantially damaging the nitride layer.

Abstract: A method for forming a fine pattern in a semiconductor device removes roughness from a pattern produced in a fine pattern fabrication process using a silylation process as being one kind of a TSI process, eliminates smoothly a photosensitive film residue caused by a residue silylation layer remained on a-non-pattern area, and increases a margin of a lithography process. To achieve the foregoing, the method performs an etching process with a fluorine/oxygen mixture gas so as to remove a thin oxide film being formed on the non-pattern area after a silylation process, enables an edge portion of a silylation region to be planarized so as to prevent the pattern from becoming rough, and forms a photosensitive film pattern by developing the photosensitive film with oxygen plasma. Thereafter, the photosensitive film residue is etched again with a mixture gas of fluorine/oxygen, thereby increasing a fabrication margin of the fine pattern.

Abstract: Disclosed herein is a post-etch treatment for plasma etched metal-comprising features in semiconductor devices. The post-etch treatment significantly reduces or eliminates surface corrosion of the etched metal-comprising feature. It is particularly important to prevent the formation of moisture on the surface of the feature surface prior to an affirmative treatment to remove corrosion-causing contaminants from the feature surface. Avoidance of moisture formation is assisted by use of a high vacuum; use of an inert, moisture-free purge gas; and by maintaining the substrate at a sufficiently high temperature to volatilize moisture.

Abstract: The present invention provides an electron-beam cell projection aperture formation method comprising: a step of applying a converged ion beam to a top surface of a substrate so as to be etched to a depth enabling to obtain a sufficient film thickness for absorbing or scattering an electron-beam thereby to form an opening of a desired pattern on the top surface; and a step of uniformly applying the converged ion beam to a back surface of the substrate, excluding a hem portion thereof, so as to be etched to a depth reaching the opening.

Abstract: A method for manufacturing contact holes in a semiconductor device is provided. In this method, a semiconductor substrate, having first and second conductive regions formed therein, is provided. A lower interdielectric layer is formed on the substrate. An etching barrier layer is formed on the lower interdielectric layer. The etching barrier layer is etched to form a plurality of holes for defining contact holes to be formed in different interdielectric layers. Then, a contact hole is formed in the lower interdielectric layer, using one of the holes in the etching barrier layer as an etching mask, and then a conductive layer pattern filling the contact hole is formed. Subsequently, an upper interdielectric layer and a mask pattern are sequentially formed on the conductive layer pattern.

Abstract: A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and second conditions include the presence or absence of a deposit film, or the presence, absence or shape of a taper angle. Various parameters for controlling the first and second conditions are contemplated.

Abstract: The present invention is directed to wet processing methods for the manufacture of electronic component precursors, such as semiconductor wafers used in integrated circuits. More specifically, this invention relates to methods, for example, prediffusion cleaning, stripping, and etching of electronic component precursors using sequential chemical processing techniques.

Abstract: A new method of forming differential gate oxide thicknesses for both high and low voltage transistors is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas by shallow trench isolation regions. A polysilicon layer is deposited overlying a tunneling oxide layer on the surface of the substrate. The polysilicon and tunneling oxide layers are removed except in the memory cell area. An ONO layer is deposited overlying the polysilicon layer in the memory cell area and on the surface of the substrate in the low voltage and high voltage areas. The ONO layer is removed in the high voltage area. The substrate is oxidized in the high voltage area to form a thick gate oxide layer. Thereafter, the ONO layer is removed in the low voltage area and the substrate is oxidized to form a thin gate oxide layer.

Abstract: A multistep etch process for forming high aspect ratio trenches in silicon having a silicon oxide and/or silicon nitride hardmask. In a first step, an etch composition of HBr and oxygen is used, depositing a passivation layer on the sidewalls and producing slightly tapered openings. In the second step, an etch composition of a fluorine-containing gas such as SF.sub.6, HBr and oxygen is used, producing more vertical openings at a high etch rate. The taper of the openings during the second step can be controlled by adjusting the relative amount of HBr or SF.sub.6 employed. This process is a clean process that does not require cleaning of the etch chamber between etch steps.

Abstract: A method and apparatus provide for etching a semiconductor wafer using a two step physical etching and a chemical etching process in order to create vertical sidewalls required for high density DRAMs and FRAMs.

Abstract: Methods for monitoring defects in a process for forming a contact hole, via or trench in a layer of a device in an integrated circuit includes the steps of forming a sacrificial topology on a substrate by duplicating at least a portion of a structure of the device while substituting a material substantially free of elemental silicon for any elemental silicon present in the device to be monitored, etching the sacrificial topology at least to the substrate, removing at least a portion of the sacrificial topology, and inspecting the substrate using a wafer surface inspection tool. The substituted material, such as a dielectric material, can be easily etched and removed from the substrate, as compared to polysilicon. The etching step preferably creates an indentation in the substrate that is readily detectable by the wafer surface inspection tool. The etching step is preferably a selective etching step, having a selectivity of at least 10:1.

Abstract: A method for fabricating a passivation layer. An isolation layer is formed on a metal layer over the substrate. The isolation layer on the metal layer is removed by chemical-mechanical polishing and dry etching. The planarization of the metal layer thus is obtained. A passivation layer having a certain structure and a thickness combination of different layers is formed over the substrate. The reflection rate of the metal layer is significantly enhanced.