Vertically Arranged (e.g., Tandem, Stacked, Etc.) Patents (Class 438/74)
  • Patent number: 10147830
    Abstract: This invention relates to a method for producing solar cells, and photovoltaic panels thereof. The method for producing solar panels comprises employing a number of semiconductor wafers and/or semiconductor sheets of films prefabricated to prepare them for back side metallization, which are placed and attached adjacent to each other and with their front side facing downwards onto the back side of the front glass, before subsequent processing that includes depositing at least one metal layer covering the entire front glass including the back side of the attached wafers/sheets of films. The metallic layer is then patterned/divided into electrically isolated contacts for each solar cell and into interconnections between adjacent solar cells.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: December 4, 2018
    Assignee: REC SOLAR PTE. LTD.
    Inventors: Martin Nese, Erik Sauar, Andreas Bentzen, Paul Alan Basore
  • Patent number: 9912290
    Abstract: A method of high reverse current burn-in of solar cells and a solar cell with a burned-in bypass diode are described herein. In one embodiment, high reverse current burn-in of a solar cell with a tunnel oxide layer induces low breakdown voltage in the solar cell. Soaking a solar cell at high current can also reduce the difference in voltage of defective and non-defective areas of the cell.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: March 6, 2018
    Assignee: SunPower Corporation
    Inventors: Michael J Defensor, Xiuwen Tu, Junbo Wu, David Smith
  • Patent number: 9768329
    Abstract: An optoelectronic semiconductor device is disclosed. The optoelectronic device comprises a plurality of stacked p-n junctions. The optoelectronic semiconductor device includes a n-doped layer disposed below the p-doped layer to form a p-n layer such that electric energy is created when photons are absorbed by the p-n layer. Recesses are formed on top of the p-doped layer at the top of the plurality of stacked p-n junctions. The junctions create an offset and an interface layer is formed on top of the p-doped layer at the top of the plurality stacked p-n junctions. The optoelectronic semiconductor device also includes a window layer disposed below the plurality stacked p-n junctions. In another aspect, one or more optical filters are inserted into a multi-junction photovoltaic device to enhance its efficiency through photon recycling.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: September 19, 2017
    Assignee: ALTA DEVICES, INC.
    Inventors: Brendan M. Kayes, Gang He, Sylvia Spruytte, I-Kang Ding, Gregg Higashi
  • Patent number: 9459797
    Abstract: A method for fabricating a photovoltaic device includes applying a diblock copolymer layer on a substrate and removing a first polymer material from the diblock copolymer layer to form a plurality of distributed pores. A pattern forming layer is deposited on a remaining surface of the diblock copolymer layer and in the pores in contact with the substrate. The diblock copolymer layer is lifted off and portions of the pattern forming layer are left in contact with the substrate. The substrate is etched using the pattern forming layer to protect portions of the substrate to form pillars in the substrate such that the pillars provide a radiation absorbing structure in the photovoltaic device.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: October 4, 2016
    Assignee: GLOBALFOUNDRIES, INC
    Inventors: Christos Dimitrakopoulos, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 9099592
    Abstract: An optical element has a plano-plano body formed of a first material having a greater refraction index n1 and a second material having a lesser refraction index n2. Both indices are greater than one. The absolute value of the index contrast, log10 (n1/n2), is in the range from about 0.001 to about 0.17, preferably from about 0.01 to about 0.05. The materials have an induced absorbance rate ?Abs/Dose less than or equal to about 0.4, preferably less than or equal to about 0.2. The materials are arranged such that an interface with at least one cusp is defined therebetween. The cusp has an apex pointed toward the material having the greater index of refraction. The cusp is operative to produce a region of increased light intensity on one surface of the optical element in response to light incident on the other surface of the optical element.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: August 4, 2015
    Assignee: E I DU PONT DE NEMOURS AND COMPANY
    Inventors: Rebekah Ann Derryberry, Roger Harquail French, Mark E. Lewittes, Ronald Jack Riegert, Jose Manuel Rodriguez-Parada
  • Patent number: 9040342
    Abstract: A photovoltaic cell comprises a top subcell having a first band gap; a middle subcell comprising a substrate and having a second band gap, wherein the substrate comprises a first side and a second side opposite to the first side; and a bottom subcell having a third band gap, wherein the top subcell is grown on the first side of the substrate and the bottom subcell is grown on the second side of the substrate, wherein the first band gap is larger than the second band gap and the second band gap is larger than the third band gap.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: May 26, 2015
    Assignee: EPISTAR CORPORATION
    Inventor: Shiuan-Leh Lin
  • Publication number: 20150122995
    Abstract: A solid-state imaging device includes an Si substrate in which a photoelectric conversion unit that photoelectrically converts visible light incident from a back surface side is formed, and a lower substrate provided under the Si substrate and configured to photoelectrically convert infrared light incident from the back surface side.
    Type: Application
    Filed: October 27, 2014
    Publication date: May 7, 2015
    Inventors: Keiji Mabuchi, Hideshi Abe, Hideo Kanbe, Shiro Uchida
  • Publication number: 20150122313
    Abstract: The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a first substrate with a lower surface and an upper surface; providing a second substrate with a lower surface and an upper surface; bonding the first substrate to the second substrate at the upper surface of the first substrate and the lower surface of the second substrate; and subsequently forming at least one first solar cell layer on the lower surface of the first substrate and at least one second solar cell layer at the upper surface of the second substrate.
    Type: Application
    Filed: March 13, 2013
    Publication date: May 7, 2015
    Applicant: SOITEC
    Inventors: Bruno Ghyselen, Chantal Arena, Matteo Piccin, Frank Dimroth, Matthias Grave
  • Publication number: 20150104899
    Abstract: Manufacture of multi-junction solar cells, and devices thereof, are disclosed. The architectures are also adapted to provide for a more uniform and consistent fabrication of the solar cell structures, leading to improved yields and lower costs. Certain solar cells may further include one or more compositional gradients of one or more semiconductor elements in one or more semiconductor layers, resulting in a more optimal solar cell device.
    Type: Application
    Filed: December 19, 2014
    Publication date: April 16, 2015
    Inventors: David Ahmari, Swee Lim, Shiva Rai, David Forbes
  • Publication number: 20150099324
    Abstract: A method of fabricating on a semiconductor substrate bifacial tandem solar cells with semiconductor subcells having a lower bandgap than the substrate bandgap on one side of the substrate and with subcells having a higher bandgap than the substrate on the other including, first, growing a lower bandgap subcell on one substrate side that uses only the same periodic table group V material in the dislocation-reducing grading layers and bottom subcells as is present in the substrate and after the initial growth is complete and then flipping the substrate and growing the higher bandgap subcells on the opposite substrate side which can be of different group V material.
    Type: Application
    Filed: October 6, 2014
    Publication date: April 9, 2015
    Inventors: Steven J. Wojtczuk, Philip T. Chiu, Xuebing Zhang, Edward Gagnon, Michael Timmons
  • Publication number: 20150090321
    Abstract: A method of forming a multijunction solar cell comprising at least an upper subcell, a middle subcell, and a lower subcell, the method including forming a first alpha layer over said middle solar subcell using a surfactant and dopant including selenium, the first alpha layer configured to prevent threading dislocations from propagating; forming a metamorphic grading interlayer over and directly adjacent to said first alpha layer; forming a second alpha layer using a surfactant and dopant including selenium over and directly adjacent to said grading interlayer to prevent threading dislocations from propagating; and forming a lower solar subcell over said grading interlayer such that said lower solar subcell is lattice mismatched with respect to said middle solar subcell.
    Type: Application
    Filed: October 2, 2013
    Publication date: April 2, 2015
    Applicant: Emcore Solar Power, Inc.
    Inventors: Benjamin Cho, Yong Lin, Pravin Patel, Mark A. Stan, Arthur Cornfeld, Daniel McGlynn, Fred Newman
  • Patent number: 8994005
    Abstract: Devices (e.g., optoelectronic devices such as solar cells and infrared or THz photodetectors) with a nanomaterial having vertically correlated quantum dots with built-in charge (VC Q-BIC) and methods of making such devices. The VC Q-BIC material has two or more quantum dot layers, where the layers have quantum dots (individual quantum dots or quantum dot clusters) in a semiconductor material, and adjacent quantum dot layers are separated by a spacer layer of doped semiconductor material. The VC-QBIC nanomaterial provides long photocarrier lifetime, which improves the responsivity and sensitivity of detectors or conversion efficiency in solar cells as compared to previous comparable devices.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: March 31, 2015
    Assignee: The Research Foundation for The State University of New York
    Inventors: Vladimir Mitin, Andrei Sergeyev, Gottfried Strasser
  • Patent number: 8993411
    Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, defining a space for a pad in the back side dielectric layer and forming vias that pass through the back side dielectric layer and the anti-reflective layer and contact back sides of super contacts which are formed on the Si substrate, filling one or more metals in the vias and the defined space for the pad, and removing a remnant amount of the metal filled in the space for the pad through planarization by a CMP (chemical mechanical polishing) process.
    Type: Grant
    Filed: February 23, 2013
    Date of Patent: March 31, 2015
    Assignee: Siliconfile Technologies Inc.
    Inventors: Heui-Gyun Ahn, Se-Jung Oh, In-Gyun Jeon, Jun-Ho Won
  • Publication number: 20150083202
    Abstract: The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a first engineered substrate; providing a second substrate; forming at least one first solar cell layer on the first engineered substrate to obtain a first wafer structure; forming at least one second solar cell layer on the second substrate to obtain a second wafer structure; bonding the first wafer structure to the second wafer structure; detaching the first engineered substrate; removing the second substrate; and bonding a third substrate to the at least one first solar cell layer.
    Type: Application
    Filed: March 3, 2013
    Publication date: March 26, 2015
    Inventors: Bruno Ghyselen, Chantal Arena, Frank Dimroth, Andreas W. Bett
  • Publication number: 20150083204
    Abstract: A cell arrangement including a plurality of solar sub cells stacked above one another, wherein at least one solar sub cell of the plurality of solar sub cells comprises an alloy of gallium, nitrogen, arsenic and antimony.
    Type: Application
    Filed: February 25, 2013
    Publication date: March 26, 2015
    Inventors: Soon Fatt Yoon, Kian Hua Tan, Wan Khai Loke, Satrio Wicaksono, Daosheng Li
  • Publication number: 20150072464
    Abstract: A tandem photovoltaic cell. The tandem photovoltaic cell includes a bifacial top cell and a bottom cell. The top bifacial cell includes a top first transparent conductive oxide material. A top window material underlies the top first transparent conductive oxide material. A first interface region is disposed between the top window material and the top first transparent conductive oxide material. The first interface region is substantially free from one or more entities from the top first transparent conductive oxide material diffused into the top window material. A top absorber material comprising a copper species, an indium species, and a sulfur species underlies the top window material. A top second transparent conductive oxide material underlies the top absorber material. A second interface region is disposed between the top second transparent conductive oxide material and the top absorber material. The bottom cell includes a bottom first transparent conductive oxide material.
    Type: Application
    Filed: November 18, 2014
    Publication date: March 12, 2015
    Inventor: Howard W.H. Lee
  • Publication number: 20150053257
    Abstract: The present invention relates to a multi junction solar cell having at least four p-n junctions. The individual subcells thereby have band gaps of 1.9 eV, 1.4 eV, 1.0 eV and 0.7 eV. The multi junction solar cells according to the invention are used in space and also in terrestrial concentrator systems.
    Type: Application
    Filed: March 8, 2013
    Publication date: February 26, 2015
    Inventors: Frank Dimroth, Andreas Bett
  • Patent number: 8951827
    Abstract: Manufacture of multi-junction solar cells, and devices thereof, are disclosed. The architectures are also adapted to provide for a more uniform and consistent fabrication of the solar cell structures, leading to improved yields and lower costs. Certain solar cells may further include one or more compositional gradients of one or more semiconductor elements in one or more semiconductor layers, resulting in a more optimal solar cell device.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: February 10, 2015
    Assignee: EpiWorks, Inc.
    Inventors: David Ahmari, Swee Lim, Shiva Rai, David Forbes
  • Publication number: 20150027519
    Abstract: The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a first substrate, providing a second substrate having a lower surface and an upper surface, forming at least one first solar cell layer on the first substrate to obtain a first wafer structure, forming at least one second solar cell layer on the upper surface of the second substrate to obtain a second wafer structure, and bonding the first wafer structure to the second wafer structure, wherein the at least one first solar cell layer is bonded to the lower surface of the second substrate and removing the first substrate.
    Type: Application
    Filed: March 13, 2013
    Publication date: January 29, 2015
    Applicant: SOITEC
    Inventors: Bruno Ghyselen, Chantal Arena, Frank Dimroth, Andreas W. Bett
  • Publication number: 20140366927
    Abstract: Provided is an energy harvesting device, including a solar cell including at least one active layer for receiving a first range of electromagnetic frequencies, at least one layer including antenna structures for receiving RF energy and formed on a first side of the solar cell, and at least one semiconductor for absorbing IR energy, and formed on a second side of the solar cell opposite the first side.
    Type: Application
    Filed: January 23, 2013
    Publication date: December 18, 2014
    Inventors: Olga A. Lavrova, Christos G. Christodoulou, Sang M. Han, Ganesh Balakrishnan
  • Patent number: 8895342
    Abstract: Inverted metamorphic multijunction solar cells having a heterojunction middle subcell and a graded interlayer, and methods of making same, are disclosed herein. The present disclosure provides a method of manufacturing a solar cell using an MOCVD process, wherein the graded interlayer is composed of (InxGa1-x)yAl1-yAs, and is formed in the MOCVD reactor so that it is compositionally graded to lattice match the middle second subcell on one side and the lower third subcell on the other side, with the values for x and y computed and the composition of the graded interlayer determined so that as the layer is grown in the MOCVD reactor, the band gap of the graded interlayer remains constant at 1.5 eV throughout the thickness of the graded interlayer.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: November 25, 2014
    Assignee: Emcore Solar Power, Inc.
    Inventors: Mark A. Stan, Arthur Cornfeld
  • Publication number: 20140342494
    Abstract: A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; and forming a contact composed of a sequence of layers over the first subcell at a temperature of 280° C. or less and having a contact resistance of less than 5×10?4 ohms-cm2.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 20, 2014
    Applicant: Emcore Solar Power, Inc.
    Inventors: Tansen Varghese, Arthur Cornfeld
  • Patent number: 8890128
    Abstract: The present invention provides an organic display device, comprising: an organic solar module for obtaining solar energy and converting the obtained solar energy into electric power, and an ultraviolet organic light emitting module driven to emit ultraviolet light by the electric power obtained from the organic solar module. The present invention can fully use solar energy and carry out ultraviolet display by combining the ultraviolet organic light emitting module with the organic solar module.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: November 18, 2014
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Yawei Liu, Yuan-Chun Wu
  • Patent number: 8872302
    Abstract: Disclosed is an electronic apparatus in which a thermoelectric conversion element and at least one of a photoelectric conversion element and a transistor or a diode are monolithically integrated, or which prevents interference between a p-type thermoelectric conversion unit and an n-type thermoelectric conversion unit. This electronic apparatus includes a thermoelectric conversion element (100) including a semiconductor layer of stacked heterostructure (38) which performs thermoelectric conversion using Seebeck effect and at least one of a photoelectric conversion element (102) in which at least a portion of the semiconductor layer of stacked heterostructure (38) performs photoelectric conversion and a transistor (104) or a diode having at least a portion of the semiconductor layer of stacked heterostructure (38) as an operating layer.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: October 28, 2014
    Assignees: Eyeviewtech Co., Ltd., 3D-Bio Co., Ltd.
    Inventor: Masayuki Abe
  • Patent number: 8871533
    Abstract: A solar cell making method includes steps of making a round P-N junction preform by (a) stacking a P-type silicon layer and a N-type silicon layer on top of each other, and (b) forming a P-N junction near an interface between the P-type silicon layer and the N-type silicon layer, wherein the round P-N junction preform defines a first surface and a second surface; forming a first electrode preform on the first surface and forming a second electrode preform on the second surface, thereby forming a round solar cell preform; and forming a photoreceptive surface with the P-N junction exposed on the photoreceptive surface by cutting the round solar cell preform into a plurality of arc shaped solar cells, the photoreceptive surface being on a curved surface of the arc shaped solar cell and being configured to receive incident light beams.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: October 28, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 8859321
    Abstract: Fabrication of a tandem photovoltaic device includes forming a bottom cell having an N-type layer, a P-type layer and a bottom intrinsic layer therebetween. A top cell is formed relative to the bottom cell. The top cell has an N-type layer, a P-type layer and a top intrinsic layer therebetween. The top intrinsic layer is formed of an undoped material deposited at a temperature that is different from the bottom intrinsic layer such that band gap energies for the top intrinsic layer and the bottom intrinsic layer are progressively lower for each cell.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ahmed Abou-Kandil, Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Patent number: 8832344
    Abstract: [Problem] A baseboard and extension modules can be connected without the use of lead lines connected between the baseboard and extension module. [Solution] A baseboard includes first connectors; an extension module includes a second connector that fits with the first connectors; the first connectors and the second connector include ground terminals, source terminals, and signal terminals connected to signal lines; each of the ground terminal, each of the source terminal, and each of the signal terminals constituting a suit of terminals, a plurality of the suit constituting the first connectors; the ground terminals, the source terminals, and the signal terminals disposed at a constant pitch on the baseboard; the second connector including a suit of terminals, the suit including a ground terminal, a source terminal, and a signal terminal; and the baseboard and the extension module are directly connected only by the first connector and the second connector.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: September 9, 2014
    Inventor: Kilseong Ha
  • Patent number: 8823159
    Abstract: Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: September 2, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Seng Kim Dalson Ye, Chin Hui Chong, Choon Kuan Lee, Wang Lai Lee, Roslan Bin Said
  • Patent number: 8822817
    Abstract: The disclosure provides for a direct wafer bonding method including providing a bonding layer upon a first and second wafer, and directly bonding the first and second wafers together under heat and pressure. The method may be used for directly bonding an GaAs-based, InP-based, GaP-based, GaSb-based, or Ga(In)N-based device to a GaAs device by introducing a highly doped (Al)(Ga)InP(As)(Sb) layer between the devices. The bonding layer material forms a bond having high bond strength, low electrical resistance, and high optical transmittance.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: September 2, 2014
    Assignee: The Boeing Company
    Inventors: Dhananjay M. Bhusari, Daniel C. Law
  • Patent number: 8816461
    Abstract: A dichromatic photodiode and method for dichromatic photodetection are disclosed. A wide bandgap junction comprises a lattice matched junction operable to detect a first light spectrum. A narrow bandgap junction is coupled to the wide bandgap junction, and comprises a photodiode structure. The narrow bandgap junction is operable to detect a second light spectrum.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: August 26, 2014
    Assignee: The Boeing Company
    Inventors: Ping Yuan, Xiaogang Bai, Rengarajan Sudharsanan
  • Patent number: 8802485
    Abstract: In the frame of manufacturing a photovoltaic cell a layer (3) of silicon compound is deposited on a structure (1). The yet uncovered surface (3a) is treated in a predetermined oxygen (O2) containing atmosphere which additionally contains a dopant (D). Thereby, the silicon compound layer is oxidized and doped in a thin surface area (5).
    Type: Grant
    Filed: September 7, 2009
    Date of Patent: August 12, 2014
    Assignee: Tel Solar AG
    Inventors: Johannes Meier, Markus Bronner, Markus Kupich, Tobias Roschek, Hanno Goldbach
  • Patent number: 8802483
    Abstract: A method of forming a self-organized nanostructured solar cell is provided. The method includes depositing a semiconductor film on a substrate, where the semiconductor film includes a mixture of at least two constituents, then activating the semiconductor film during or after the deposition. Here, the activated semiconductor film self-assembles into an organized nanostructure geometry on the substrate, where the organized nanostructure includes a first structure of the at least one constituent having a first polarity and a second structure of the at least one constituent having a second polarity opposite to the first polarity. Further, the invention includes depositing a contact on a top surface of the organized nanostructure geometry.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: August 12, 2014
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Stacey F. Bent, Bruce M. Clemens
  • Publication number: 20140209149
    Abstract: Voltage-matched thin film multijunction solar cell and methods of producing cells having upper CdTe pn junction layers formed on a transparent substrate which in the completed device is operatively positioned in a superstate configuration. The solar cell also includes a lower pn junction formed independently of the CdTe pn junction and an insulating layer between CdTe and lower pn junctions. The voltage-matched thin film multijunction solar cells further include a parallel connection between the CdTe pn junction and lower pn junctions to form a two-terminal photonic device. Methods of fabricating devices from independently produced upper CdTe junction layers and lower junction layers are also disclosed.
    Type: Application
    Filed: April 2, 2014
    Publication date: July 31, 2014
    Applicant: Alliance for Sustainable Energy, LLC
    Inventors: Angelo MASCARENHAS, Kirstin ALBERI
  • Patent number: 8778778
    Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Masahiro Sekiguchi, Masayuki Dohi, Tsuyoshi Matsumura, Hideo Numata, Mari Otsuka, Naoko Yamaguchi, Takashi Shirono, Satoshi Hongo
  • Patent number: 8749056
    Abstract: A module and a method for manufacturing a module are disclosed. An embodiment of a module includes a first semiconductor device, a frame arranged on the first semiconductor device, the frame including a cavity, and a second semiconductor device arranged on the frame wherein the second semiconductor device seals the cavity.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: June 10, 2014
    Assignee: Infineon Technologies AG
    Inventors: Daniel Kehrer, Stefan Martens, Tze Yang Hin, Helmut Wietschorke, Horst Theuss, Beng Keh See, Ulrich Krumbein
  • Patent number: 8748957
    Abstract: A coherent spin field effect transistor is provided by depositing a ferromagnetic base like cobalt on a substrate. A magnetic oxide layer is formed on the cobalt by annealing at temperatures on the order of 1000° K to provide a few monolayer thick layer. Where the gate is cobalt, the resulting magnetic oxide is Co3O4(111). Other magnetic materials and oxides may be employed. A few ML field of graphene is deposited on the cobalt (III) oxide by molecular beam epitaxy, and a source and drain are deposited of base material. The resulting device is scalable, provides high on/off rates, is stable and operable at room temperature and easily fabricated with existing technology.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: June 10, 2014
    Assignee: Quantum Devices, LLC
    Inventors: Jeffry Kelber, Peter Dowben
  • Patent number: 8735715
    Abstract: Disclosed is a photovoltaic device that comprises: a first electrode including a transparent conductive oxide layer; a first unit cell being placed on the first electrode; a second unit cell being placed on the first unit cell; and a second electrode being placed on the second unit cell, wherein the intrinsic semiconductor layer of the first unit cell includes hydrogenated amorphous silicon or hydrogenated amorphous silicon based material, wherein an intrinsic semiconductor layer of the second unit cell includes hydrogenated microcrystalline silicon or hydrogenated microcrystalline silicon based material, and wherein a ratio of a root mean square roughness to an average pitch of a texturing structure formed on the surface of the first electrode is equal to or more than 0.05 and equal to or less than 0.13.
    Type: Grant
    Filed: January 9, 2011
    Date of Patent: May 27, 2014
    Assignee: Intellectual Discovery Co., Ltd.
    Inventor: Seung-Yeop Myong
  • Publication number: 20140116494
    Abstract: A high-efficiency four-junction solar cell includes: an InP growth substrate; a first subcell formed over the growth substrate, with a first band gap, and a lattice constant matched with that of the growth substrate; a second subcell formed over the first subcell, with a second band gap larger than the first band gap, and a lattice constant matched with that of the growth substrate; a third subcell formed over the second subcell, with a third band gap larger than the second band gap, and a lattice constant matched with that of the substrate lattice; a composition gradient layer formed over the third subcell, with a fourth band gap larger than the third band gap; and a fourth subcell formed over the composition gradient layer, with a fifth band gap larger than the third band gap, and a lattice constant mismatched with that of the substrate.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 1, 2014
    Applicant: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: ZHIHAO WU, GUIJIANG LIN, MINGHUI SONG, YANYAN FANG, JIANGNAN DAI, CHANGQING CHEN, JINZHONG YU, ZHIDONG LIN
  • Patent number: 8703521
    Abstract: A method for fabrication of a multijunction photovoltaic (PV) cell includes providing a stack comprising a plurality of junctions on a substrate, each of the plurality of junctions having a respective bandgap, wherein the plurality of junctions are ordered from the junction having the smallest bandgap being located on the substrate to the junction having the largest bandgap being located on top of the stack; forming a top metal layer, the top metal layer having a tensile stress, on top of the junction having the largest bandgap; adhering a top flexible substrate to the metal layer; and spalling a semiconductor layer from the substrate at a fracture in the substrate, wherein the fracture is formed in response to the tensile stress in the top metal layer.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: April 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Norma Sosa Cortes, Keith E. Fogel, Devendra Sadana, Davood Shahrjerdi
  • Patent number: 8704083
    Abstract: In a thin film photoelectric conversion deice fabricated by addition of a catalyst element with the use of a solid phase growth method, defects such as a short circuit or leakage of current are suppressed. A catalyst material which promotes crystallization of silicon is selectively added to a second silicon semiconductor layer formed over a first silicon semiconductor layer having one conductivity type, the second silicon semiconductor layer is partly crystallized by a heat treatment, a third silicon semiconductor layer having a conductivity type opposite to the one conductivity type is stacked, and element isolation is performed at a region in the second silicon semiconductor layer to which a catalyst material is not added, so that a left catalyst material is prevented from being diffused again, and defects such as a short circuit or leakage of current are suppressed.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: April 22, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kazuo Nishi
  • Publication number: 20140102522
    Abstract: The invention relates to a method for manufacturing a thin film solar cell, comprising the sequential steps of a) depositing a positively doped Si layer (3), b1) depositing a first intrinsic a-Si:H layer (21) at a first deposition rate, b2) depositing a second intrinsic a-Si:H layer (22) at a second deposition rate, and c) depositing a negatively doped Si layer (5), whereby the second deposition rate is greater than the first deposition rate. The thin film solar cell manufactured is characterized by an increased initial and stabilized efficiency while at the same time the overall deposition rate, even by depositing two different intrinsic layers (21, 22), is kept at a reasonable and economic level.
    Type: Application
    Filed: November 14, 2011
    Publication date: April 17, 2014
    Applicant: TEL SOLAR AG
    Inventors: Marian Fecioru-Morariu, Bogdan Mereu
  • Patent number: 8697481
    Abstract: Multijunction solar cells having at least four subcells are disclosed, in which at least one of the subcells comprises a base layer formed of an alloy of one or more elements from group III on the periodic table, nitrogen, arsenic, and at least one element selected from the group consisting of Sb and Bi, and each of the subcells is substantially lattice matched. Methods of manufacturing solar cells and photovoltaic systems comprising at least one of the multijunction solar cells are also disclosed.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: April 15, 2014
    Assignee: Solar Junction Corporation
    Inventors: Rebecca Elizabeth Jones-Albertus, Pranob Misra, Michael J. Sheldon, Homan B. Yuen, Ting Liu, Daniel Derkacs, Vijit Sabnis, Micahel West Wiemer, Ferran Suarez
  • Patent number: 8697495
    Abstract: The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: April 15, 2014
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Shanggar Periaman, Kooi Chi Ooi, Yen Hsiang Chew
  • Publication number: 20140093995
    Abstract: A method of hybrid stacked Chip for a solar cell onto which semiconductor layers of different materials is provided by stacking tunnel layer and bumps in order to solve the problem of lattices mismatch between the layers for further increasing of the efficiency of solar cell. Electric charges (i.e., current) generated by respective solar cells can be outputted by means of contacts. Further total power P is defined by a summation of powers of respective solar cells, i.e., V1I1+V2I2+ . . . VnIn. This is a great increase in comparison with the power of conventional solar cells connected in series.
    Type: Application
    Filed: November 26, 2013
    Publication date: April 3, 2014
    Applicant: Chang Gung University
    Inventors: Liann-Be Chang, Yu-Lin Lee
  • Publication number: 20140090700
    Abstract: A high-concentration multi-junction solar cell and method for fabricating same is provided. The high-concentration multi-junction solar cell comprises a top cell, an intermediate cell, a bottom cell and two tunneling junctions connecting the top cell and intermediate cell and the intermediate cell and bottom cell. The emitter layers of the top and intermediate cells both employ the graded doping concentrations and have high open circuit voltage and short circuit current. The top cell emitter layer is over several hundred nanometers thicker than that of the traditional multi-junction cell so as to decrease the whole series resistance of the multi-junction cell, improve the fill factor, and gain higher photoelectric conversion efficiency.
    Type: Application
    Filed: May 7, 2012
    Publication date: April 3, 2014
    Applicant: Xiamen Sanan Optoelectroics Technology Co., Ltd.
    Inventors: Minghui Song, Guijiang Lin, Zhihao Wu, Liangjun Wang, Jianqing Liu, Jingfeng Bi, Weiping Xiong, Zhidong Lin
  • Patent number: 8670055
    Abstract: An image pickup lens is provided that includes a substrate; resin layers formed on both respective opposite surfaces of the substrate; a lens portion formed on at least any one of the surfaces of the substrate; and a spacer formed on at least any one of the surfaces of the substrate at an area surrounding the lens portion.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: March 11, 2014
    Assignee: Sony Corporation
    Inventor: Kazuya Tsujino
  • Patent number: 8669135
    Abstract: A system and method for fabricating a 3D image sensor structure is disclosed. The method comprises providing an image sensor with a backside illuminated photosensitive region on a substrate, applying a first dielectric layer to the first side of the substrate opposite the substrate side where image data is gathered, and applying a semiconductor layer that is optionally polysilicon, to the first dielectric layer. A least one control transistor may be created on the first dielectric layer, within the semiconductor layer and may optionally be a row select, reset or source follower transistor. An intermetal dielectric may be applied over the first dielectric layer; and may have at least one metal interconnect disposed therein. A second interlevel dielectric layer may be disposed on the control transistors. The dielectric layers and semiconductor layer may be applied by bonding a wafer to the substrate or via deposition.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: March 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang
  • Publication number: 20140048122
    Abstract: A photovoltaic device that includes an upper cell that absorbs a first range of wavelengths of light and a bottom cell that absorbs a second range of wavelengths of light. The bottom cell includes a heterojunction comprising a crystalline germanium containing (Ge) layer. At least one surface of the crystalline germanium (Ge) containing layer is in contact with a silicon (Si) containing layer having a larger band gap than the crystalline (Ge) containing layer.
    Type: Application
    Filed: August 15, 2012
    Publication date: February 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith E. Fogel, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8652856
    Abstract: Disclosed herein is a method of forming electronic device having thin-film components by using trenches. One or more of thin-film components is formed by depositing a thin-film in the trench followed by processing the deposited thin-film to have the desired thickness.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: February 18, 2014
    Assignee: Crocus Technology Inc.
    Inventors: Jean Pierre Nozieres, Jason Reid
  • Patent number: 8642361
    Abstract: A method for large scale manufacture of photovoltaic devices includes loading a substrate into a load lock station and transferring the substrate in a controlled ambient to a first process station. The method includes using a first physical deposition process in the first process station to cause formation of a first conductor layer overlying the surface region of the substrate. The method includes transferring the substrate to a second process station, and using a second physical deposition process in the second process station to cause formation of a second layer overlying the surface region of the substrate. The method further includes repeating the transferring and processing until all thin film materials of the photovoltaic devices are formed. In an embodiment, the invention also provides a method for large scale manufacture of photovoltaic devices including feed forward control.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: February 4, 2014
    Assignee: Stion Corporation
    Inventors: Howard W. H. Lee, Chester A. Farris, III