Abstract: The invention is a novel manufacturing method for making multi-junction solar cell circuits that addresses current problems associated with such circuits by allowing the formation of integral diodes in the cells and allows for a large number of circuits to readily be placed on a single silicon wafer substrate. The standard Ge wafer used as the base for multi-junction solar cells is replaced with a thinner layer of Ge or a II-V semiconductor material on a silicon/silicon dioxide substrate. This allows high-voltage cells with multiple multi-junction circuits to be manufactured on a single wafer, resulting in less array assembly mass and simplified power management.

Abstract: A solar cell array including a first solar cell with an integral bypass diode and an adjacent second solar cell and two discrete metal interconnection members coupling the anode of the bypass diode of the first cell with the anode of the second solar cell.

Abstract: A photosensitive device (100), the photosensitive device (100) comprising a substrate (101) and a plurality of vertically aligned nanowire diodes (102 to 105) provided on and/or in the substrate (101).

Abstract: A multijunction solar cell including an upper first solar subcell having a first band gap; a second solar subcell adjacent to the first solar subcell and having a second band gap smaller than the first band gap; a first graded interlayer adjacent to the second solar subcell; the first graded interlayer having a third band gap greater than the second band gap; and a third solar subcell adjacent to the first graded interlayer, the third subcell having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell. A second graded interlayer is provided adjacent to the third solar subcell; the second graded interlayer having a fifth band gap greater than the fourth band gap; and a lower fourth solar subcell is provided adjacent to the second graded interlayer, the lower fourth subcell having a sixth band gap smaller than the fourth band gap such that the fourth subcell is lattice mismatched with respect to the third subcell.

Abstract: A high-amplitude magnetic angle sensor is described along with a process for its manufacture. A thin tantalum nitride hard mask, used to pattern the device, is left in place within the completed structure but, by first converting most of it to tantalum oxide, its effect on current shunting is greatly reduced.

Abstract: Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line patte

Abstract: The present invention provides a method for manufacturing a multi-junction solar cell which makes it possible to implement a 4-junction solar cell and to increase the area of a device. A nucleus generation site is disposed on a substrate 2 made of a first semiconductor. A first material gas is fed to the nucleus generation site to form a wire-like semiconductor 3 in the nucleus generation site. A third material gas and a fourth material gas are fed to form a wire-like semiconductor 4 on the semiconductor 3 and a wire-like semiconductor 5 on the semiconductor 4. A nucleus generation site is disposed on a substrate 6. The first material gas is fed to the nucleus generation site to form a wire-like semiconductor 2a in the nucleus generation site. A second material gas to the fourth material gas are fed to form the wire-like semiconductor 3 on the semiconductor 2a, the wire-like semiconductor 4 on the semiconductor 3, and the wire-like semiconductor 5 on the semiconductor 4.

Abstract: A method of forming a multijunction solar cell includes providing a substrate, forming a first subcell by depositing a nucleation layer over the substrate and a buffer layer including gallium arsenide (GaAs) over the nucleation layer, forming a middle second subcell having a heterojunction base and emitter disposed over the first subcell and forming first and second tunnel junction layers between the first and second subcells. The first tunnel junction layer includes GaAs over the first subcell and the second tunnel junction layer includes aluminum gallium arsenide (AlGaAs) over the first tunnel junction layer. The method further includes forming a third subcell having a homojunction base and emitter disposed over the middle subcell.

Abstract: Embodiments relate to an image sensor and a method for manufacturing an image sensor that may prevent a photoresist pattern from remaining on gates by forming a floating diffusion area faster than the gates. According to embodiments, since the gates may not be influenced by an ion implantation process, current characteristics and operation reliability may be enhanced. According to embodiments, the method may include forming dummy ion implantation mask patterns for forming a floating diffusion area over an epitaxial layer and forming an ion implantation mask pattern over the epitaxial layer and at least a portion of the dummy ion implantation mask patterns, so as to form the floating diffusion area by performing an ion implantation process.

Abstract: In one or more embodiments of a photovoltaic device and a method of manufacturing the photovoltaic device, a first conductive layer, a first light-absorbing layer and a second conductive layer may be formed on a substrate, in sequence. A temperature for forming the second conductive layer may be lower than a temperature for forming the first conductive layer and a temperature for forming the first light-absorbing layer.

Abstract: An optoelectronic component that includes a semiconductor device and an optical component is disclosed. The semiconductor device includes at least one radiation-sensitive zone configured to detect electromagnetic radiation. The optical element for focusing is configured to focus the electromagnetic radiation in the at least one radiation-sensitive zone. The optical element includes a diffractive element having structures on the order of magnitude of the wavelength of the electromagnetic radiation.

Abstract: A Complementary Metal Oxide Semiconductor (CMOS) image sensor includes a red photodiode formed in an first epitaxial layer, an isolation layer formed with a contact region left in a partial area of the red photodiode, a green photodiode formed in a surface of the isolation layer, a contact formed in the contact region at a predetermined spatial distance from the green photodiode, a second epitaxial layer formed on the first epitaxial layer in which the green photodiode is formed, a plurality of plugs formed in the second epitaxial layer and electrically connected to the green photodiode and the contact, a device isolation film formed in a surface of the second epitaxial layer, a blue photodiode formed in a surface of the second epitaxial layer above the green photodiode, and a well region formed in the second epitaxial layer inside the plug.

Abstract: To provide a stacked photoelectric conversion device and a method for producing the same, in which an interlayer is provided between photoelectric conversion layers to obtain an effect of controlling the amount of incidence light, and carrier recombination at an interface between the interlayer and a semiconductor layer is decreased to enhance photoelectric conversion efficiency. The stacked photoelectric conversion device of the present invention comprises a plurality of silicon-based photoelectric conversion layers having a p-i-n structure stacked, wherein at least a pair of adjacent photoelectric conversion layers have an interlayer of a silicon nitride therebetween, the pair of the photoelectric conversion layers are electrically connected with each other, and a p-type silicon-based semiconductor layer constituting a part of the photoelectric conversion layer and contacting the interlayer contains a nitrogen atom.

Abstract: A method and apparatus for forming solar cells is provided. Doped crystalline semiconductor alloys including carbon, oxygen, and nitrogen are used as charge collection layers for thin-film solar cells. The semiconductor alloy layers are formed by providing semiconductor source compound and a co-component source compound to a processing chamber and ionizing the gases to deposit a layer on a substrate. The alloy layers provide improved control of refractive index, wide optical bandgap, high conductivity, and resistance to attack by oxygen.

Abstract: An image sensor contains a semiconductor substrate, a plurality of pixels defined on the semiconductor substrate, a photo conductive layer and a transparent conductive layer formed on the pixel electrodes of the pixels in order, and a shield device positioned between any two adjacent pixel electrodes. The shield device has a shield electrode and an isolation structure surrounding the shield electrode so that the shield electrode is isolated from the pixel electrodes and the photo conductive layer by the isolation structure.

Abstract: An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, with a corresponding fabrication process. The color imager cell array is formed from a bulk silicon (Si) substrate without an overlying epitaxial Si layer. A plurality of color imager cells are formed in the bulk Si substrate, where each color imager cell includes a photodiode set and a U-shaped well liner. The photodiode set includes first, second, and third photodiode formed as a stacked multi-junction structure, while the U-shaped well liner fully isolates the photodiode set from adjacent photodiode sets in the array. The U-shaped well liner includes a physically interfacing doped well liner bottom and first wall. The well liner bottom is interposed between the substrate and the photodiode set, and the first wall physically interfaces each doped layer of each photodiode in the photodiode set.

Abstract: A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; and forming a contact layer over the third subcell having a fifth band gap greater than at least the magnitude of the second band gap.

Abstract: A method for obtaining an optimal reflectivity value for complex multilayer stacks is disclosed. Aspects of the present invention include generating a model of a multilayer stack and parameterizing each layer by a thickness and an index of refraction; allowing a user to input values for the parameters; calculating an extrema for a cost function of reflectivity R using the input parameter values; calculating sensitivity values S for the extrema points; and obtaining an optimal value by calculating a cost function R+S.

Abstract: More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region on between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.

Abstract: A tandem thin-film silicon solar cell comprises a transparent substrate, a first unit cell positioned on the transparent substrate, the first unit cell comprising a p-type window layer, an i-type absorber layer and an n-type layer, an intermediate reflection layer positioned on the first unit cell, the intermediate reflection layer including a hydrogenated n-type microcrystalline silicon oxide of which the oxygen concentration is profiled to be gradually increased and a second unit cell positioned on the intermediate reflection layer, the second unit cell comprising a p-type window layer, an i-type absorber layer and an n-type layer.

Abstract: There is provided a method for producing a multijunction solar cell having four-junctions, the method allowing the area of a device to be increased. On a nucleation site formed on a substrate 2, is grown a semiconductor 2a comprising the same material as the substrate 2 in the shape of a wire. On the semiconductor 2a, are successively grown semiconductors 3, 4, 5, and 6 with a narrower band gap in the shape of a wire. The semiconductor 3 may be directly grown in the shape of a wire on the nucleation site formed on the substrate 2. It is preferred to form the nucleation site by forming an amorphous SiO2 coating 8a on the substrate 2 and etching a part of the amorphous SiO2 coating 8a. Further, it is preferred to form an insulating film 8 in the region except the nucleation sites on the substrate 2 by allowing the amorphous SiO2 coating 8a to remain therein. The semiconductor 2a is GaP; the semiconductor 3 is Al0.3Ga0.7As; the semiconductor 4 is GaAs; the semiconductor 5 is In0.3Ga0.

Abstract: The purpose is manufacturing a photoelectric conversion device with excellent photoelectric conversion characteristics typified by a solar cell with effective use of a silicon material. A single crystal silicon layer is irradiated with a laser beam through an optical modulator to form an uneven structure on a surface thereof. The single crystal silicon layer is obtained in the following manner; an embrittlement layer is formed in a single crystal silicon substrate; one surface of a supporting substrate and one surface of an insulating layer formed over the single crystal silicon substrate are disposed to be in contact and bonded; heat treatment is performed; and the single crystal silicon layer is formed over the supporting substrate by separating part of the single crystal silicon substrate fixed to the supporting substrate along the embrittlement layer or a periphery of the embrittlement layer.

Abstract: A cubic element of photonic crystal is integrally formed on the surface of a photo-detection element, and a portion of the photonic crystal cubic element is irradiated with ultraviolet rays thereby to change the refractive index of the portion of the cubic element that has been irradiated with ultraviolet rays. Alternatively, by causing globular particles having different refractive indices to eject on the surface of the photo-detection element from an ink-jet apparatus having a nozzle provided with a temperature control part by controlling temperature of the nozzle to form a laminate of globular particle layers having different refractive indices, a photonic crystal lens is integrally formed on the surface of the photo-detection element.

Abstract: More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.

Abstract: In the solar cell element 2, the second semiconductor layer 24 includes the first extension part 241 which is extended toward and in contact with the first semiconductor layer 22. The extension part 241 is provided along the element separation groove 6 and the power generation region separation groove 7.

Abstract: A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell, including providing first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a grading interlayer over the second subcell, the grading interlayer having a third band gap greater than the second band gap; and forming a third solar subcell over the grading interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mis-matched with respect to the second subcell, wherein at least one of the bases of a solar subcell has an exponentially doped profile.

Abstract: A method for manufacturing structures of a CMOS image sensor. The method comprises the steps of depositing a gate insulating layer and a conductive layer on a semiconductor substrate; depositing an ion implantation barrier layer on the conductive layer; patterning the deposited gate insulating layer, conductive layer and ion implantation barrier layer to form a patterned, composite gate insulating layer, gate electrode and ion implantation barrier structure; forming a second photosensitive layer pattern to define a photodiode region; and implanting low-concentration dopant ions into the substrate using the second photosensitive layer pattern as an ion implantation mask to form a low-concentration dopant region within the photodiode region.

Abstract: A method for forming an optical sensor. First, a structure which comprises a semiconductor substrate is provided. Then, a first electrode and a fourth electrode are formed at a first depth in the semiconductor substrate. Then, a second electrode and a fifth electrode are formed at a second depth in the semiconductor substrate. Then, a third electrode and a sixth electrode are formed at a third depth in the semiconductor substrate. The first depth is greater than the second depth which is greater than the third depth. First, second, and third semiconducting regions of the semiconductor substrate are disposed between and in direct physical contact with the first and fourth electrodes, the second and fifth electrodes, and the third and sixth electrodes, respectively. The first, second, and third semi-conducting regions are in direct physical contact with one another.

Abstract: This embodiment addresses a novel Chip-to-wafer chip lamination technique that provides low cost and high throughput. In the Chip-to-Chip process, using the temperature rise and utilizing deformation caused by thermal expansion of a metal shim inserted between the inner wall of a cavity, in which multiple chips are laminated and accommodated, multiple chips in the cavity are pressed against a reference surface on a side wall of the cavity to automatically perform positioning.

Abstract: An image sensor is disclosed where individual photo diodes of the respective unit cells separated by an element isolating layer are physically integrated into a single large scale pixel formed widely on a semiconductor substrate so as to hold the pixels in common. A pixel separation pattern is additionally formed on a portion of the large scale photo diode formed so as to electrically separate them. An optimization of the light receiving area of the photo diode, a minimization of the intrusion area of an element isolating layer, and so on are achieved, so that the photo diode recovers an area occupied by an intrusion of the element isolating layer, thus maximizing the light receiving area in an optimal scale and easily preventing electrical impacts between the respective unit cells.

Abstract: A complementary metal oxide semiconductor (CMOS) device with a three dimensional integration structure and a method for fabricating the same are provided. An image sensor includes a first substrate in which a photo detection device is formed; a second substrate in which a peripheral circuit is formed, wherein the first substrate and the second substrate are bonded through a plurality of bonding pads formed on both the first substrate and the second substrate, and a back side of the first substrate is turned upside down; and a microlens formed on a top portion of the back side of the first substrate.

Abstract: A thermal emitter device includes a cavity structure that comprises an active medium for allowing thermal emissions to occur. A photonic crystal structure is positioned on one side of the cavity structure. The photonic crystal structure comprises alternating layers of high index and low index materials and acts as a first mirror for the cavity structure. A highly reflective mirror structure is positioned on another side of the cavity structure and acting as both the high-temperature source of radiation and a second mirror for the cavity structure.

Abstract: A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface leakage and dark current and increases the capacitance of the photodiode by acting as a reflective barrier to photo-generated charge in the doped region of the second conductivity type of the photodiode. The deep implanted region also provides improved charge transfer from the charge collection region of the photodiode to a floating diffusion region adjacent the gate of the transfer transistor.

Abstract: Provided is a multi-well CMOS image sensor and a method of fabricating the same. The multi-well CMOS image sensor may include a plurality of photodiodes vertically formed in a region of a substrate, an n+ wall that vertically connects an outer circumference of the photodiodes, and a floating diffusion region that is connected to the photodiodes on a side of the n+ wall to receive charges from the photodiodes, wherein a p-type region is formed between the floating diffusion region and the n+ wall, and the plurality of photodiodes have a multi-potential well structure.

Abstract: A fabricating method of a CMOS image sensor is disclosed, by which a light condensing effect is enhanced by providing an inner microlens to a semiconductor substrate. The CMOS image sensor includes a plurality of photodiodes on a semiconductor substrate, a plurality of inner microlenses on a plurality of the photodiodes, an insulating interlayer on a plurality of the inner microlenses, a plurality of metal lines within the insulating interlayer, a device protecting layer on the insulating interlayer, and a plurality of microlenses on the device protecting layer.

Abstract: The present invention is directed to systems and methods for protecting a solar cell. The solar cell includes first solar cell portion. The first solar cell portion includes at least one junction and at least one solar cell contact on a backside of the first solar cell portion. At least one bypass diode portion is epitaxially grown on the first solar cell portion. The bypass diode has at least one contact. An interconnect couples the solar cell contact to the diode contact.

Abstract: The present invention, in one aspect, relates to a solar cell. In one embodiment, the solar cell includes an anode; an active organic layer comprising an electron-donating organic material and an electron-accepting organic material; a semiconducting layer formed between the anode and the active organic layer; and an electron-blocking layer (EBL) formed between the semiconducting layer and the active organic layer, where the EBL is transparent and adapted for blocking electron leakage from the active organic layer to the anode while transporting holes from the active organic layer to the anode.

Abstract: A method for making a multiple-wavelength opto-electronic device which may include providing a substrates and forming a plurality of active optical devices to be carried by the substrate and operating at different respective wavelengths. Moreover, each optical device may include a superlattice comprising a plurality of stacked groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: An image sensor including a first epitaxial layer having a first photodiode, a second epitaxial layer formed on and/or over the first epitaxial layer, the second epitaxial layer having a second photodiode and a first plug, and a third epitaxial layer formed on and/or over the second epitaxial layer, the third epitaxial layer having a third photodiode, a second plug and an isolation layer.

Abstract: A method for forming an optical sensor. First, a structure which comprises a semiconductor substrate is provided. Then, a first electrode and a fourth electrode are formed at a first depth in the semiconductor substrate. Then, a second electrode and a fifth electrode are formed at a second depth in the semiconductor substrate. Then, a third electrode and a sixth electrode are formed at a third depth in the semiconductor substrate. The first depth is greater than the second depth which is greater than the third depth. First, second, and third semiconducting regions of the semiconductor substrate are disposed between and in direct physical contact with the first and fourth electrodes, the second and fifth electrodes, and the third and sixth electrodes, respectively. The first, second, and third semi-conducting regions are in direct physical contact with one another.

Abstract: An image sensor including a first epitaxial layer formed over a semiconductor substrate; first photodiodes formed spaced apart in the first epitaxial layer; a first isolation region electrically isolating the first photodiodes from each other; a second epitaxial layer formed over the first epitaxial layer; second photodiodes formed spaced apart in the second epitaxial layer; and a second isolation region electrically isolating the second photodiodes from each other.

Abstract: Embodiments relate to an image sensor and a method for manufacturing an image sensor that may prevent a photoresist pattern from remaining on gates by forming a floating diffusion area faster than the gates. According to embodiments, since the gates may not be influenced by an ion implantation process, current characteristics and operation reliability may be enhanced. According to embodiments, the method may include forming dummy ion implantation mask patterns for forming a floating diffusion area over an epitaxial layer and forming an ion implantation mask pattern over the epitaxial layer and at least a portion of the dummy ion implantation mask patterns, so as to form the floating diffusion area by performing an ion implantation process.

Abstract: A Complementary Metal Oxide Semiconductor (CMOS) image sensor includes a red photodiode formed in an first epitaxial layer, an isolation layer formed with a contact region left in a partial area of the red photodiode, a green photodiode formed in a surface of the isolation layer, a contact formed in the contact region at a predetermined spatial distance from the green photodiode, a second epitaxial layer formed on the first epitaxial layer in which the green photodiode is formed, a plurality of plugs formed in the second epitaxial layer and electrically connected to the green photodiode and the contact, a device isolation film formed in a surface of the second epitaxial layer, a blue photodiode formed in a surface of the second epitaxial layer above the green photodiode, and a well region formed in the second epitaxial layer inside the plug.

Abstract: A semiconductor structure has an active region on a substrate, and recessed portions are formed at lower edges of lateral portions of the semiconductor structure. Patterned first insulation layers for device isolation are buried into the recessed portions. Second insulation layers for device isolation are formed on sidewalls of the first insulation layers.

Abstract: An image sensor with a vertically integrated thin-film photodiode includes a bottom doped layer of a PIN photodiode imbedded in a dielectric layer, wherein a bottom surface of the bottom doped layer completely contacts its corresponding underlying pixel electrode. The bottom doped layers of the PIN photodiodes are formed by a self-aligned and damascene method, therefore the pixel electrodes are not exposed to the I-type amorphous silicon layer of the PIN photodiodes. Moreover, the transparent electrode connects the PIN photodiodes to an external ground voltage power through a ground pad which is a portion of a top metal layer.

Abstract: A method of manufacturing a tandem-type thin film photoelectric conversion device includes the steps of forming at least one photoelectric conversion unit (3) on a substrate (1) in a deposition apparatus, taking out the substrate (1) having the photoelectric conversion unit (3) from the deposition apparatus to the air, introducing the substrate (1) into a deposition apparatus and carrying out plasma exposure processing on the substrate (1) in an atmosphere of a gas mixture containing an impurity for determining the conductivity type of the same conductivity type as that of the uppermost conductivity type layer (33) and hydrogen, forming a conductivity type intermediate layer (5) by additionally supplying semiconductor raw gas to the deposition apparatus, and then forming a subsequent photoelectric conversion unit (4).

Abstract: A thin film transistor array substrate structure includes a plurality of data lines; a plurality of gate lines intersecting the data lines to define pixel areas, the gate line being adjacent to at least two pixel areas; a plurality of common lines disposed between the at least two pixel areas; a plurality of thin film transistors formed at each intersection between the gate lines and the data lines; a plurality of common electrodes provided substantially parallel to the common lines; and a plurality of pixel electrodes connected to the thin film transistors.

Abstract: A multilayer color-sensing photodetector is fabricated in a semiconductor wafer having a single crystal structure to form a first, second and third layer of single crystal semiconductor material. A dielectric layer is formed that completely surrounds each single crystal region. A blocking layer is applied to prevent ion implantation where not desired. Ions are implanted into a predefined implant area. The semiconductor wafer is heated to create a dielectric layer part way through the single crystal semiconductor region. The second layer of single crystal semiconductor materials is formed by depositing a single crystal or polycrystalline material and annealing it to form a single crystal semiconductor. The deposited semiconductor layer is masked and etched to obtain single crystal regions directly above the previous layer. A blocking layer is applied and an ion implant is performed. After heating, there is left a region of single crystal silicon that has its sides and bottom surrounding by a dielectric border.

Abstract: A thin-film solar cell is provided. The thin-film solar cell comprises an a-SiGe:H (1.6 eV) n-i-p solar cell having a deposition rate of at least ten (10) ?/second for the a-SiGe:H intrinsic layer by hot wire chemical vapor deposition. A method for fabricating a thin film solar cell is also provided. The method comprises depositing a n-i-p layer at a deposition rate of at least ten (10) ?/second for the a-SiGe:H intrinsic layer.