Vertically Arranged (e.g., Tandem, Stacked, Etc.) Patents (Class 438/74)
  • Patent number: 8642361
    Abstract: A method for large scale manufacture of photovoltaic devices includes loading a substrate into a load lock station and transferring the substrate in a controlled ambient to a first process station. The method includes using a first physical deposition process in the first process station to cause formation of a first conductor layer overlying the surface region of the substrate. The method includes transferring the substrate to a second process station, and using a second physical deposition process in the second process station to cause formation of a second layer overlying the surface region of the substrate. The method further includes repeating the transferring and processing until all thin film materials of the photovoltaic devices are formed. In an embodiment, the invention also provides a method for large scale manufacture of photovoltaic devices including feed forward control.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: February 4, 2014
    Assignee: Stion Corporation
    Inventors: Howard W. H. Lee, Chester A. Farris, III
  • Patent number: 8642373
    Abstract: Disclosed is a method for manufacturing a photovoltaic device that includes: providing a substrate having a first electrode formed thereon; forming a first unit cell, the first unit cell including a first conductive silicon layer, an intrinsic silicon layer and a second conductive silicon layer, which are sequentially stacked from the first electrode; exposing to the air either a portion of an intermediate reflector formed on the first unit cell or the second conductive silicon layer of the first unit cell; forming the rest of the intermediate reflector or the entire intermediate reflector on the second conductive silicon layer of the first unit cell in a second manufacturing system; and forming a second unit cell on the intermediate reflector in the second manufacturing system, the second unit cell including a first conductive silicon layer, an intrinsic silicon layer and a second conductive silicon layer, sequentially stacked.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: February 4, 2014
    Assignee: Intellectual Discovery Co., Ltd.
    Inventor: Seung-Yeop Myong
  • Patent number: 8624103
    Abstract: A backside illuminated multi junction solar cell module includes a substrate, multiple multi junction solar cells, and a cell interconnection that provides a series connection between at least two of the multi junction solar cells. The substrate may include a material that is substantially transparent to solar radiation. Each multi junction solar cell includes a first active cell, grown over the substrate, for absorbing a first portion of the solar radiation for conversion into electrical energy and a second active cell, grown over the first active cell, for absorbing a second portion of the solar radiation for conversion into electrical energy. At least one of the first and second active cells includes a nitride.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: January 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jizhong Li
  • Patent number: 8609457
    Abstract: Generally, the present disclosure is directed to a semiconductor device with DRAM bit lines made from the same material as the gate electrodes in non-memory regions of the device, and methods of making the same. One illustrative method disclosed herein comprises forming a semiconductor device including a memory array and a logic region. The method further comprises forming a buried word line in the memory array and, after forming the buried word line, performing a first common process operation to form at least a portion of a conductive gate electrode in the logic region and to form at least a portion of a conductive bit line in the memory array.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: December 17, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Till Schloesser, Frank Jakubowski
  • Patent number: 8609451
    Abstract: Fabrication of a single crystal silicon solar cell with an insitu epitaxially deposited very highly doped p-type silicon back surface field obviates the need for the conventional aluminum screen printing step, thus enabling a thinner silicon solar cell because of no aluminum induced bow in the cell. Furthermore, fabrication of a single crystal silicon solar cell with insitu epitaxial p-n junction formation and very highly doped n-type silicon front surface field completely avoids the conventional dopant diffusion step and one screen printing step, thus enabling a cheaper manufacturing process.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: December 17, 2013
    Assignee: Crystal Solar Inc.
    Inventors: Tirunelveli S. Ravi, Ashish Asthana
  • Patent number: 8609982
    Abstract: A thin film solar cell with a graded bandgap structure comprises a front contact, a first light absorption layer, a transition layer, a second light absorption layer and a back contact. The first light absorption layer is formed on the front contact, the transition layer is formed on the first light absorption layer, the second light absorption layer is formed on the transition layer, and the back contact is formed on the second light absorption layer, wherein the transition layer has a graded bandgap, which is made by alternating a layer of the first superlattice layers, having a first bandgap, with a layer of the second superlattice layers, having a second bandgap, in a tandem arrangement, based on the condition that the thickness of each layer of the first and the second superlattice layers is varied increasing, decreasing or increasing first and then decreasing.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: December 17, 2013
    Assignee: National Chiao Tung University
    Inventor: Chun-Yen Chang
  • Patent number: 8604330
    Abstract: In various embodiments, an array of discrete solar cells with associated devices such as bypass diodes is formed over a single substrate. In one instance, a method of forming a solar-cell array with integrated bypass diodes comprising: providing a semiconductor substrate, a first cell comprising a SiGe p-n junction or SiGe p-i-n junction, one or more second cells each comprising a III-V semiconductor p-n junction or III-V semiconductor p-i-n junction; forming a bypass diode that is discrete and laterally separate from its associated solar cell and comprises an unremoved portion of the first cell, the formation comprising removing an unremoved portion of the one or more second cells thereover.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: December 10, 2013
    Assignee: 4Power, LLC
    Inventors: John J. Hennessy, Andrew C. Malonis, Arthur J. Pitera, Eugene A. Fitzgerald, Steven A. Ringel
  • Patent number: 8598447
    Abstract: Provided is a photoelectric conversion device in which the conductivity after hydrogen-plasma exposure is set within an appropriate range, thereby suppressing the leakage current and improving the conversion efficiency. A photoelectric conversion device includes, on a substrate, a photoelectric conversion layer having at least two power generation cell layers, and an intermediate contact layer provided between the power generation cell layers. The intermediate contact layer mainly contains a compound represented by Zn1-xMgxO (0.096?x?0.183).
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: December 3, 2013
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Kengo Yamaguchi, Satoshi Sakai, Shigenori Tsuruga
  • Patent number: 8592248
    Abstract: The present invention relates to a chemical etching method to electrically isolate the edge from the interior of a thin-film photovoltaic panel comprising a substrate and a photovoltaic laminate. The method comprises a step to dispense an etching paste comprising two or more acids on the laminate periphery; an optional step to apply heat to the laminate; and a step to remove the etching paste. The method is further characterized by the chemical removal of at least two chemically distinctive layers of the laminate at the periphery where the etching paste is applied. The method may be used to produce a thin-film photovoltaic panel.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: November 26, 2013
    Assignee: E I du Pont de Nemours and Company
    Inventors: Lap-Tak Andrew Cheng, Meijun Lu
  • Patent number: 8569098
    Abstract: A method for manufacturing a photoelectric conversion device including a first-conductivity-type crystalline semiconductor region, an intrinsic crystalline semiconductor region, and a second-conductivity-type semiconductor region that are stacked over an electrode is provided for a new anti-reflection structure. An interface between the electrode and the first-conductivity-type crystalline semiconductor region is flat. The intrinsic crystalline semiconductor region includes a crystalline semiconductor region, and a plurality of whiskers that are provided over the crystalline semiconductor region and include a crystalline semiconductor. The first-conductivity-type crystalline semiconductor region and the intrinsic crystalline semiconductor region are formed by a low pressure chemical vapor deposition method at a temperature higher than 550° C. and lower than 650° C.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: October 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8569613
    Abstract: A multi-terminal photovoltaic module includes an upper photovoltaic device which has a first upper electrode, an overlying upper absorber layer, an overlying upper window layer, and a second upper electrode. The upper absorber layer has an upper band gap in a first band gap range. The module also includes a lower photovoltaic device which has a first lower electrode, an overlying lower absorber layer, an overlying lower window layer, and a second lower electrode. The lower absorber layer has a lower band gap in a second band gap range. The module also includes a bonding material coupling the second upper electrode and the first lower electrode. Moreover, the module includes a first upper terminal coupling the first upper electrode and a second upper terminal coupling the second upper electrode. The module further includes a first lower terminal coupling the first lower electrode and a second lower terminal coupling the second lower electrode.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: October 29, 2013
    Assignee: Stion Corporation
    Inventor: Albert S. Brown
  • Patent number: 8563342
    Abstract: A method of making a semiconductor optical integrated device includes the steps of forming, on a substrate, a plurality of semiconductor integrated devices including a first optical semiconductor element having a first bonding pad and a second optical semiconductor element; forming a plurality of bar-shaped semiconductor optical integrated device arrays by cutting the substrate, each of the semiconductor optical integrated device arrays including two or more semiconductor optical integrated devices; alternately arranging the plurality of semiconductor optical integrated device arrays and a plurality of spacers in a thickness direction of the substrate so as to be fixed in place; and forming a coating film on a facet of the semiconductor optical integrated device array. Furthermore, the spacer has a movable portion facing the first bonding pad, the movable portion protruding toward the first bonding pad and being displaceable in a protruding direction.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: October 22, 2013
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: Yoshihiro Yoneda, Hirohiko Kobayashi, Kenji Koyama, Masaki Yanagisawa, Kenji Hiratsuka
  • Publication number: 20130269761
    Abstract: This disclosure relates to photovoltaic and photoelectrosynthetic cells, devices, methods of making and using the same.
    Type: Application
    Filed: April 3, 2013
    Publication date: October 17, 2013
    Inventors: Shane Ardo, Matthew Shaner, Robert Coridan, Nicholas C. Strandwitz, James R. McKone, Katherine Fountaine, Harry A. Atwater, Nathan S. Lewis
  • Publication number: 20130240014
    Abstract: The present invention concerns a vertical electrical connection of photoelectrochemical cells, arranged side-by-side between two opposing substrates, at least one of which is transparent or semi-transparent, and covered, on the side facing towards the other substrate, by an electrically conductive coating divided into a plurality of side-by-side regions electrically isolated by means of a corresponding number of interruptions, said vertical electrical connection being arranged between an electrically isolated region of the electrically conductive coating of a substrate, in electric contact with a photoelectrochemical cell, and the electrically isolated region of the electrically conductive coating of the opposing substrate, in contact with an adjacent photoelectrochemical cell, characterized in that it is made of three overlapping portions, that is two portions, respectively coupled with the conductive coating of each of the two opposing substrates delimiting said photoelectrochemical cells.
    Type: Application
    Filed: April 3, 2013
    Publication date: September 19, 2013
    Inventors: Fabrizio GIORDANO, Eleonora PRETROLATI, Andrea GUIDOBALDI, Thomas BROWN, Richard TOZZI
  • Patent number: 8502065
    Abstract: Disclosed is a photovoltaic device. The photovoltaic device includes: a first electrode and a second electrode; a first unit cell and a second unit cell which are placed between the first electrode and the second electrode and include a first conductive semiconductor layer, an intrinsic semiconductor layer and a second conductive semiconductor layer; and an intermediate reflector which is placed between the first unit cell and the second unit cell, and includes a hydrogenated amorphous carbon layer.
    Type: Grant
    Filed: January 9, 2011
    Date of Patent: August 6, 2013
    Assignee: KISCO
    Inventor: Seung-Yeop Myong
  • Patent number: 8481357
    Abstract: A method for fabricating a photovoltaic (PV) cell panel wherein all PV cells are formed simultaneously on a two-dimensional array of monocrystalline silicon mother wafers affixed to a susceptor is disclosed. Porous silicon separation layers are anodized in the surfaces of the mother wafers. The porous film is then smoothed to form a suitable surface for epitaxial film growth. An epitaxial reactor is used to grow n- and p-type films forming the PV cell structures. A glass/ceramic handling layer is then formed on the PV cell structures. The PV cell structures with handling layers are then exfoliated from the mother wafer. The array of mother wafers may be reused multiple times, thereby reducing materials costs for the completed solar panels. The glass/ceramic handling layers provide structural integrity to the thin epitaxial solar cells during the separation process and subsequent handling.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: July 9, 2013
    Assignee: Crystal Solar Incorporated
    Inventors: Ananda H. Kumar, Tirunelveli S. Ravi, Vidyut Gopal
  • Patent number: 8482093
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: July 9, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8476727
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: July 2, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8471313
    Abstract: A solid-state imaging device includes a substrate, a plurality of photodiodes arranged in the substrate in a depth direction of the substrate, a vertical readout gate electrode for reading signal charges in the photodiodes, the vertical readout gate electrode being embedded in the substrate such that the readout gate electrode extends in the depth direction of the substrate, a dark-current suppressing area which covers a bottom portion and a side surface of the readout gate electrode, the dark-current suppressing area including a first-conductivity-type semiconductor area having a uniform thickness on the side surface of the readout gate electrode, and a reading channel area disposed between the first-conductivity-type semiconductor area and the photodiodes, the reading channel area including a second-conductivity-type semiconductor area.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: June 25, 2013
    Assignee: Sony Corporation
    Inventor: Hiroshi Takahashi
  • Patent number: 8466533
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: June 18, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Publication number: 20130139877
    Abstract: A multijunction solar cell including a window layer with a gradation in doping; an upper first solar subcell having a first band gap adjacent to the window layer; a second solar subcell adjacent to said first solar subcell; a first graded interlayer adjacent to said second solar subcell, said first graded interlayer having a third band gap greater than said second band gap; a third solar subcell adjacent to said first graded interlayer; a second interlayer adjacent to said third solar subcell, said second graded interlayer having a fifth band gap greater than said fourth band gap; a fourth solar subcell adjacent to said second graded interlayer, such that said fourth subcell is lattice mismatched with respect to said third subcell.
    Type: Application
    Filed: February 15, 2013
    Publication date: June 6, 2013
    Applicant: Emcore Solar Power, Inc.
    Inventor: Arthur Cornfeld
  • Publication number: 20130122638
    Abstract: Multijunction solar cells having at least four subcells are disclosed, in which at least one of the subcells comprises a base layer formed of an alloy of one or more elements from group III on the periodic table, nitrogen, arsenic, and at least one element selected from the group consisting of Sb and Bi, and each of the subcells is substantially lattice matched. Methods of manufacturing solar cells and photovoltaic systems comprising at least one of the multijunction solar cells are also disclosed.
    Type: Application
    Filed: December 7, 2012
    Publication date: May 16, 2013
    Applicant: Solar Junction Corporation
    Inventor: Solar Junction Corporation
  • Publication number: 20130118566
    Abstract: Multijunction solar cells having at least four subcells are disclosed, in which at least one of the subcells comprises a base layer formed of an alloy of one or more elements from group III on the periodic table, nitrogen, arsenic, and at least one element selected from the group consisting of Sb and Bi, and each of the subcells is substantially lattice matched. Methods of manufacturing solar cells and photovoltaic systems comprising at least one of the multijunction solar cells are also disclosed.
    Type: Application
    Filed: November 15, 2012
    Publication date: May 16, 2013
    Applicant: Solar Junction Corporation
    Inventor: Solar Junction Corporation
  • Patent number: 8440471
    Abstract: A method of flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: May 14, 2013
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Mahmud Assar
  • Patent number: 8441090
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: May 14, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8435823
    Abstract: According to one embodiment, a method of manufacturing a back-illuminated solid-state imaging device including forming a mask with apertures corresponding to a pixel pattern on the surface of a semiconductor layer, implanting second-conductivity-type impurity ions into the semiconductor layer from the front side of the layer to form second-conductivity-type photoelectric conversion parts and forming a part where no ion has been implanted into a pixel separation region, forming at the surface of the semiconductor layer a signal scanning circuit for reading light signals obtained at the photoelectric conversion parts after removing the mask, and removing the semiconductor substrate and a buried insulating layer from the semiconductor layer after causing a support substrate to adhere to the front side of the semiconductor layer.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: May 7, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirofumi Yamashita
  • Patent number: 8415713
    Abstract: This invention provides a photo-FET, in which a FET part and photodiode part are stacked, and the FET part and photodiode part are optimized independently in design and operational bias conditions. The semiconductor layer serving as a photo-absorption layer (41) is formed on the cathode semiconductor layer (10) of a photodiode part (50). An electron barrier layer (40) with a wider bandgap semiconductor than a photo-absorption layer (41), which also serves as an anode layer of a photodiode part (50), is formed on a photo-absorption layer (41). The channel layer (15) which constitutes the channel regions of the FET part is formed with a narrower bandgap semiconductor than an electron barrier layer (40) on an electron barrier layer (40). The hole barrier layer (16) with a bandgap wider than the semiconductor which constitutes a channel layer (15) is formed on a channel layer (15). The source electrode (30) and drain electrode (32) which are separated each others, are formed on a hole barrier layer (16).
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: April 9, 2013
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventor: Mutsuo Ogura
  • Patent number: 8409907
    Abstract: A method for manufacturing a semiconductor device for detecting a physical amount distribution, the semiconductor device comprising unit components arrayed in a predetermined order, the unit components each including a unit signal generation portion for detecting an electromagnetic wave and outputting the corresponding unit signal. A diffraction grating is provided on the incident light side of a spectral image sensor, the diffraction grating including scatterers, slits, and scatterers disposed in that order. An electromagnetic wave is scattered by the scatterers to produce diffracted waves, and by using the fact that interference patterns between the diffracted waves change with wavelengths, signals are detected for respective wavelengths by photoelectric conversion elements in each photodiode group.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: April 2, 2013
    Assignee: Sony Corporation
    Inventors: Atsushi Toda, Hirofumi Sumi
  • Patent number: 8411197
    Abstract: An image pickup device is disclosed that has little deformation caused by thermal expansion of a transparent resin for sealing an image pickup element. The image pickup device includes an image pickup element having a light receiving surface, a micro-lens for condensing incident light to the image pickup element, a first transparent plate disposed on the light receiving surface of the image pickup element with the micro-lens in between, a transparent resin that seals the image pickup element and the first transparent plate, and a second transparent plate disposed on the transparent resin to face the first transparent plate.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: April 2, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Naoyuki Watanabe, Toshiyuki Honda, Yoshito Akutagawa, Susumu Moriya, Izumi Kobayashi
  • Patent number: 8399282
    Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, forming vias that pass through the anti-reflective layer and the back side dielectric layer and contact back sides of super contacts which are formed on the Si substrate, and forming a pad on the back side dielectric layer such that the pad is electrically connected to the vias.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: March 19, 2013
    Assignee: Siliconfile Technologies Inc.
    Inventors: Heui Gyun Ahn, Se Jung Oh, In Gyun Jeon, Jun Ho Won
  • Publication number: 20130026366
    Abstract: A vertically stacked thermopile and an IR sensor using said stacked thermopiles are provided. The vertically stacked thermopile may include multiple thermocouples stacked vertically on one another. The thermocouples may be connected in series, parallel, or a combination of series and parallel. One or more vertically stacked thermopiles may be included in an IR sensor and the thermopiles may be connected in series, parallel, or a combination of series and parallel.
    Type: Application
    Filed: March 17, 2011
    Publication date: January 31, 2013
    Applicant: Excelitas Canada Inc.
    Inventors: Reiner Quad, Arthur Barlow, Yuan Hsi Chan, Michael Ersoni, Hermann Karagozoglu, Radu M. Marinescu
  • Patent number: 8338263
    Abstract: Methods of forming isolation structures are disclosed. A method of forming isolation structures for an image sensor array of one aspect may include forming a dielectric layer over a semiconductor substrate. Narrow, tall dielectric isolation structures may be formed from the dielectric layer. The narrow, tall dielectric isolation structures may have a width that is no more than 0.3 micrometers and a height that is at least 1.5 micrometers. A semiconductor material may be epitaxially grown around the narrow, tall dielectric isolation structures. Other methods and apparatus are also disclosed.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: December 25, 2012
    Assignee: OmniVision Technologies, Inc.
    Inventors: Chia-Ying Liu, Keh-Chiang Ku, Wu-Zhang Yang
  • Patent number: 8329495
    Abstract: A method of forming a PV module includes forming conductors on a top surface of a PV coated substrate; forming insulators on the top surface of the PV coated substrate; and cutting the PV coated substrate to form a plurality of individual PV cells. The PV coated substrate is cut so that each of the PV cells has some of the conductors and an insulator on its top surface. Multiple PV cells are then joined to form a PV module by attaching an edge of a first one of the PV cells under an edge of a second one of the PV cells so that at least a portion of the conductors on the first PV cell electrically contacts a bottom surface of the second PV cell.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: December 11, 2012
    Assignee: Preco, Inc.
    Inventor: Chris Walker
  • Patent number: 8324012
    Abstract: A tandem solar cell and fabricating method thereof are disclosed. The steps of the fabricating method comprises: a top inverted solar cell having a plurality of inverted solar sub-cells is provided; a bottom normal solar cell having a plurality of normal solar sub-cells accompanying with the inverted solar sub-cells is provided; and processing fit process of the top inverted solar cell and the bottom normal solar cell is executed, wherein an interlayer is disposed between the bottom normal solar cell and the top inverted solar cell, and the interlayer includes a plurality of conductive dots. The plurality of inverted solar sub-cells and normal solar sub-cells are placed with an offset distance from each other, and a plurality of solar sub-cells are formed after the pressing fit process, and the plurality of solar sub-cells are series/parallel connection each other by electrically connecting the plurality of conductive dots.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: December 4, 2012
    Assignee: National Tsing Hua University
    Inventors: Sheng-Fu Horng, Hsin-Fe Meng, Ming-Kun Lee, Jen-Chun Wang, Tsung-Te Chen
  • Patent number: 8313975
    Abstract: The purpose is manufacturing a photoelectric conversion device with excellent photoelectric conversion characteristics typified by a solar cell with effective use of a silicon material. A single crystal silicon layer is irradiated with a laser beam through an optical modulator to form an uneven structure on a surface thereof. The single crystal silicon layer is obtained in the following manner; an embrittlement layer is formed in a single crystal silicon substrate; one surface of a supporting substrate and one surface of an insulating layer formed over the single crystal silicon substrate are disposed to be in contact and bonded; heat treatment is performed; and the single crystal silicon layer is formed over the supporting substrate by separating part of the single crystal silicon substrate fixed to the supporting substrate along the embrittlement layer or a periphery of the embrittlement layer.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: November 20, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Fumito Isaka, Sho Kato, Junpei Momo
  • Patent number: 8298854
    Abstract: The objective of this invention is to provide a type of photodiode and the method of manufacturing the photodiode characterized by the fact that it has a higher photoelectric conversion efficiency (sensitivity) than that in the prior art. PIN photodiode 100 has a p-type silicon substrate, p-type silicon layer 112, n-type silicon layer 114 formed on p-type silicon layer 112 and having a junction plane with silicon layer 112, n-type low-resistance silicon region 116 that is formed to a prescribed depth from the surface of silicon layer 114 and has an impurity concentration higher than that of silicon layer 114, silicon oxide film 120 formed on silicon region 116, and silicon nitride film 122 formed on silicon oxide film 120.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: October 30, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroyuki Tomomatsu, Akihiro Sugihara, Motoaki Kusamaki, Tohru Kato
  • Patent number: 8288195
    Abstract: A method is presented for fabrication of a three-dimensional thin-film solar cell semiconductor substrate from a template. A semiconductor template having three-dimensional surface features comprising a top surfaces substantially aligned along a (100) crystallographic plane of semiconductor template and a plurality of inverted pyramidal cavities defined by sidewalls substantially aligned along a (111) crystallographic plane is formed according to an anisotropic etching process. A dose of relatively of high energy light-mass species is implanted in the template at a uniform depth and parallel to the top surfaces and said sidewalls defining the inverted pyramidal cavities of the template. The semiconductor template is annealed to convert the dose of relatively of high energy light-mass species to a mechanically-weak-thin layer. The semiconductor template is cleaved along the mechanically-weak-thin layer to release a three-dimensional thin-film semiconductor substrate from the semiconductor template.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: October 16, 2012
    Assignee: Solexel, Inc.
    Inventors: David Xuan-Qi Wang, Mehrdad M. Moslehi
  • Patent number: 8263855
    Abstract: Apparatus and Method for Optimizing the Efficiency of a Bypass Diode in Solar Cells. In a preferred embodiment, a layer of TiAu is placed in an etch in a solar cell with a contact at a doped layer of GaAs. Electric current is conducted through a diode and away from the main cell by passing through the contact point at the GaAs and traversing a lateral conduction layer. These means of activating, or “turning on” the diode, and passing the current through the circuit results in greater efficiencies than in prior art devices. The diode is created during the manufacture of the other layers of the cell and does not require additional manufacturing.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: September 11, 2012
    Assignee: Emcore Solar Power, Inc.
    Inventors: Paul R. Sharps, Marvin Brad Clevenger, Mark A Stan
  • Patent number: 8263971
    Abstract: The OLED display device includes a first stack and a second stack that are separated from each other between an anode electrode and a cathode electrode, with a charge generation layer sandwiched between the first stack and the second stack, each of the first stack and the second stack having an emission layer. The first stack includes a blue emission layer formed between the anode electrode and the CGL. The second stack includes a fluorescent green emission layer and a phosphorescent red emission layer formed between the cathode electrode and the CGL. The blue emission layer includes one of a fluorescent blue emission layer and a phosphorescent blue emission layer.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: September 11, 2012
    Assignee: LG Display Co., Ltd.
    Inventor: Sung Hoon Pieh
  • Patent number: 8258596
    Abstract: To provide a stacked photoelectric conversion device and a method for producing the same, in which an interlayer is provided between photoelectric conversion layers to obtain an effect of controlling the amount of incidence light, and carrier recombination at an interface between the interlayer and a semiconductor layer is decreased to enhance photoelectric conversion efficiency. The stacked photoelectric conversion device of the present invention comprises a plurality of silicon-based photoelectric conversion layers having a p-i-n structure stacked, wherein at least a pair of adjacent photoelectric conversion layers have an interlayer of a silicon nitride therebetween, the pair of the photoelectric conversion layers are electrically connected with each other, and a p-type silicon-based semiconductor layer constituting a part of the photoelectric conversion layer and contacting the interlayer contains a nitrogen atom.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: September 4, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshiyuki Nasuno, Noriyoshi Kohama, Takanori Nakano
  • Publication number: 20120211068
    Abstract: A multijunction solar cell including an upper first solar subcell, and the base-emitter junction of the upper first solar subcell being a homojunction; a second solar subcell adjacent to said first solar subcell; a third solar subcell adjacent to said second solar subcell. A first graded interlayer is provided adjacent to said third solar subcell. A fourth solar subcell is provided adjacent to said first graded interlayer, said fourth subcell is lattice mismatched with respect to said third subcell. A second graded interlayer is provided adjacent to said fourth solar subcell; and a lower fifth solar subcell is provided adjacent to said second graded interlayer, said lower fifth subcell is lattice mismatched with respect to said fourth subcell.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 23, 2012
    Applicant: Emcore Solar Power, Inc.
    Inventors: Arthur Cornfeld, John Spann, Pravin Patel, Mark A. Stan, Benjamin Cho, Paul R. Sharps, Daniel J. Aiken
  • Patent number: 8236600
    Abstract: A method of manufacturing a solar cell by providing a first semiconductor substrate and depositing a first sequence of layers of semiconductor material to form a first solar subcell, including a first bond layer disposed on the top of the first sequence of layers. A second semiconductor substrate is provided, and on the top surface of the second substrate a second sequence of layers of semiconductor material is deposited forming at least a second solar subcell. A second bond layer is disposed on the top of said second sequence of layers. The first solar subcell is mounted on top of the second solar subcell by joining the first bond layer to the second bond layer in an ultra high vacuum chamber, and the first semiconductor substrate is removed.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: August 7, 2012
    Assignee: Emcore Solar Power, Inc.
    Inventor: Arthur Cornfeld
  • Publication number: 20120192913
    Abstract: Fabrication of a tandem photovoltaic device includes forming a bottom cell having an N-type layer, a P-type layer and a bottom intrinsic layer therebetween. A top cell is formed relative to the bottom cell. The top cell has an N-type layer, a P-type layer and a top intrinsic layer therebetween. The top intrinsic layer is formed of an undoped material deposited at a temperature that is different from the bottom intrinsic layer such that band gap energies for the top intrinsic layer and the bottom intrinsic layer are progressively lower for each cell.
    Type: Application
    Filed: January 31, 2011
    Publication date: August 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: AHMED ABOU-KANDIL, KEITH E. FOGEL, AUGUSTIN J. HONG, JEEHWAN KIM, DEVENDRA K. SADANA
  • Publication number: 20120152321
    Abstract: A tandem photovoltaic device includes a first cell and a second cell arranged in tandem. The first cell is configured to receive incident electromagnetic radiation and includes a first charge separating layer having a first semiconducting polymer adapted to create electric charge carriers generated by electromagnetic radiation. A second cell is configured to receive electromagnetic radiation passing out of the first cell in a light propagation path. The second cell includes a second charge separating layer having a second semiconducting polymer adapted to create electric charge carriers generated by electromagnetic radiation. A first titanium oxide layer is interposed between the first and second cells, wherein the first titanium oxide layer is substantially amorphous and has a general formula of TiOx where X being a number of 1 to 1.96.
    Type: Application
    Filed: August 8, 2011
    Publication date: June 21, 2012
    Inventors: Alan J. HEEGER, Kwanghee LEE, Jin Young KIM
  • Publication number: 20120152340
    Abstract: A multi junction photovoltaic device and an integrated multi junction photovoltaic device, having a two-terminal structure, in which subsequent layers can be stacked under conditions with minimal restrictions imposed by previously stacked layers. Also, processes for producing these photovoltaic devices. A plurality of photovoltaic cells having different spectral sensitivity levels are stacked such that at least the photovoltaic cells (2, 4) at the light-incident end and the opposite end have a conductive thin-film layer (5a, 5d) as the outermost layer that undergoes connection, the remaining photovoltaic cell (3) has conductive thin-film layers (5b, 5c) as the outermost layers that undergo connection, and the outermost layers are bonded via anisotropic conductive adhesive layers (6a, 6b) containing conductive microparticles within a transparent insulating material.
    Type: Application
    Filed: June 10, 2010
    Publication date: June 21, 2012
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Michio Kondo, Takashi Koida, Yoshiaki Takeuchi, Satoshi Sakai, Yasuhiro Yamauchi
  • Publication number: 20120152339
    Abstract: A method is disclosed for manufacturing a thin film substrate solar cell that has a metal electrode, a photoelectric conversion layer, and a transparent electrode stacked in this order on a substrate, the photoelectric conversion layer combining, in a thickness direction, two or more n, i, p junctions with non-single crystal silicon as main materials thereof. A top cell which is the photoelectric conversion layer on the side of the transparent electrode and another cell of one or more layers on the side of the metal electrode relative to the top cell are provided. The method includes a step of simultaneously removing at least the two or more photoelectric conversion layers and the transparent electrode using a laser with a wavelength having selective sensitivity with respect to the top cell, from the side of the transparent electrode, followed by blowing-away.
    Type: Application
    Filed: February 8, 2012
    Publication date: June 21, 2012
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Shinji FUJIKAKE
  • Patent number: 8202755
    Abstract: Various embodiments of the present invention are directed to a photodiode module including a structure configured to selectively couple light to a dielectric-surface mode of a photonic crystal of the photodiode module. In one embodiment of the present invention, a photodiode module includes a semiconductor structure having a p-region and an n-region. The photodiode module further includes a photonic crystal having a surface positioned adjacent to the semiconductor structure. A diffraction grating of the photodiode module may be positioned and configured to selectively couple light incident on the diffraction grating to a dielectric-surface mode associated with the surface of the photonic crystal. In another embodiment of the present invention, a photodiode apparatus includes multiple, stacked photodiode modules, each of which is configured to selectively absorb light at a selected wavelength or range of wavelengths.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: June 19, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: David Fattal, Jason Blackstock, Duncan Stewart
  • Publication number: 20120145231
    Abstract: A photovoltaic (PV) device has at least one lower PV cell on a substrate, the cell having a metallic back contact, and a absorber, and a transparent conductor layer. An upper PV cell is adhered to the lower PV cell, electrically in series to form a stack. The upper PV cell has III-V absorber and junction layers, the cells are adhered by transparent conductive adhesive having filler of conductive nanostructures or low temperature solder. The upper PV cell has no substrate. An embodiment has at least one shape of patterned conductor making contact to both a top of the upper and a back contact of the lower cells to couple them together in series. In an embodiment, a shape of patterned conductor draws current from excess area of the lower cell to the upper cell, in an alternative embodiment shapes of patterned conductor couples I-III-VI cells not underlying upper cells in series strings, a string being in parallel with at least one stack.
    Type: Application
    Filed: December 13, 2010
    Publication date: June 14, 2012
    Inventors: Lawrence M. Woods, Joseph H. Armstrong
  • Publication number: 20120138134
    Abstract: A stack-type photovoltaic element with improved conversion efficiency having an intermediate layer and a method of manufacturing the same are provided. A stack-type photovoltaic element according to the present invention includes a first photovoltaic element portion (a) and a second photovoltaic element portion from a substrate side, as well as at least one intermediate layer between the first photovoltaic element portion and the second photovoltaic element portion. The intermediate layer is formed from a metal oxide film having an oxygen atom concentration/metal atom concentration ratio not lower than 0.956 and not higher than 0.976.
    Type: Application
    Filed: August 25, 2010
    Publication date: June 7, 2012
    Inventors: Makoto Higashikawa, Takako Shimizu, Shinya Honda, Yasuaki Ishikawa, Yuichi Sano
  • Patent number: 8178370
    Abstract: A method for large scale manufacture of photovoltaic devices includes loading a substrate into a load lock station and transferring the substrate in a controlled ambient to a first process station. The method includes using a first physical deposition process in the first process station to cause formation of a first conductor layer overlying the surface region of the substrate. The method includes transferring the substrate to a second process station, and using a second physical deposition process in the second process station to cause formation of a second layer overlying the surface region of the substrate. The method further includes repeating the transferring and processing until all thin film materials of the photovoltaic devices are formed. In an embodiment, the invention also provides a method for large scale manufacture of photovoltaic devices including feed forward control. That is, the method includes in-situ monitoring of the physical, electrical, and optical properties of the thin films.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: May 15, 2012
    Assignee: Stion Corporation
    Inventors: Howard W. H. Lee, Chester A. Farris, III