Abstract: A method of etching an opening having tapered wall in a layer of silicon carbide (SiC) includes forming a layer of a resist on the SiC layer. An opening having tapered wall is formed in the resist layer so as to expose a portion of the SiC layer. The exposed portion of the SiC layer is then exposed to a plasma of a gas containing carbon and fluorine to etch an opening through the SiC layer with the opening having tapered walls. If a layer of a glass is provided under the SiC layer, the plasma will also etch through the glass layer to provide an opening in the glass layer having tapered walls.

Abstract: A method of removing a planarized insulating layer from over an alignment mark on a wafer. The invention allows steppers to see alignment marks without the difficulty of viewing the alignment marks through the insulating layer overlying the alignment marks. The method begins by chemical mechanical polishing a conformal oxide layer over a substrate. Next, a first photoresist layer is formed over the conformal oxide layer. Then vias are etched in the conformal oxide layer in the device area and etch the conformal oxide layer in the alignment mark area. Subsequently, we form a second photoresist layer over the first photoresist layer and the conformal oxide layer. The second photoresist layer filling the vias, but not the alignment mark resist opening. Then etch the second photoresist layer leaving sidewall spacers on the sidewall of the first photoresist layer in the alignment mark area and leaving photoresist plugs filling the vias.

Abstract: A novel process for forming a window, illustratively, an emitter window BiCMOS process is disclosed. An anisotropic etch followed by an isotropic etch to open the window is disclosed. The isotropic etch prevents contamination of the substrate by the anisotropic etching process.

Abstract: A method for use in the fabrication of semiconductor devices includes forming a titanium nitride film and depositing a silicon hard mask over the titanium nitride film. The silicon hard mask is used to pattern a titanium nitride interconnect from the titanium nitride film and the silicon hard mask is also used as a contact etch stop for forming a contact area. In forming the interconnect, the silicon hard mask is dry etched stopping selectively on and exposing portions of the titanium nitride film and the exposed portions of the titanium nitride film are etched resulting in the titanium nitride interconnect. In using the silicon hard mask as a contact etch stop, an insulating layer is deposited over the silicon hard mask and the insulating layer is etched using the silicon hard mask as an etch stop to form the contact area. The silicon hard mask is then converted to a metal silicide contact area. Interconnects formed using the method are also described.

Abstract: A method for forming a patterned silicon containing dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a silicon containing dielectric layer. There is then formed upon the silicon containing dielectric layer a hard mask layer, where the hard mask layer leaves exposed a portion of the silicon containing dielectric layer. There is then etched partially through a first plasma etch method the silicon containing dielectric layer to form a partially etched silicon containing dielectric layer. The first plasma etch method employs a first etchant gas composition comprising a first fluorocarbon etchant gas which predominantly forms a fluoropolymer layer upon at least the hard mask layer. Finally, there is then etched through a second plasma etch method the partially etched silicon containing dielectric layer to form a patterned silicon containing dielectric layer.

Abstract: A plasma etch process for an insulating layer, such as silicon dioxide, overlaying a silicide layer having a high selectivity with respect to the silicide layer is disclosed, comprising the use of a mixture of a nitrogen-containing gas and one or more other fluorine-containing etch gases in an etch chamber maintained within a pressure range of from about 5 millitorr to about 400 millitorr. The high selectivity exhibited by the etch process of the invention permits operation of the etch process at reduced pressures of from as low as 5 millitorr to about 30 millitorr to achieve complete etching of vertical sidewall openings in the oxide layer with significant overetch capability.

Abstract: A method for forming a semiconductor device having a via by using a composite dielectric layer is disclosed. The method includes forming a first dielectric layer over a first conductive layer disposed on a substrate, where the first dielectric layer has a first etch rate. A second dielectric layer is then formed on the first dielectric layer, where the second dielectric layer has a second etch rate higher than the first etch rate. The second dielectric layer is isotropically removed by masking and etching to form a rounded contoured recess in the second dielectric layer using the first dielectric layer as an etch stop layer. The first dielectric layer is anisotropically removed by masking and etching to form the via in the first dielectric layer, where the bottom of the rounded contoured recess is aligned to the via.

Abstract: In the manufacture of 16 Mbits DRAM chips, a polysilicon strap is used to provide an electrical contact between the drain region of the active NFET device and one electrode of the storage capacitor for each memory cell. The storage capacitor is formed in a trench etch in a silicon substrate which is partially filled with polysilicon. The substrate is conformally coated by a TEOS SiO.sub.2 collar layer having a non-uniform thickness. A chemistry having a high TEOS SiO.sub.2 /Si3N.sub.4 and polysilicon selectively (i.e. which etches TEOS SiO.sub.2 faster than Si.sub.3 N.sub.4 and polysilicon by a factor of at least 6) is used to anisotropically etch the collar layer. C.sub.4 F.sub.8 /Ar/C) mixtures which have selectivities of 9:1 and 15:1 are adequate. When the surface of the Si.sub.3 N.sub.

Abstract: A dry etch process for use in the fabrication of integrated circuits which use SiN etch stop layers is disclosed. The process is conducted in a reactive-ion etch reactor and employs a gaseous etchant mixture comprised of octaflourocyclobutane (C.sub.4 F.sub.8), carbon monoxide (CO) and Ar. The specific process parameters effect the formation of a polymer on SiN but not on oxide, thereby resulting in a very high etch rate selectivity of the oxide to the nitride.

Abstract: A new method for planarization of shallow trench isolation is disclosed by using wet selective etching. The formation of the shallow trench isolation described herein includes a pad layer, a silicon nitride layer formed on a semiconductor substrate. A PE-TEOS oxide layer is subsequently formed on the silicon nitride layer. Then a shallow trench is created by photolithography and dry etching processes to etch the PE-TEOS oxide layer, the silicon nitride layer and the pad layer. Then, the photoresist is removed, an ozone-TEOS layer is form in the shallow trench and on the PE-TEOS oxide layer for the purpose of isolation. A wet selective etching is used to etch the ozone-TEOS layer. A CMP is performed to make the surface of the substrate with a planar surface. Then, a thermal annealing is used for densification of the ozone-TEOS layer and for forming a lining oxide to improve the isolation of the shallow trench isolation.

Abstract: A process for forming a planarized, insulator, or silicon oxide filled shallow trench has been developed. The process features a hybrid planarization procedure, comprised of an initial dry etching cycle, used to remove all but about 100 to 500 Angstroms of silicon oxide, from subsequent device regions, or regions outside the insulator filled trench. Silicon oxide residing on the insulator filled trench is protected by a photoresist shape. A final chemical mechanical polishing procedure is than employed to remove both the silicon oxide, on the insulator filled shallow trench, as well as removing the remaining silicon oxide on silicon nitride, in subsequent device regions. An endpoint monitoring procedure allows the detection of the remaining 100 to 500 Angstroms of silicon oxide, on silicon nitride.

Abstract: A plasma etch method for forming a patterned silicon nitride layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket silicon nitride layer. There is then formed upon the blanket silicon nitride layer a patterned photoresist layer. Finally, there is etched through a plasma etch method while employing the patterned photoresist layer as an etch mask layer the blanket silicon nitride layer to form a patterned silicon nitride layer. The plasma etch method employs an etchant gas composition comprising a perfluorocarbon etchant gas, a hydrofluorocarbon etchant gas and an oxygen etchant gas at a perfluorocarbon etchant gas flow rate, a hydrofluorocarbon etchant gas flow rate and an oxygen etchant gas flow rate which yields substantially no plasma etch bias of the patterned silicon nitride layer with respect to the patterned photoresist layer.

Abstract: Method for semiconductor processing comprising etching of oxide layers, especially etching thick SiO.sub.2 layers and/or last step in the cleaning process wherein the oxide layers are etched in the gas phase with a mixture of hydrogen fluoride and one or more carboxylic acids, eventually in admixture with water.

Abstract: Disclosed is a method selective of vapor phase etching for fabricating a semiconductor device having a refractory metal silicide electrode abutting a silicon oxide film on the surface or a semiconductor device having an AlGaAs layer, an electrode formed on the AlGaAs layer and a silicon oxide film on the surface of the semiconductor device. The method comprises a step of removing a portion of the silicon oxide film by a gas including a vapor of hydrogen fluoride. The method further uses a mixture of nitrogen gas including vapor of anhydrous hydrofluoric acid and a nitrogen gas including a vapor of H.sub.2 O, wherein the ratio of the nitrogen gas including the vaporized anhydrous hydrofluoric acid to the nitrogen gas including vapor of H.sub.2 O is less than 1.

Abstract: A semiconductor sensor having a thin-film structure body, in which thin-film structure is prevented from bending due to the internal stress distribution in the thickness direction, is disclosed. A silicon-oxide film is formed as a sacrificial layer on a silicon substrate, and a polycrystalline-silicon thin film is formed on the silicon-oxide film. Thereafter, phosphorus (P) is ion-implanted in the surface of the polycrystalline-silicon thin film, and thereby the surface state of the polycrystalline-silicon thin film is modified. A portion of distribution of stress existing in the thickness direction of the polycrystalline-silicon thin film is changed by this modification, and stress distribution is adjusted. By removal of the silicon-oxide film, a movable member of the polycrystalline-silicon thin film is disposed above the silicon substrate with a gap interposed therebetween.

Abstract: A method for etching through a selected portion of a Borophosphosilicate Glass (BPSG) layer of the silicon wafer layer stack to a Titanium Silicide (TiSi.sub.2) layer in a plasma processing chamber is disclosed. The method includes the step of etching through the BPSG layer using an etchant source gas that includes Ne, CHF.sub.3, CO and C.sub.4 F.sub.8. Additional process parameters are disclosed for obtaining a high BPSG:TiSi.sub.2 selectivity etch with commercially advantageous BPSG etch rates.

Abstract: A method in a plasma processing chamber for etching through a selected portion of a borophosphosilicate glass (BPSG) layer of a wafer layer stack. The method includes the step of introducing an etchant source gas into the plasma processing chamber, which consists essentially of CO, CHF.sub.3, and C.sub.4 F.sub.8. The method further includes the step of striking a plasma in the plasma processing chamber from the etchant source gas. Additionally, there is included the step of etching at least partially through the BPSG layer with the plasma.

Abstract: The present invention has an object of providing a method for manufacturing a semiconductor device wherein an underlying silicon substrate or polycrystalline silicon film is less subject to etching during ashing. A method for manufacturing a semiconductor device according to the present invention comprises the steps of: covering a predetermined portion of an insulating film (2) on the silicon substrate (1) or the polycrystalline silicon film with a photoresist (3); removing a portion of said insulating film (2) not covered with the photoresist by dry etching using an etching gas containing carbon and fluorine; and removing a fluorocarbon film (6) deposited on the surface of the substrate and said photoresist 3 by ashing using at least an oxygen gas while controlling the temperature at 100.degree. C. or lower, wherein the underlying silicon substrate or polycrystalline silicon film is less subject to etching during the ashing.

Abstract: The present invention discloses a noel method for anchoring a via/contact or the forming of a capacitor having increasing capacitance in a semiconductor device by utilizing alternating layers of BPTEOS oxide and TEOS oxide and a deep UV photoresist such that toroidal-shaped cavities can be formed at the interfaces between the BPTEOS oxide layers and the TEOS oxide layers during the formation of the via/contact opening or the capacitor opening by a plasma etching process. The number of cavities formed, i.e., the number of anchors formed on the via/contact or capacitor, can be suitably adjusted by the number of BPTEOS oxide layer deposited on the semiconductor structure. Each BPTEOS oxide layer produces two anchors on the via/contact or the capacitor. The deep UV photoresist layer should contain a photo-acid-generator such that hydrogen ions are emitted when the photoresist layer is subjected to UV radiation and heating which accelerates the hydrogen ion generation process.

Abstract: A method of removing an oxide layer from an article. The article is located in a reaction chamber. An interhalogen compound reactive with the oxide layer is introduced into the reaction chamber. The interhalogen compound forms volatile by-product gases upon reaction with the oxide layer. For compounds that form volatile chlorides, bromides or iodides, a reducing gas, such as for example hydrogen, ammonia, amines, phosphine, silanes, and higher silanes, may optionally be added simultaneously with the interhalogen to form a volatile by-product. Unreacted interhalogen compound and volatile by-product gases are removed from the reaction chamber. In one embodiment, the temperature in the reaction chamber may be elevated prior to or after introducing the interhalogen compound. In another embodiment, a metal layer is deposited in-situ on a portion of the article within the reaction chamber.

Abstract: The chemoresistive gas sensor comprises a heating element integrated in a dedicated SOI substrate having an air gap in the intermediate oxide layer between two wafers of monocrystalline silicon. A sensitive element of tin oxide is formed over the heating element and separated from it by a dielectric insulating and protective layer. A trench formed at the end of the fabrication of the device, extends from the surface of the wafer in which the heating element is integrated, up to the air gap to mechanically separate and insulate the sensitive element from the rest of the chip, thereby improving the mechanical characteristics sensitivity and response of the sensor.

Abstract: Problems forming silicided and nonsilicided structures on the same silicon substrate are overcome utilizing a spacer oxide masking technique. A protective spacer oxide layer is deposited over the entire silicon substrate surface, and a silicide exclusion photoresist mask is selectively developed to permit etching of the spacer oxide layer in unmasked regions where silicides are expected to be formed. Areas of silicon substrate revealed by etching of the spacer oxide layer are exposed to silicide-forming metals, and these silicide-forming metals react with the silicon substrate to produce silicides. Spacer oxide remaining in masked regions prevents formation of silicides in those regions.

Abstract: After a resist mask is selectivity formed on an upper portion of a gate electrode containing mainly aluminum. At this state an anodization process is performed using an electrolytic solution, to form an anodic oxide film in a region other than a region of the upper portion on which the resist mask is formed. A silicon oxide film is formed to cover the gate electrode or the like Since an anodic oxide film is not formed on the region of the upper portion, contact holes for a wiring or an electrode made of aluminum are formed by etching the silicon oxide film using a hydrofluoric acid system etchant.

Abstract: A process for controlling the etch of a silicon dioxide layer at a high etch rate and high selectivity with respect to silicon nitride, particularly in a multilayer structure, by maintaining various portions of the etch chamber at elevated temperatures.

Abstract: A method is described which uses the differential etch behaviour of two different kinds of sequentially deposited silicon oxide layers in conjunction with controlled thicknesses and etching conditions to allow the etching of features such as via contact holes, oxide sidewalls, and crossover insulation edges to produce non-abrupt step height profiles for better edge coverage while still maintaining close adherence to minimum spacing design ground rules between adjacent features.

Abstract: Vias are formed in a dielectric film overlying an electrode layer by sweeping a laser beam over the area in which the via is to be formed. In particular, a Nd:YAG laser, producing a beam of light having a 266 nm wave length, effectively ablates a barium strontium titanate dielectric film, without adversely affecting an underlying platinum electrode. The present invention overcomes the problem of wet chemical etching of dielectric films to form vias. Wet chemical etching often requires etchants that adversely affect the underlying metal electrode and typically require the use of environmentally undesirable chemicals.

Abstract: A method for forming a contact hole of semiconductor device is disclosed and comprises forming a word line and a first internal insulating film on a semiconductor substrate, forming an insulating film spacer at the side wall of the word line and the first internal insulating film, forming a nitride film as a second internal insulating film at a predetermined thickness on the resultant structure, forming a planarization layer on the second internal insulating film, etching the planarization layer in an atmosphere comprising C.sub.4 F.sub.8 gas, Ar gas and a hydrogen-containing gas in the presence of a contact mask, to create a contact hole through which the second internal insulating film is exposed. The hydrogen-containing gas acts to generate C--H type polymers weaker in bond strength but at a larger amount than C--C type polymers, thereby preventing the etching stop phenomenon as well as the underlying layer damage caused by overetch during the etching process of a contact hole.

Abstract: A semiconductor processing method of forming a contact opening to a substrate includes forming at least one conductive line over the substrate adjacent a substrate contact area to which electrical connection is to be made. A first oxide layer is formed over the substrate to cover at least part of the contact area. A second oxide layer is formed over the first oxide layer and is formed from a different oxide than the first oxide layer. A first etch is conducted over the contact area and through the second oxide layer to a degree sufficient to leave at least a portion of the first oxide layer over the contact area. A second etch is conducted to a degree sufficient to remove substantially all of the first oxide layer left behind and to remove a desired amount of the second oxide layer laterally outwardly of the contact area.

Abstract: A method for forming a microelectronic structure includes the steps of forming a mask layer on a substrate, forming a trench in the exposed portion of the substrate, forming a layer of an insulating material which fills the trench and covers the mask layer, and annealing the insulating material at a temperature of at least about 1,150.degree. C. The annealing step can be performed for a period of time of about .5 hours to about 8 hours, and the annealing step can be performed in an inert atmosphere.

Abstract: A semiconductor processing method of forming a contact opening includes providing a substrate having a node location to which electrical connection is to be made. A layer comprising doped silicon dioxide is formed over the node location. Thereafter, both O.sub.2 and O.sub.3 are flowed simultaneously to the substrate along with tetraethylorthosilicate to the substrate to form a continuous layer comprising undoped silicon dioxide on the layer comprising doped silicon dioxide. During the flowing, a ratio of O.sub.3 to O.sub.2 flows is increased to form an outer portion of the continuous layer comprising undoped silicon dioxide to have a higher etch rate for a selected wet etch chemistry than an inner portion of said continuous layer. A common contact opening is anisotropically dry etched into the layer comprising undoped silicon dioxide and into the layer comprising doped silicon dioxide over the node location to outwardly expose the node location.

Abstract: A first semiconductor layer and a second semiconductor layer are laminated on a semiconductor wafer in that order. A resist pattern having an opening is formed on the second semiconductor layer. The second semiconductor layer is etched through the opening in the formed resist pattern to expose the first semiconductor layer. A surface oxide film is formed on the exposed surface of the first semiconductor layer and then selectively etched away. Alternatively, the exposed surface of the first semiconductor layer is subjected to a separate oxidization treatment and the resulting surface oxide film is selectively removed in the subsequent etching.

Abstract: A method for forming a via through a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines a contact beneath the patterned silicon nitride layer. There is then formed over the patterned silicon nitride layer a silicon oxide layer. There is then etched the silicon oxide layer through a first reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas to form: (1) an etched silicon oxide layer which exposes the contact without substantially etching the patterned silicon nitride layer; and (2) a fluorocarbon polymer residue layer formed upon at least one of the etched silicon oxide layer and the patterned silicon nitride layer. Finally, there is stripped from the substrate the fluorocarbon polymer residue layer through a second reactive ion etch (RIE) method employing a second etchant gas composition comprising carbon tetrafluoride and oxygen.

Abstract: The present invention provides a method of to planarize a spin-on-glass layer overlying a HDP-CVD oxide layer using a six etchback process. The process comprises: forming a spin-on-glass layer 40 over a plasma chemical vapor deposition (HDP-CVD)oxide layer 30 over spaced raised portions 20 on a semiconductor structure. The spin-on-glass and the density plasma chemical vapor deposition (HDP-CVD) oxide layer 30 are then planarized using a six etch back process comprising: Step 2, (Etch High), a CF4 gas flow of between about 88 and 108 sccm, CHF.sub.3 flow between about 35 and 45 sccm, an argon flow of between about 40 and 60 sccm, at a pressure of between about 210 and 310 mtorr, at a power of between 650 and 950 watts; Step 3 (Etch Low) a CF4 gas flow of between about 10 and 20 sccm, CHF.sub.

Abstract: One embodiment of the instant invention is a method of preventing the formation of silicic acid on exposed silicon of an electronic device formed on a silicon wafer and having silicon features, the method comprising: removing a portion of oxide (step 302) formed on the silicon wafer thereby exposing at least some portion of the silicon substrate or the silicon features; cleaning the silicon wafer by subjecting the silicon wafer to an ozonated solution (step 304), preferably deionized water; and drying the silicon wafer (step 306). Preferably, a thin oxide is formed on the silicon wafer during the step of subjecting the wafer to the ozonated solution. The thin oxide is, preferably, on the order of approximately 6 to 20 .ANG. thick. After removing said portions of oxide and thereby exposing portions of said silicon wafer and/or silicon feature, the exposed silicon becomes hydrophobic.

Abstract: A method in a plasma processing chamber for fabricating a semiconductor device having a self-aligned contact. The method includes the step of providing a wafer having a substrate, a polysilicon layer disposed above the substrate, a nitride layer disposed above a polysilicon layer, and an oxide layer disposed above the nitride layer. The method further includes the step of etching in a first etching step partially through the oxide layer of the layer stack with a first chemistry and a first set of process parameters. In this first etching step, the first chemistry comprises essentially of CHF.sub.3 and C.sub.2 HF.sub.5. The method also includes the step of etching the oxide layer in a second etching step through to the substrate with a second chemistry comprising CHF.sub.3 and C.sub.2 HF.sub.5 and a second set of process parameters.

Abstract: A method of cleaning wafer surfaces includes providing a wafer surface and cleaning the wafer surface using at least hydrofluoric acid (HF) and an etch reducing component. The etch reducing component is from the group of (R).sub.4 NOH wherein R=(C.sub.1 -C.sub.20)alkyls, either straight or branch chained, and further wherein each R is independently a (C.sub.1 -C.sub.20)alkyl, preferably a (C.sub.1 -C.sub.4)alkyl, and more preferably one of tetra ethyl ammonium hydroxide (TEAH) and tetra methyl ammonium hydroxide (TMAH). A cleaning solution for use in cleaning a wafer surface includes an H.sub.2 O diluted HF solution and an etch reducing component from the group above, preferably, TMAH. A system for performing an HF vapor cleaning process includes a vapor chamber for positioning a wafer having a wafer surface and means for providing an HF vapor to the vapor chamber. The HF vapor includes an inert carrier gas, an HF component, one of a water vapor or an alcohol vapor, and an etch reducing component.

Abstract: Pitting in active regions along the edges of a gate electrode when etching a composite comprising an anti-reflective coating on polysilicon is avoided by etching the anti-reflective coating with an etchant that forms a protective passivating coating on at least the sidewalls of the etched anti-reflective pattern and on the underlying polysilicon layer. Subsequently, anisotropic etching is conducted to remove the protective passivating coating from the surface of the polysilicon layer, leaving the etched anti-reflective pattern protected from the main polysilicon etch on at least its sidewalls by the passivating coating to prevent interaction. In another embodiment, the anti-reflective coating is etched without formation of a passivating coating, and the polysilicon layer subsequently etched with an etchant that forms a passivating coating.

Abstract: An improved process is described for the post-etching treatment after subtractive etching of aluminum and aluminum-alloy layers in the fabrication of semiconductor integrated circuit devices. The improvement consists of in situ exposure immediately after subtractive etching of the metal pattern to a reactive plasma sustained in a mixture of oxygen and carbon tetrafluoride gases by continuous radiofrequency power input for a controlled period of time.

Abstract: A method for etching a silicon nitride film, includes the steps of supplying a fluorine radical, a compound of fluorine and hydrogen, and an oxygen radical close to a substrate having the silicon nitride film, and selectively etching the silicon nitride film from the substrate with the fluorine radical, the compound of fluorine and hydrogen, and the oxygen radical.

Abstract: A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.

Abstract: A method and apparatus for improving the accuracy of a contact to an underlying layer comprises the steps of forming a first photoresist layer over the underlying layer, forming a mask layer over the first photoresist layer, then forming a patterned second photoresist layer over the mask layer. The mask layer is patterned using the second photoresist layer as a pattern then the first photoresist layer is patterned using the mask layer as a pattern. A tapered hole is formed in the first photoresist layer, for example using an anisotropic etch. The tapered hole has a bottom proximate the underlying layer and a top distal the underlying layer with the top of the hole being wider than the bottom of the hole.

Abstract: In a method of removing a polymer and the leavings of the resist pattern that have adhered during dry etching to a film formed on a semiconductor substrate, the etched film undergoes plasma etching with the resist patter as a mask. Next, the resist pattern is removed by O.sub.2 plasma ashing and then the surface of the substrate is washed with pure water. Thereafter, with the substrate heated to 40.degree. C. or higher, the surface of the substrate is exposed to HF vapor and then the surface of the substrate is rinsed with pure water. With this method, the polymer and the leavings of the resist pattern that have adhered to the etched film can be removed easily.

Abstract: In a method for the selective removal of SiO.sub.2 relative to semiconductor materials and/or metal, a specimen to be processed and containing SiO.sub.2 is placed into a chamber having at least one gas admission opening and one gas outlet opening. Using controllable valves at the gas admission opening, dosed quantities of hydrogen fluoride gas and water vapor are admitted into the chamber. These gasses proceed to the SiO.sub.2 in a specimen in a quantity adequate for etching. However, the quantities of these gasses are limited such that a condensation of the water vapor to form liquid water on the specimen during the etching event is avoided. An etching event is then implemented. Water vapor that arises as a reaction product during the etching is eliminated through the gas outlet opening before the occurrence of condensation and, simultaneously, an inert gas is admitted into the chamber through the gas admission opening. These steps are repeated as needed.

Abstract: The present invention provides methods of removing or etching silicon oxide from a semiconductor wafer by contacting the silicon oxide with diorganocarbonates, including comprising hydrocarbyl groups that are either aliphatic, aromatic, or a combination thereof. The diorganocarbonate can include (C.sub.1 -C.sub.10)hydrocarbyl groups. Specific examples of useful diorganocarbonates include dimethylcarbonate, diethylcarbonate, dipropylcarbonate, diisopropylcarbonate, and dibutylcarbonate.

Abstract: A process for selectively removing a porous silicon oxide layer from a substrate having a portion thereon with an exposed dense silicon oxide to be retained on the substrate, the porous silicon oxide layer containing absorbed moisture therein, the process comprising:introducing the substrate to a flowing anhydrous gaseous environment consisting of anhydrous inert gas;adding anhydrous hydrogen fluoride gas to the gaseous environment for a pulse time which is at most only shortly longer than that required to initiate etching of the dense silicon oxide;flushing the gaseous environment with anhydrous inert gas for a time sufficient to remove said hydrogen fluoride and water vapor generated by the etching of the porous oxide; and,repeating said adding and flushing steps until said porous oxide layer has been removed.

Abstract: A dry etching process for use in the manufacture of silicon integrated circuit devices uses a mixture of about eight parts neon to one part CHF.sub.3 (Freon 23) to form the etching plasma. The process etches doped oxides of silicon, such as BPSG and BPTEOS, in preference to undoped oxides of silicon, silicon nitride, silicides and silicon.

Abstract: A method of manufacturing a semiconductor device. The method includes the application of a gas containing HF vapor and H.sub.2 O or alcohol vapor to a substrate. An excitation energy is applied to a flow of gas containing hydrogen to generate a plasma. Gas containing nitrogen fluoride is added to the gas containing hydrogen at a first position which is downstream from the place where the plasma is generated and at which the concentration of high energy particles in the gas containing hydrogen is negligible. The HF treated substrate is exposed to the gas containing nitrogen fluoride at a second position which is further downstream than the first position where the nitrogen fluoride is added.