Abstract: When in a chamber, an upper electrode and a lower electrode (suscepter) are provided opposite to each other and with a to-be-treated substrate supported by the lower electrode, the high-frequency electric field is formed between the upper electrode and the lower electrode to generate plasma of the process gas while introducing the process gas into the chamber held to the reduced pressure, and an etching is provided to the to-be-treated substrate with this plasma, the high frequency in the range from 50 to 150 MHZ, for example, 60 MHz, is applied to the upper electrode, and the high frequency in the range from 1 to 4 MHz, for example, 2 MHz, is applied to the lower electrode.

Abstract: When a via hole is formed in an insulating film formed by stacking a TEOS oxide film over an organic SOG film whose surface is modified as a low-K interlayer dielectric, by dry etching, a mixed gas of CHF3, CH2F2 and CO is used as an etching gas and a mixture ratio between CH2F2 and (CHF3+CH2F2) is set to 50% or more, whereby the dry etching for the formation of the via hole is performed.

Abstract: Improved methods and apparatus for chemically assisted etch processing in a plasma processing system are disclosed. In accordance with one aspect of the invention, improved techniques suitable for performing an etch process in the plasma processing can be realized. The invention operates to reduce the critical dimension bias that is associated with the etch process. Lower critical dimension bias provides many benefits. One such benefit is that features with higher aspect ratio can be etched correctly. In addition, several other undesired effects, e.g., micro loading, bowing and passivation, can be curtailed using the techniques of the present invention.

Abstract: A chamber 28 comprises a radiation source 58 capable of emitting radiation having a wavelength that is substantially absorbed in a predetermined pathlength in a thickness of a layer 22 on a substrate, and a radiation detector 62 adapted to detect the radiation. The radiation is substantially absorbed in a first thickness of the layer 22, and after at least partial processing of the layer 22, is at least partially transmitted through a second thickness of the layer 22 and reflected by one or more underlayers 24 of the substrate 20.

Abstract: A method of fabricating a device is provided. A shadow mask is positioned in a first position over a substrate. A first process is performed on the substrate through the shadow mask. After the first process is performed, the shadow mask is moved to a second position over the substrate, measured relative to the first position. After the shadow mask is moved to the second position, a second process is performed on the substrate through the shadow mask.

Abstract: A method for fabricating a capacitor of a semiconductor device is provided. In the capacitor fabricating method, the step of forming a lower electrode by using gas including chlorine is included after the step of forming hemispherical grained silicon (HSG—Si) seeds. Also, after the step of selectively growing only HSG—Si seeds formed on the lower electrode, the step of removing the HSG—Si seeds formed on an insulation layer pattern through an etching process using a gas including chlorine is included. Thus, the surface area of the lower electrode is increased, so that capacitance is increased. Also, an electrical short between the lower electrodes of each adjacent capacitor can be prevented without decreasing capacitance.

Abstract: The invention concerns a method for simultaneously forming a metallization and contact structure in an integrated circuit. The method involves the steps of etching a trench dielectric layer of a composite structure having a semiconductor substrate with an active region, a gate structure thereon, at least one dielectric spacer adjacent to the gate structure, a contact dielectric layer over the semiconductor substrate, the gate structure and the dielectric spacer, an etch stop layer over the contact dielectric layer, and a trench dielectric layer over the etch stop layer, to form a trench in the trench dielectric under etch conditions which do not substantially etch the etch stop layer; thereafter, forming an opening in the etch stop layer and the contact dielectric layer by etching under conditions which do not damage the gate structure to expose the active region; and depositing a conductive material into the opening and the trench.

Abstract: A method and apparatus for selectively removing a native oxide layer from a silicon wafer without significantly affecting the underlying silicon or other materials that may be thereon, by exposing the silicon wafer to an etchant gas including NF3 while simultaneously exposing the wafer to ultraviolet radiation, and heating the wafer to a temperature of 100-400° C.

Abstract: A semiconductor substrate is provided. A number of rows of layer stacks are formed on the semiconductor substrate with a shallow trench positioned between two adjacent layer stacks. Each layer stack is a polysilicon layer and a sacrificial layer and has two side walls. Each side wall of the layer stack intersects the bottom of the shallow trench at an angle of approximately 90 degrees. A HDPCVD silicon oxide layer is deposited to cover the layer stacks and the shallow trenches followed by a planarization process to remove portions of the HDPCVD silicon oxide layer to expose in the sacrificial layer. Then, the sacrificial layer is removed. An insulating layer, a word line layer, and a photoresist layer are formed on the polysilicon layer, respectively. The photoresist layer is patterned so as to define a position for forming a word line.

Abstract: An oxide etching process, particularly useful for selectively etching oxide over a feature having a non-oxide composition, such as silicon nitride and especially when that feature has a corner that is prone to faceting during the oxide etch. The invention uses one of three hydrogen-free fluorocarbons having a low F/C ratio, specifically hexafluorobutadiene (C4F6), hexafluorocyclobutene (C4F6), and hexafluorobenzene (C6F6). At least hexafluorobutadiene has a boiling point below 10° C. and is commercially available. The fluorocarbon together with a substantial amount of a noble gas such as argon is excited into a high-density plasma in a reactor which inductively couples plasma source power into the chamber and RF biases the pedestal electrode supporting the wafer. Preferably, one of two two-step etch process is used. In the first, the source and bias power are reduced towards the end of the etch.

Abstract: An integrated in situ oxide etch process particularly useful for a counterbore dual-damascene structure over copper having in one inter-layer dielectric level a lower nitride stop layer, a lower oxide dielectric, a lower nitride stop layer, an upper oxide dielectric layer, and an anti-reflective coating (ARC). The process is divided into a counterbore etch and a trench etch with photolithography for each, and each step is preferably performed in a high-density plasma reactor having an inductively coupled plasma source primarily generating the plasma and a capacitively coupled pedestal supporting the wafer and producing the bias power. The counterbore etch preferably includes at least four substeps of opening the ARC, etching through the upper oxide and nitride layers, selectively etching the lower oxide layer but stopping on the lower nitride layer, and a post-etch treatment for removing residue.

Abstract: The present invention provides a method for manufacturing a semiconductor device without the use of an anti-reflective coating. In one embodiment, electrical devices are formed on a semiconductor substrate. A material with a low dielectric constant such as an oxide is then deposited. The low dielectric layer is then covered with photoresist and photolithographically processed and subsequently developed. The low dielectric layer is then etched using the pattern formed on the photoresist and the photoresist is later removed. Because this process works in any similar circumstances, good examples of its application are the formation of both contacts and local interconnects.

Abstract: A method for forming a via through a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines a contact region beneath the patterned silicon nitride layer. There is then formed over the patterned silicon nitride layer a silicon oxide layer. There is then etched the silicon oxide layer while employing a reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas to form: (1) an etched silicon oxide layer which exposes the contact region without substantially etching the patterned silicon nitride layer; and (2) a fluorocarbon polymer residue layer formed upon at least one of the etched silicon oxide layer and the patterned silicon nitride layer. Finally, there is stripped from the substrate the fluorocarbon polymer residue layer while employing a downstream plasma etch method employing a second etchant gas composition comprising a fluorocarbon etchant gas and oxygen.

Abstract: An improved dry plasma cleaning process for the removal of native oxides, or other oxide films or growth residue, from openings formed in an insulating layer provided over a semiconductor substrate, without damaging the substrate or significantly affecting the critical dimension of the opening is disclosed. A mixture of nitrogen trifluoride (NF3), ammonia (NH3) and oxygen (O2) is first injected upstream into a microwave plasma source and is exited, and then the plasma is flowed downstream from the plasma source into a reaction chamber containing the substrate.

Abstract: A method for forming a multi-level metal interconnection, comprising the step of forming a first metal interconnection over an underlying layer; forming an insulating layer having a selected thickness over the underlying layer including the first metal interconnection; etching the insulating layer to form a contact hole, thereby exposing the first metal interconnection; forming a metal plug in the contact hole to contact with the first metal interconnection; etching the insulating layer by a portion of the selected thickness; forming a pair of metal spacers in sidewalls of the metal plug over the insulating layer; and forming a second metal interconnection over the insulating layer to contact with the first metal interconnection through one of the metal spacers.

Abstract: A resist mark for measuring the accuracy of overlay of a photomask disposed on a semiconductor wafer, includes a first measurement mark having a first opening, formed on the substrate, an intermediate layer formed on the first measurement mark and in the first opening, a frame-shaped second measurement mark formed on the intermediate layer, and a third measurement mark that is spaced from the second measurement mark toward the outside, formed on the intermediate layer. The second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.

Abstract: A method for making an integrated circuit preferably includes the steps of: forming a trench laterally adjacent an active region in a semiconductor substrate; forming a dielectric layer on the semiconductor substrate filling the trench and covering the active area; selectively etching the dielectric layer to remove at least a portion of the dielectric layer overlying the active region and to define a recess within the dielectric layer filling the trench to serve as an alignment mark; and polishing the selectively etched dielectric layer and leaving the alignment mark. The method may also include forming an optically opaque layer adjacent the polished dielectric layer and with the alignment mark causing a repeated alignment mark in the optically opaque layer. The alignment mark and/or repeated alignment mark may be used for alignment in a subsequent processing step.

Abstract: The invention defines a method for fabricating a semiconductor insulation layer: A semiconductor substrate is first provided; an insulation layer is applied by way of region-by-region or whole-area application to the semiconductor substrate; impurity ions are selectively implanted into at least one predetermined zone of the insulation layer; then the insulation layer is selectively etched, and the insulation layer is thereby patterned in accordance with the zone or zones of the selectively implanted impurity ions.

Abstract: A plasma etch process, particularly applicable to an self-aligned contact etch in a high-density plasma for selectively etching oxide over nitride, although selectivity to silicon is also achieved. In the process, a fluoropropane or a fluoropropylene is a principal etching gas in the presence of a substantial amount of an inactive gas such as argon. Good nitride selectivity has been achieved with hexafluoropropylene (C3F6), octafluoropropane (C3F8), heptafluoropropane (C3HF7), hexafluoropropane (C3H2F6). The process may use one or more of the these gases in proportions to optimize selectivity and a wide process window. Difluoromethane (CH2F2) or other fluorocarbons may be combined with the above gases, particularly with C3F6 for optimum selectivity over other materials without the occurrence of etch stop in narrow contact holes and with a wide process window.

Abstract: A technique for forming a borderless transistor gate and source/drain region contact structure which provides an on-chip area efficient layout and connection between the device gate layer and an associated source/drain region that can also overlap adjoining isolation structures. In a representative embodiment, this may be effectuated through the overlapping of one portion of the contact region over the edge of the gate polysilicon layer and another part of the contact over the source/drain diffusion. The structure and process of the present invention provides a desirable size reduction in the contact for given design rule dimensions and the resultant contact structure is inherently “self-aligned” to both the gate polysilicon layer and the isolation region in that the contact has no need for an interstitial space between it and the gate polysilicon or isolation regions to prevent unintended electrical connections.

Abstract: A high plasma density etch process for etching an oxygen-containing layer overlying a non-oxygen containing layer on a workpiece in a plasma reactor chamber, by providing a chamber ceiling overlying the workpiece and containing a semiconductor material, supplying into the chamber a process gas containing etchant precursor species, polymer precursor species and hydrogen, applying plasma source power into the chamber, and cooling the ceiling to a temperature range at or below about 150 degrees C. The etchant and polymer precursor species contain fluorine, and the chamber ceiling semiconductor material includes a fluorine scavenger precursor material. Preferably, the process gas includes at least one of CHF3 and CH2F2. Preferably, the process gas further includes a species including an inert gas, such as HeH2 or Ar. If the chamber is of the type including a heated fluorine scavenger precursor material, this material is heated to well above the polymer condensation temperature, while the ceiling is cooled.

Abstract: A process of exposing the head of a metal post used with a chip size package is simplified. A first semiconductor manufacturing method comprising the steps of forming an insulating resin layer R so as to completely cover the top of a metal post 8 and then polishing the resin layer so as to expose the head of the metal post, and a second semiconductor manufacturing method comprising the steps of forming an insulating resin layer R so as to completely cover the top of the metal post 8, then back grinding the wafer rear face, and then polishing the resin layer R so as to expose the head of the metal post are provided.

Abstract: The invention advantageously provides a novel method for making self-aligned contacts on a semiconductor substrate. A gate electrode having a vertical sidewall and a protecting layer thereon is formed over the semiconductor substrate. A doped region is formed in the substrate adjacent to the gate electrode. An insulating sidewall spacer is formed on the sidewall of the gate electrode. A second doped region is formed in the substrate adjacent to the sidewall spacer. A second protecting layer is formed to cover or blanket the first protecting layer, the sidewall spacer, and the substrate. An interlayer insulting layer is provided on the second protecting layer in order to form a planer surface. The interlayer insulating layer and the second protecting layer are etched to expose the doped regions to form the self-aligned contacts.

Abstract: A method and apparatus for improving the accuracy of a contact to an underlying layer comprises the steps of forming a first photoresist layer over the underlying layer, forming a mask layer over the first photoresist layer, then forming a patterned second photoresist layer over the mask layer. The mask layer is patterned using the second photoresist layer as a pattern then the first photoresist layer is patterned using the mask layer as a pattern. A tapered hole is formed in the first photoresist layer, for example using an anisotropic etch. The tapered hole has a bottom proximate the underlying layer and a top distal the underlying layer with the top of the hole being wider than the bottom of the hole.

Abstract: An integrated self aligned contact process includes oxide etch with high oxide etch rate, integrated selective oxide etch and nitride liner removal with high selectivity to corner nitride with the ability to remove the bottom nitride liner, and stripping of all polymer and photoresist. C4F8 and CH2F2 are used for the high selectivity oxide etch step. The unique behavior of CH2F2 in high density plasma allows polymer protection to form on the nitride corner/sidewall while at the same time etching the bottom nitride.

Abstract: A gas etchant composition and a method for simultaneously etching-back silicon oxide and polysilicon at substantially similar etching rates are used for manufacturing semiconductor devices. The gas etchant composition to be utilized for dry-etching includes carbon tetrafluoride gas and nitrogen gas mixed at a ratio of 25-40:1, while its etching rate ratio of polysilicon to silicon oxide is 0.8-1.2:1. Since polysilicon and silicon oxide are simultaneously etched by a single etching equipment utilizing the gas etchant composition in a single process, a composite layer having both polysilicon and silicon oxide can be effectively removed to obtain a resulting surface having a good profile. As a result, the formation of a polysilicon bridge caused by detachments of polysilicon particles in subsequent manufacturing processes can be prevented.

Abstract: A method for improving the quality of a deposited layer over a silicon substrate in a selective deposition where the silicon substrate has a native oxide layer thereon. A plasma reaction using a halogen compound as a reactive agent is performed so that the native oxide layer is transformed into a silicon halide layer and then removed at low pressure. A layer of the desired material is formed over the native oxide free silicon substrate surface by selective deposition.

Abstract: According to a fabrication method of a semiconductor device, differing areas of metal interconnect layers 102a and 102b are formed on top of interlayer base layer 101. An HSQ layer 103 is then deposited over them. A plasma SiO2 is then deposited on top of the HSQ film 103. Afterwards, the top surface of the plasma SiO2 film 104 is subjected to the CMP process so that its surface can be smoothed. A photoresist film 105 is deposited on top of the SiO2 film 104 and then patterned for a subsequent step of making via holes. Afterwards, the insulation film 104 and HSQ film 103 are selectively etched so as to dig via holes 110 so that the bottoms 120 of the via holes 110 respectively end at the top surfaces of the interconnect layers 102a and 102b. This etching is performed using a mixture of a fluorine-based gas and a hydrogen-based gas.

Abstract: A method for forming a bit line of a DRAM memory array is disclosed. The method comprises the steps of: forming an interlayer dielectric over the DRAM memory array; etching the interlayer dielectric to form trenches in the interlayer dielectric, the trenches collectively forming a bit line pattern and having tapered side walls; and depositing a conductive material into the trenches to form the bit line.

Abstract: To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.

Abstract: The prevention of the formation of undesired defects formed during the etching of etched metal interconnect lines on an integrated circuit during an integrated circuit manufacturing process that involves laying down on a semiconductor wafer a thin film such as an anti-reflective coating (ARC) on a layer of metal to be patterned into the metal interconnects of the individual integrated circuits. To do this the anti-reflective coating layer is covered with an oxide layer prior to applying and patterning subsequent photoresist. The specific metalization layer disclosed can be of aluminum, copper or copper-aluminum alloy. The ARC as disclosed is a nitride layer, such as titanium nitride. The oxide may be formed on the ARC in a number of known ways and may be etched subsequently alone or in combination with the underlying ARC and metal after subsequent photoresist deposit upon the oxide layer.

Abstract: There is provided a method of manufacturing a semiconductor device having a MOS transistor formed on a silicon substrate, and a stacked capacitor constituted by an information storage electrode provided above the MOS transistor through an insulating interlayer and a counter-electrode separated from the information storage electrode due to the presence of a capacitor insulating film. In this method, the capacitor is formed by adding an impurity in a silicon oxide film which is formed on the insulating interlayer and used to shape the information storage electrode, and performing etching by using a chemical solution containing phosphoric acid, sulfuric acid, nitric acid, or a solution mixture thereof, or a chemical solution containing a solution mixture of an aqueous ammonia solution and a hydrogen peroxide solution to selectively remove the silicon oxide film added with the impurity.

Abstract: A method to improve silicon oxynitride when used as an etching stop for silicon oxide plasma etching, by nitridizing with a nitrogen plasma, in the fabrication of an integrated circuit is achieved. The method is applied to forming etch stopping silicon oxynitride spacers for MOS transistors and for forming etch stopping silicon oxynitride for dual damascene interconnects. A semiconductor substrate is provided wherein devices and features have been formed in and on the semiconductor substrate. A silicon oxynitride layer is deposited overlying the semiconductor substrate. The silicon oxynitride layer is nitridized. An interlevel dielectric oxide layer is deposited overlying surface of the silicon oxynitride layer. The interlevel dielectric oxide layer is etched through to the silicon oxynitride layer where defined by photolithography and wherein the silicon oxynitride layer acts as an etching stop.

Abstract: Methods of forming contact openings and methods of controlling the degree of taper of contact openings are described. In one implementation, a layer is first etched through a contact mask opening using a first set of etching conditions. The etching conditions provide a first degree of sidewall taper from vertical, if etching completely through the layer. After the first etching, the layer is second etched through the contact mask opening using a second set of etching conditions. The second set of etching conditions provide a second degree of sidewall taper from vertical, if etching completely through the layer. The second degree of sidewall taper is different from the first degree of taper. In another embodiment, a material through which a contact opening is to be etched to a selected depth is formed over a substrate. A masking layer having an opening therein is formed over the material.

Abstract: A manufacturing method for a micromechanical device. In this method, a substrate is prepared with a plating base area to accommodate an anchoring region, and an adhesive layer is formed and structured on the substrate, so that the anchoring region is formed in the plating base area in the form of a quasi-insular region in a recess of the adhesive layer. The quasi-insular region is connected to the adhesive layer outside of the plated based area by at least one thin web. A mask is formed on the adhesive layer and structured so that the anchoring region and an overgrowth region adjacent to the anchoring region remain unmasked. An electroplated layer is deposited on the unmasked anchoring region so that the overgrowth region is overgrown, and the mask and the part of the adhesive layer that has not been overgrown are removed.

Abstract: Method and apparatus for plasma etching both metal and inorganic dielectric layers in a single chamber during deep sub-micron semiconductor fabrication. Fluorine based chemistries, or a mixture of fluorine and chlorine based chemistries, are used to etch the inorganic dielectric layer. A switch is then made to chlorine based chemistries, within the same etching chamber, which are utilized to etch the metal layer. Overetching may also be performed with chlorine based chemistries to clear any residuals.

Abstract: A process for controlling the etch of a silicon dioxide layer at a high etch rate and high selectivity with respect to silicon nitride, particularly in a multilayer structure, by maintaining various portions of the etch chamber at elevated temperatures.

Abstract: A semiconductor device fabrication method in which a conductive interconnect is formed over a semiconductor substrate. First and second dielectric films are formed over the interconnect. A first patterning layer is formed over the second dielectric. A via opening is then formed in the first patterning layer and a second patterning layer is formed over the first patterning layer. A trench opening is defined in the second patterning layer. A first portion of the second dielectric film exposed by the trench opening is removed to define a via pattern. A portion of the first patterning layer exposed by the second patterning layer is then removed to expose a second portion of the second dielectric film, which is then removed to define a trench portion of a dual inlaid opening in the second dielectric. A portion of the first dielectric film defined by the via pattern is then removed to expose the conductive region.

Abstract: A method for reducing RC delay by forming an air gap between conductive lines. A sacrificial layer is formed over a semiconductor structure, filling the gaps between conductive lines on the semiconductor structure. An air bridge layer is formed over the sacrificial layer. The semiconductor structure is exposed to an oxygen plasma, which penetrates through pores in the air bridge layer to react with the sacrificial layer, whereby the sacrificial layer is removed through the air bridge layer. The sacrificial layer and/or the air bridge layer comprise buckminsterfullerene. The air bridge layer can comprise buckminsterfullerene incorporated in an inorganic spin-on material. The buckminsterfullerene reacts with the oxygen plasma and is removed to form a porous air bridge layer. Then the oxygen species from the plasma penetrate the porous air bridge layer to react with and remove the sacrificial layer.

Abstract: The invention describes a method for fabricating an inter-layer dielectric layer. In this method, a plurality of first polysilicon lines, a first inter-layer dielectric layer, and a plurality of second polysilicon lines are formed in sequence on the substrate. A second inter-layer dielectric layer is formed between the plurality of second polysilicon lines and entirely covers the plurality of second polysilicon lines. Afterwards, a spin-on glass layer is formed on the second inter-layer dielectric layer, and then, while using the upper surfaces of the second polysilicon lines as etch end points, the spin-on glass layer and the second inter-layer dielectric layer are etched back to entirely remove the spin-on glass layer and partially remove the second inter-layer dielectric layer over the second polysilicon lines. Subsequently, a cover layer is formed to cover the second polysilicon lines and the remainder of the inter-layer dielectric layer. Finally, an oxide layer is formed to cover the resulting structure.

Abstract: In one aspect, the invention encompasses a semiconductor processing method comprising contacting a surface with a liquid solution comprising at least one fluorine-containing species and a temperature of at least about 40° C. In another aspect, the invention encompasses a method of passivating a silicon-comprising layer comprising contacting the layer with a liquid solution comprising hydrogen fluoride and a temperature of at least about 40° C. In yet another aspect, the invention encompasses a method of forming hemispherical grain polysilicon comprising: a) forming a layer comprising substantially amorphous silicon over a substrate; b) contacting the layer comprising substantially amorphous silicon with a liquid solution comprising fluorine-containing species and a temperature of at least about 40° C.; c) seeding the layer comprising substantially amorphous silicon; and d) annealing the seeded layer to convert at least a portion of the seeded layer to hemispherical grain polysilicon.

Abstract: Disclosed is a process for removing doped silicon dioxide from a structure selectively to undoped silicon dioxide. A structure having both doped and undoped silicon dioxide regions is exposed to a high density plasma etch having a fluorinated etch chemistry. Doped silicon dioxide is preferably removed thereby at a rate 10 times or more greater than that of undoped silicon dioxide. The etch is conducted in a chamber having an upper electrode to which a source power is applied and a lower electrode to which a bias power is applied sufficient to generate a power density on a surface of the structure such that the source power density is in a range less than or equal to about 1000 W per 200-mm diameter wafer surface. The high density plasma etch has an ion density not less that about 109 ions/cm3. A variety of structures are formed with the etch process, including self-aligned contacts to a semiconductor substrate.

Abstract: A method for fabricating an interconnect structure by a dual damascene process is described, in which a first low dielectric constant material is formed on a substrate, followed by forming a gradient silicon oxy-nitride layer on the first low dielectric constant. A second low dielectric constant layer is further formed on the gradient silicon oxy-nitride layer. A trench line is then formed in the second low dielectric constant material using the gradient silicon oxy-nitride layer as an etch-stop, followed by forming a via under the trench line.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a conductive structure over the substrate, the conductive structure comprised of an oxygen-sensitive conductor; forming a layer of dielectric material over the conductive structure (step 306 of FIG. 1); forming a photoresist layer over the layer of the dielectric material (step 308 of FIG. 1); patterning the layer of the dielectric material (step 308); removing the photoresist layer after patterning the layer of the dielectric material (step 312 of FIG. 1); and subjecting the semiconductor wafer to a plasma which incorporates the combination of hydrogen or deuterium and a fluorine-containing mixture which is comprised of a gas selected from the group consisting of: CF4, C2F6, CHF3, CFH3 and other fluorine-containing hydrocarbon (step 313 of FIG. 1).

Abstract: A method of fabricating an integrated circuit, and an integrated circuit so fabricated, is disclosed. A silicon dioxide layer (14) that is doped with both boron and phosphorous, typically referred to as BPSG, is used as a planarizing layer in the integrated circuit structure, above which conductive structures (46, 52, 54) are disposed. A silicon nitride layer (30) is in place below the BPSG layer (14), and serves as a barrier to the diffusion of boron and phosphorous from the BPSG layer (14) during high temperature processes such as reflow and densification of the BPSG layer (14) itself. Contact openings (PC, BLC, CT) are etched through the BPSG layer (14) and the silicon nitride layer (30) using a two-step etch process.

Abstract: A method is provided for directly measuring the source/drain resistance of a metal oxide semiconductor (MOS) device. Embodiments include partially deconstructing a typical MOS device by removing its gate and gate oxide from the substrate, as by etching, while preserving its gate sidewall spacer (typically silicon nitride). A sacrificial oxide spacer is formed on the nitride spacer, as by anisotropically etching a deposited oxide layer, and the area surrounding the sacrificial oxide spacer is filled with a layer of nitride. The sacrificial oxide spacer is then selectively etched to expose a portion of the main surface of the substrate and leave the nitride spacer and layer, thus creating a location near the edge of a source/drain region for a metal contact to be formed, as by chemical vapor deposition (CVD).

Abstract: The invention pertains to dielectric films for the production of microelectronic devices. A relatively stabile fluorinated silicate glass film is produced by depositing a fluorinated silicate glass film onto a substrate and then exposing the fluorinated silicate glass film to electron beam radiation. The electron beam exposing step is conducted by overall exposing the dielectric layer with a wide, large beam of electron beam radiation from a large-area electron beam source.

Abstract: The invention has two embodiments for forming a contact plug having large nail shaped landing pad. The large pad areas increase the overlay tolerances. The first embodiment comprises forming first 20 and second 24 insulating layers over a semiconductor structure. A first photoresist layer 28 with a first opening is formed over the second insulating layer 24. The second insulating layer 24 is isotropically etched using an etchant with a high selectivity thereby forming a disk shaped opening 26A. The disk shaped opening is used to define the large nail shaped landing pad. The first insulating layer 20 is etched using a dry etch thereby forming a nail shaped contact opening 26. The opening is filled with polysilicon to form the nail shaped conductive plug 36. The second embodiment begins by forming a first insulating layer 40 over a semiconductor structure. A first photoresist layer 44 with a first opening is formed over the first insulating layer 24.

Abstract: A method for use in the fabrication of semiconductor devices includes forming a titanium nitride film and depositing a silicon hard mask over the titanium nitride film. The silicon hard mask is used to pattern a titanium nitride interconnect from the titanium nitride film and the silicon hard mask is also used as a contact etch stop for forming a contact area. In forming the interconnect, the silicon hard mask is dry etched stopping selectively on and exposing portions of the titanium nitride film and the exposed portions of the titanium nitride film are etched resulting in the titanium nitride interconnect. In using the silicon hard mask as a contact etch stop, an insulating layer is deposited over the silicon hard mask and the insulating layer is etched using the silicon hard mask as an etch stop to form the contact area. The silicon hard mask is then converted to a metal silicide contact area. Interconnects formed using the method are also described.

Abstract: The present invention provides a bonding pad on a semiconductor chip such that peeling of bonding pads during interconnection in the packaging process is avoided. The bonding pad is used to electrically connect an integrated circuit in the semiconductor chip with an external circuit. The semiconductor chip comprises a first dielectric layer positioned in a predetermined area on the surface of the semiconductor chip, a second dielectric layer positioned on the surface of the semiconductor chip outside the predetermined area wherein the first dielectric layer is harder than the second dielectric layer, and a bonding pad positioned on the first dielectric layer for electrically connecting anintegrated circuit (IC) in the semiconductor chip with an external circuit.