Abstract: A method of fabricating a self-aligned contact window includes forming an undoped dielectric layer on a substrate having a least gate structure. The dopants are implanted into a pre-determined region of the undoped dielectric layer and the dielectric layer with the dopants is then removed. A self-aligned contact is therefore completed.

Abstract: A plasma etching method is provided, which forms a penetrating hole with a size as small as approximately 0.3 .mu.m or less and a high aspect ratio in a doped or undoped silicon dioxide film covered with a patterned masking film. This method is comprised of a step of forming a masking film with a window on a silicon dioxide film to be etched, and a step of selectively etching the silicon dioxide film through the window of the masking film using a fluorocarbon-based etching gas and a plasma in a reaction chamber, thereby forming a penetrating hole in the silicon dioxide film. During the step of selectively etching the silicon dioxide film, an etching condition is adjusted in such a way that a fluorocarbon polymer film having a ratio of carbon to fluorine (i.e., a C/F ratio) ranging from 1.1 to 1.8 is deposited on the masking film. The masking film preferably has a thickness of approximately 1 .mu.m or less. It is preferred that this method is carried out using a surface-wave plasma etching apparatus.

Abstract: A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90.degree. from horizontal, with no bowing or notching.

Abstract: A photo-resist mask is removed from an inter-level insulating structure by using plasma produced from N.sub.x H.sub.y gas, and the plasma does not make an organic insulating layer forming part of the inter-level insulating structure hygroscopic, because SiCH.sub.3 bond is never replaced with Si--OH bond during the removal of the photo-resist mask.

Abstract: The dimensional precision and accuracy of sub-micron-sized, in-laid metallization patterns, e.g., of electroplated copper or copper alloy, formed in the surface of a dielectric layer are significantly improved by utilizing a layer of a sputter-resistant mask material formed of a high atomic mass metallic element or compound thereof during reactive ion etching of the dielectric layer by a fluorine-containing plasma for forming sub-micron-dimensioned recesses therein. After filling of the recesses, planarization, as by CMP, is conducted wherein excess thickness of the metal layer is removed, together with underlying portions of the sputter-resistant mask layer.

Abstract: A process for removal of residual silicon oxide hardmask used to etch vias in low-k organic polymer dielectric layers is described. The hardmask deteriorates by developing an angular aspect or faceting along the pattern edges when used to etch organic polymer layers in an oxygen/inert gas plasma in a high density plasma etcher. In addition the deterioration of the hardmask during organic polymer etching causes a significant degradation of surface planarity which would result in via-to-via shorts when a second metal layer is patterned over it if the hardmask were left in place. The residual hardmask is selectively removed immediately after the via etch by a soft plasma etch which restores surface planarity and removes via edge facets. The plasma etch has a high selectivity of oxide-to-organic polymer so that the surface irregularities are not transferred to the polymer surface and the exposed metal surface at the base of the via is also unscathed.

Abstract: The present invention relates to the fabrication of semiconductor devices and more particularly to a new method for avoiding abnormal via holes when Spin On Glass, SOG, is used as a means of planarizing an interlevel metal interconnect structure. The invention addresses the problem of locations of micro bubbles in a SOG layer that can lead to seams, voids and a ragged surface topology which, in turn, can make it very difficult to eventually etch well formed via holes at such locations. The invention details a new etch back method that solves the above problem by properly smoothing the micro bubble locations. This new method includes a sequence of anisotropic and isotropic etching steps that are used to partially etch back the cured SOG layer in order to achieve a planarized surface while also smoothing the micro bubble locations in the cured SOG layer.

Abstract: The present invention is directed to methods of creating a cavity to contain an interconnect leading to a location within a substrate. The substrate has a first dielectric layer of a first etch rate over the location, and a semiconductor device containing the interconnect. One of the methods includes the steps of: forming a second dielectric layer on the first dielectric layer wherein the second dielectric layer has a second etch rate that is slower than the first etch rate, forming a photoresist layer on the second dielectric layer and etching into the first and second dielectric layers to form the cavity leading to the location. The second dielectric layer acts as a profile guiding layer to form a plug and runner simultaneously in a single etching step while controlling relative size of the plug and runner.

Abstract: A chemical mechanical polishing step is performed to expose a silicon/silicon dioxide interface on a surface situated on a semiconductor substrate. The semiconductor substrate is dipped in a solution of about 200 parts of deionized water, about 1 part of hydrofluoric acid, and at least 5 parts tetramethyl ammonium hydroxide. The exposed silicon/silicon dioxide interface is then contacted with an organic carboxylic acid surfactant having a critical micelle concentration greater than or equal to 10.sup.-7 m/l and having a pH from about 2.2 to about 7. Lastly, the exposed silicon/silicon dioxide interface is rinsed in deionized water or sulfuric acid to remove silicon dioxide particles from the exposed silicon/silicon dioxide interface, leaving a very clean, low particulate surface on both the silicon dioxide and silicon portions thereof, with little or no etching of the silicon portion.

Abstract: A method for creating via holes in a chip or a plurality of chips of a wafer is disclosed. The method is performed by using a pre-patterned transparent mask on the back of the chip or chips, and bombarding the chip(s) through the positioning holes on the transparent mask that correspond to the pre-formed pattern, with accelerated particles. According to this method, via holes can be created from the back of the chip(s) without interfering with the existing IC structure of the chip(s). The present method is highly efficient because a number of via holes can be formed simultaneously by using a large pre-pattered mask to cover the entire wafer. In addition, the present method is cost-effective because no precision apparatus is required.

Abstract: A method of forming local interconnects uses a dual damascene process. The process comprises the steps of first providing a substrate, and then forming a first insulating layer over the substrate. Then, a pillar-shaped second insulating layer is formed over the first insulating layer. Thereafter, a first conductive layer is formed over the first insulating layer and the second insulating layer, and then a third insulating layer is formed over the first conductive layer. In the subsequent step, a portion of the third insulating layer and the first conductive layer is polished away using a chemical-mechanical polishing operation, stopping at the surface of the second insulating layer. Next, a fourth insulating layer is formed over the third insulating layer, the second insulating layer and the first conductive layer, wherein the fourth insulating layer and the second insulating layer are made from the same material.

Abstract: A plasma etching method includes forming polymer material over at least some internal surfaces of a plasma etch chamber and forming polymer material over at least some surfaces of a semiconductor wafer received within the plasma etch chamber. Substantially all polymer material is plasma etched from the chamber internal surfaces while at least some polymer material remains on the wafer. In another aspect, a semiconductor wafer is positioned on a wafer receiver within a plasma etch chamber. A photoresist layer has previously been formed thereon and has openings formed therethrough. First plasma etching is conducted through openings formed in the photoresist layer with a gas comprising carbon and a halogen to form openings in material on the wafer. A first polymer comprising carbon and the halogen forms over at least some internal surfaces of the plasma etch chamber during the first plasma etching.

Abstract: The invention comprises processing deposited oxide and grown oxide materials. In one implementation, a substrate is provided to have outwardly exposed grown oxide material and having deposited oxide material. The grown oxide material is etched substantially selective relative to the deposited oxide material. In another considered aspect, a silicon surface is thermally oxidized to form substantially undoped silicon dioxide over a substrate. A substantially undoped silicon dioxide layer is chemical vapor deposited over the substrate, with at least some of the thermally grown silicon dioxide being outwardly exposed. The exposed thermally grown silicon dioxide layer is vapor etched substantially selective relative to the deposited silicon dioxide layer using an etch chemistry comprising substantially anhydrous HF and an organic primer.

Abstract: The invention includes methods of patterning substrates. In one implementation, an electrically conductive etch mask layer is formed over a substrate. A resist layer, for example photoresist, is formed over the etch mask layer. The etch mask layer is etched into through an opening formed in the patterned resist. The etching preferably comprises dry etching within a dual source, high density plasma etcher using an oxygen containing gas. Substrate layers beneath the electrically conductive base layer are preferably etched through one or more openings formed in the conductive layer at least in part by the preferred dry etching. The etch mask layer and resist are ultimately removed from the substrate.

Abstract: An etching method used in the high density plasma etching system to etch a silicon oxide dielectric layer to form openings of different depths. The method uses a mixture of C.sub.4 H.sub.8, CH.sub.2 F.sub.2, and Ar as an etching gas source to etch the silicon oxide dielectric layer, forming a plurality of openings of a first depth. A mixture of C.sub.4 H.sub.8, CO, and Ar is used as an etching gas source to etch the silicon oxide dielectric layer exposed by the first opening, so that the opening is deepened to the second depth. Using a mixture of C.sub.4 H.sub.8, CH.sub.2 F.sub.2, CO, and Ar as the etching gas source, the silicon oxide dielectric layer exposed by the opening is etched, so that the openings are deepened to the third depth and the fourth depth.

Abstract: In accordance with the present invention, there is provided a method for fabricating a contact on an integrated circuit, such as a DRAM. The method includes the following steps. A gate stack is formed on the integrated circuit. A spacer is formed on sidewalls of the gate stack. An insulating film is formed on the integrated circuit. The insulating film is planarized. Finally, a gate contact opening is formed through the planarized insulating film. In one embodiment, the gate contact opening is formed by removing the insulator, spacer and insulating film by etching. In this embodiment, the insulator, spacer and insulating film are etched at substantially similar rates. As a result, the integrated circuit is tolerant of mask misalignments, and does not over-etch field oxide or create silicon nitride slivers. In another embodiment, the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit.

Abstract: A method of forming a plurality of contact holes 70 in a semiconductor wafer uses a single step. The semiconductor wafer includes a dielectric layer 69 overlying a silicon substrate 51, a silicon nitride layer 67a, and a silicon oxynitride layer 63c. First, a photoresist 68 layer is developed on the dielectric layer. Prior to forming the dielectric layer, the silicon oxynitride layer is formed overlying a first conductive layer, and the silicon nitride layer is formed overlying a second conductive layer. Second, an etching step is performed to etch through the silicon oxynitride layer, the silicon nitride layer, a portion of the dielectric layer above the silicon oxynitride layer, and the silicon nitride layer to expose the silicon substrate 51, the first conductive layer 63a, and the second conductive layer 67c. The etching recipe includes a first chemistry and a second chemistry. The first chemistry includes C.sub.2 F.sub.6, C.sub.4 F.sub.8, CH.sub.3 F, and Ar.

Abstract: Methods of forming contact openings and methods of controlling the degree of taper of contact openings are described. In one implementation, a layer is first etched through a contact mask opening using a first set of etching conditions. The etching conditions provide a first degree of sidewall taper from vertical, if etching completely through the layer. After the first etching, the layer is second etched through the contact mask opening using a second set of etching conditions. The second set of etching conditions provide a second degree of sidewall taper from vertical, if etching completely through the layer. The second degree of sidewall taper is different from the first degree of taper. In another embodiment, a material through which a contact opening is to be etched to a selected depth is formed over a substrate. A masking layer having an opening therein is formed over the material.

Abstract: A method for forming a CMOS image sensor spacer structure. A polysilicon gate electrode is formed on a substrate; a thin layer of first dielectric is deposited over the exposed surfaces of the gate electrode and the top of the substrate. Next a second layer of dielectric is deposited after which etching is performed to create the electrode spacer. The deposited second layer of dielectric serves as an etch stop and prevents damage to the substrate surface between spacers of the gate electrodes. An alternate method uses a thin ply layer as the stop layer and, in so doing, source/drain damage caused by the white pixel problem.

Abstract: A method for etching a silicon layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a blanket silicon layer. There is then formed upon the blanket silicon layer a blanket silicon containing hard mask layer, where the blanket silicon containing hard mask layer is formed from a silicon containing material chosen from the group of silicon containing materials consisting of silicon oxide materials, silicon nitride materials, silicon oxynitride materials and composites of silicon oxide materials, silicon nitride materials and silicon oxynitride materials. There is then formed upon the blanket silicon containing hard mask layer a patterned photoresist layer. There is then etched through a first plasma etch method the blanket silicon containing hard mask layer to form a patterned silicon containing hard mask layer while employing the patterned photoresist layer as a first etch mask layer.

Abstract: The present invention discloses a dry etching method using a high density plasma, in which a fluorocarbon gas, whose fluorine to carbon ratio is less than 2:1, is used. Such arrangement provides improved etching selectivity ratios to the resist film. The adding of an inert gas and oxygen to such a fluorocarbon gas provides further improved etching selectivity ratios and improved etching rates.

Abstract: A method for increasing chip yield by reducing black silicon deposition in accordance with the present invention includes the steps of providing a silicon wafer suitable for fabricating semiconductor chips, depositing a first layer over an entire surface of the wafer, removing a portion of the first layer to expose a region suitable for forming semiconductor devices and etching the wafer such that a remaining portion of the first layer prevents redeposition of etched material on the wafer. A semiconductor assembly for reducing black silicon deposition thereon, includes a silicon wafer suitable for fabricating semiconductor chips, the wafer having a front surface for forming semiconductor devices, a back surface and edges. A deposited layer is formed on the wafer for covering the back surface and the edges such that redeposition of silicon on the back surface and edges of the wafer during etching is prevented.

Abstract: A method of manufacturing a semiconductor device, including the steps of: cooling a semiconductor wafer to a predetermined temperature, the semiconductor wafer being mounted on a stage provided with cooling means and having a thin oxide film on a surface thereof; supplying energy to gas containing hydrogen and water vapor to excite the gas into a plasma state; adding nitrogen fluoride downstream into a flow of the gas in the plasma state; and introducing a flow of the gas, including the nitrogen fluoride, to the semiconductor wafer to etch the thin oxide film while maintaining the semiconductor wafer at the predetermined temperature.

Abstract: A method for fabricating a semiconductor device according to the present invention includes the steps of: forming an oxide film on a substrate having a silicon region at least on the surface thereof; defining a resist pattern on the oxide film; placing the substrate on an electrode provided inside a reaction chamber of a plasma etching apparatus, and etching the oxide film by using plasma generated from a gas including a fluorocarbon gas with a bias voltage applied to the substrate; and removing fluorine from the reaction chamber by generating oxygen plasma inside the reaction chamber with substantially no bias voltage applied to the substrate.

Abstract: A method for forming a contact hole in an active matrix substrate, the method comprising steps of: (a) depositing an insulating film covering a first electrode provided on a substrate and the substrate; (b) forming a contact hole by patterning said insulating film by means of dry etching; and (c) forming a second electrode, and contacting the second electrode with the first electrode; wherein in the step (b) after forming a contact hole by dry etching, a surface treatment by plasma etching or reactive ion etching with oxygen gas under a condition in which a pressure P is in a range of 100 Pa to 400 Pa is performed.

Abstract: A method used during the formation of a semiconductor device including a semiconductor wafer assembly comprises a first step of forming a first mask over a front of the wafer assembly such that a portion of first and second layers are uncovered by the mask. Next, the uncovered portion of the second layer is etched to form at least one sidewall in the second layer. A film is formed over the sidewall and, subsequent to forming the film, at least a portion of a third layer on a back of the wafer assembly is removed. During this removal, the sidewall is protected by the film. After removing the third layer, a second mask is formed over a portion of the first and second layers and the first layer is exposed.

Abstract: A method for improving the patterning process of a conductive layer using a dual-layer cap of oxynitride and silicon nitride. The oxynitride layer acts as a BARC (Bottom Anti-Reflective Coating) to improve photolithography process performance. The oxynitride is formed by plasma-enhanced chemical vapor deposition.

Abstract: A method of patterning a polysilicon gate using an oxide hard mask using a novel 4 step insitu etch process. All 4 etch steps are performed insitu in a polysilicon high density plasma (TCP--transformer coupled plasma) etcher. A multi-layered semiconductor structure 35 (FIG. 1) is formed comprising: a substrate 10, a gate oxide layer 14, a polysilicon layer 18, a hard mask layer 22, and a bottom anti-reflective coating (BARC) layer 26 and a resist layer 30. The 4 step insitu etch process comprises:a) in STEP 1, etching the bottom anti-reflective coating (BARC) layer by flowing HBr and O.sub.

Abstract: A process is disclosed for forming vias and trenches in two separate dielectric layers, which may be separated by an etch stop, while avoiding the etch mask stress complicated resist masks, or high aspect ratio openings of the prior art. A first dielectric layer 10 is formed over an integrated circuit structure 2 on a semiconductor substrate, and a thin second dielectric layer 20 is formed over the first dielectric layer. A first resist mask, is formed over the second dielectric layer, and the first and second dielectric layers are etched through to form one or more vias 18, 28 extending through both the first and second dielectric layers. The first resist mask is then removed and a third dielectric layer 70, having different etch characteristics than the second dielectric layer, is deposited over the structure.

Abstract: The practice of forming self-aligned contacts in MOSFETs using a silicon nitride gate sidewall and a silicon nitride gate cap has found wide acceptance, particularly in the manufacture of DRAMs, where bitline contacts are formed between two adjacent wordlines, each having a nitride sidewall. The contact etch requires a an RIE etch having a high oxide/nitride selectivity. Current etchants rely upon the formation of a polymer over nitride surfaces which enhances oxide/nitride selectivity. However, for contact widths of less than 0.35 microns, as are encountered in high density DRAMs, the amount of polymer formation required to attain a high selectivity causes the contact opening to close over with polymer before the opening is completely etched. This results in opens or unacceptably resistive contacts. On the other hand, if the etchant is adjusted to produce too little polymer, the nitride cap and sidewalls are thinned or etched through, producing gate to source/drain shorts.

Abstract: An interconnection layer 3 in a floating state and an interlayer insulating film 6 are formed on a semiconductor substrate. A connection hole 4 penetrating the interlayer insulating film and the interconnection layer is formed by dry etching with fluorocarbon. Filled in the connection hole is a conductive member 5 which is electrically connected to the interconnection layer. Accordingly, an improved method for manufacturing a semiconductor device offering a reduced contact resistance even for an extremely small contact hole is obtained.

Abstract: In this invention is described a process for controlling the etching of side wall spacers to a prescribed width. A gaseous mixture of an inert gas, CF.sub.4 and CHF.sub.3 in a prescribed ratio, under pressure and with a plasma is flowed within a RIE chamber. A magnetic field in parallel with the surface of the wafer being etched is used to control the oxide/silicon selectivity. The shape and width of the side wall spacers are controlled by controlling the selectivity. Uniformity of the shape of side wall spacers over the surface of a wafer is also produced by the magnetic field which induces a higher etch rate at the edge of the wafer where the oxide coating is the thickest.

Abstract: A microwave-activated plasma process for etching dielectric layers (20) on a substrate (25) with excellent control of the shape and cross-sectional profile of the etched features (40), high etch rates, and good etching uniformity, is described. A process gas comprising (i) fluorocarbon gas (preferably CF.sub.4), (ii) inorganic fluorinated gas (preferably NF.sub.3), and (iii) oxygen, is used. The process gas is introduced into a plasma zone (55) remote from a process zone (60) and microwaves are coupled into the plasma zone (55) to form a microwave-activated plasma. The microwave-activated plasma is introduced into the process zone (60) to etch the dielectric layer (20) on the substrate (25) with excellent control of the shape of the etched features.

Abstract: A method for fabricating trench isolation structures using the reverse mask is described. The method of using a reverse mask to fabricate trench isolation structures includes providing a semiconductor substrate having a first trench and a second trench in the substrate. The first trench has a width smaller than a fixed value, while the second trench has a width larger than the fixed value, the fixed value being, for example, about 0.7 .mu.m. Thereafter, a conformal insulating layer is formed over the first trench and the second trench. Next, a reverse mask layer is formed over the conformal insulating layer, and then the reverse mask layer is patterned. The reverse mask layer is patterned selectively. For example, only the region directly above the second trench is covered by the reverse mask. The region directly above the first trench is exposed.

Abstract: The present disclosure pertains to a method for plasma etching a semiconductor patterning stack. The patterning stack includes at least one layer comprising either a dielectric-comprising antireflective material or an oxygen-comprising material. In many instances the dielectric-comprising antireflective material will be an oxygen-comprising material, but it need not be limited to such materials. In one preferred embodiment of the method, the chemistry enables the plasma etching of both a layer of the dielectric-comprising antireflective material or oxygen-comprising material and an adjacent or underlying layer of material. In another preferred embodiment of the method, the layer of dielectric-comprising antireflective material or oxygen-comprising material is etched using one chemistry, while the adjacent or underlying layer is etched using another chemistry, but in the same process chamber.

Abstract: A method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as an plasma treatment, on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densified surface of the dielectric layer is able to efficiently prevent the occurrence of poisoned trenches and vias caused by the outgassing phenomena.

Abstract: In a method for manufacturing a semiconductor device, an insulating layer is formed on a refractory metal layer, and a contact hole in the insulating layer by a dry etching process using an etching gas includes one of:a mixture gas of fluorocarbon and hydrogen;a mixture gas of hydrofluorocarbon and hydrogen;a gas of hydrofluorocarbon; anda fluorocarbon gas except for CF.sub.4.

Abstract: Contact holes through a dielectric are formed by forming a layer of polysilicon having a thickness between 0.02 um and 0.15 um inclusive on the dielectric, forming a layer of resist having a thickness between 0.4 um and 0.6 um inclusive on the layer of polysilicon, making a mask of the layer of resist, using it to form a mask in the layer of polysilicon and etching contact holes in the dielectric by exposing it to etching gasses through the apertures in the polysilicon mask. When the dielectric includes a layer of oxide adjacent the polysilicon mask and a layer of nitride between it and elements of the device, the resist mask is removed prior to etching the contact hole and a gas mixture of: C.sub.4 F.sub.8 ; one of Ar, H, F; CO; CF.sub.4 or C.sub.2 F.sub.6 is used.

Abstract: The invention comprises methods of forming contact openings and methods of forming contacts. In but one implementation, an inorganic antireflective coating material layer is formed over an insulating material layer. A contact opening is etched through the inorganic antireflective coating layer and into the insulating layer. Insulative material within the contact opening is etched and a projection of inorganic antireflective coating material is formed within the contact opening. The inorganic antireflective coating material is etched to substantially remove the projection from the contact opening. The preferred etching to remove the projection is facet etching, most preferably plasma etching. The preferred inorganic antireflective coating material is selected from the group consisting of SiO.sub.x where "x" ranges from 0.1 to 1.8, SiN.sub.y where "y" ranges from 0.1 to 1.2, and SiO.sub.x N.sub.y where "x" ranges from 0.2 to 1.8 and "y" ranges from 0.01 to 1.0, and mixtures thereof.

Abstract: A method for forming contacts with vertical sidewalls, high aspect ratios, improved salicide and photoresist etch selectivity at submicron dimensions. In one currently preferred embodiment, an opening is formed in a dual oxide layer by etching the undoped oxide layer at a first rate and then etching the doped oxide layer at a second rate. The etch process is performed in a low density parallel plate reactor. The process parameters of the etch are fixed in ranges which optimize the etch process and allow greater control over the critical dimensions of the opening. For example, the oxide layer is etched at a pressure in the range of approximately 100-300 mTorr and with an etch chemistry having a CHF.sub.3 :CF.sub.4 gas flow ratio in the range of approximately 3:1-1:1, respectively.

Abstract: A method for fabricating a semiconductor device is characterized by using a mixture chemical comprising ozone gas, anhydrous HF gas and deionized water vapor as an etchant for etching an oxide- and silicon-exposed wafer, whereby the etch selection ratio of oxide to silicon can be controlled according to necessity, so that the production yield and reliability of semiconductor device are improved. During etching of a wafer with exposed thermal oxide and exposed silicon, the etch rate ratio of oxide to silicon is controlled by changing the relative flow rates of the ozone gas, anhydrous HF gas and deionized water vapor.

Abstract: A semiconductor processing method of forming a contact opening to a substrate includes forming at least one conductive line over the substrate adjacent a substrate contact area to which electrical connection is to be made. A first oxide layer is formed over the substrate to cover at least part of the contact area. A second oxide layer is formed over the first oxide layer and is formed from a different oxide than the first oxide layer. A first etch is conducted over the contact area and through the second oxide layer to a degree sufficient to leave at least a portion of the first oxide layer over the contact area. A second etch is conducted to a degree sufficient to remove substantially all of the first oxide layer left behind and to remove a desired amount of the second oxide layer laterally outwardly of the contact area.

Abstract: An improved etching method allowing the formation of a silicon nitride film with an adequate film thickness at the sidewall portion of a pattern is disclosed. A silicon nitride film formed to cover a stepped pattern is dry-etched, employing plasma of mixed gases containing CH.sub.2 F.sub.2 and O.sub.2. As a result, a sidewall spacer of the silicon nitride film is formed at the sidewall of the pattern in a self-aligned manner.

Abstract: A surface having exposed doped silicon dioxide such as BPSG is cleaned with a vapor phase solution that etches thermal oxide at least one-third as fast as it etches the exposed doped silicon dioxide, resulting in more thorough cleaning with less removal of the exposed doped silicon dioxide. Specific applications to formation of container capacitors are disclosed. Preferred cleaning vapor phase solutions include about 1% water, about 5% hydrogen fluoride, and about 5% ammonias. The vapor phase solution is also useful in cleaning methods in which a refractory metal silicide is exposed to the cleaning vapor phase solution such as in cleaning prior to spacer formation or prior to a gate stack contact fill, in which case about 500 PPMV water, about 2% hydrogen fluoride, and about 2% ammonia is most preferred.

Abstract: A material containing, as a main component, an organic silicon compound represented by the following general formula:R.sup.1.sub.x Si(OR.sup.2).sub.4-x(where R.sup.1 is a phenyl group or a vinyl group; R.sup.2 is an alkyl group; and x is an integer of 1 to 3) is caused to undergo plasma polymerization or react with an oxidizing agent to form an interlayer insulating film composed of a silicon oxide film containing an organic component. As the organic silicon compound where R.sup.1 is a phenyl group, there can be listed phenyltrimethoxysilane or diphenyldimethoxysilane. As the organic silicon compound where R.sup.1 is a vinyl group, there can be listed vinyltrimethoxysilane or divinyldimethoxysilane.

Abstract: A method for forming a chlorine containing plasma etched patterned layer. There is first provided a substrate 10 employed within a microelectronics fabrication. There is then formed over the substrate a blanket target layer 12 formed of a material susceptible to etching within a second plasma employing a chlorine containing etchant gas composition. There is then formed upon the blanket target a blanket hard mask layer 14 formed of a material selected from the group consisting of silsesquioxane spin-on-glass (SOG) materials and amorphous carbon materials. There is then formed upon the blanket hard mask layer a patterned photoresist layer 16. There is then etched while employing the patterned photoresist layer as a first etch mask layer and while employing a first plasma employing a fluorine containing etchant gas composition the blanket hard mask layer to form a patterned hard mask layer.

Abstract: A self-aligned contact etch and method for forming a self-aligned contact etch. In one embodiment, the present invention performs an oxide selective etch to form an opening originating at a top surface of a photoresist layer. The opening extends through an underlying oxide layer, and terminates at a top surface of a nitride layer which underlies the oxide layer. Next, the present invention performs a nitride selective etch to extend the opening through the nitride layer to an underlying contact layer. In the present invention, the nitride selective etch causes the photoresist layer to be etched/receded. The nitride selective etch of the present invention further causes the oxide layer to be etched at and near the opening at the interface between the photoresist layer and the oxide layer. As a result, the opening is rounded at the top edge thereof when the layer of photoresist is removed.

Abstract: There is provided a dry etching method which does not contribute to earth anathermal due to the green house effect and which has a good etching characteristics. According to the present invention, the flow rates of Ar, O.sub.2, and C.sub.3 F.sub.6 supplied from gas sources 152, 154 and 156 are regulated by a mass flow controller MFC 146, 148 and 150 and valves 140, 142 and 144, respectively, to be mixed. The mixed gas is introduced onto a wafer W via a gas introducing pipe 138, a gas inlet 134, a space 130 and through holes 124a while the flow ratio of O.sub.2 to C.sub.3 F.sub.6 is set to be 0.1.ltoreq.O.sub.2 /C.sub.3 F.sub.6 .ltoreq.1.0 and the partial pressure of C.sub.3 F.sub.6 is set to be in the range of from 0.5 mTorr to 2.0 mTorr.

Abstract: An oxide etch process that is highly selective to nitride, thereby being beneficial for a self-aligned contact etch of silicon dioxide to an underlying thin layer of silicon nitride. The process uses difluoromethane (CH.sub.2 F.sub.2) for its strong polymer forming and a greater amount of trifluoromethane (CHF.sub.3) for its strong etching, and with a high diluent fraction of argon (Ar). The etch process is performed at a low pressure of about 20 milliTorr in a high-density plasma etching chamber.

Abstract: A low-temperature process for selectively etching oxide with high selectivity over silicon in a high-density plasma reactor. The principal etching gas is a hydrogen-free fluorocarbon, such as C.sub.2 F.sub.6 or C.sub.4 F.sub.8, to which is added a silane or similar silicon-bearing gas, e.g., the monosilane SiH.sub.4. The fluorocarbon and silane are added in a ratio within the range of 2 to 5, preferably 2.5 to 3. The process provides high polysilicon selectivity, high photoresist facet selectivity, and steep profile angles. Selectivity is enhanced by operating at high flow rates. Silicon tetrafluoride may be added to enhance the oxide etching rate. The process may operate at temperatures of chamber parts below 180.degree. C. and even down to 120.degree. C. The process enables the fabrication of a bi-level contact structure with a wide process window.