Abstract: A method of fabricating a semiconductor device includes the steps of: providing a semiconductor structure including a memory region and a logic region. The semiconductor structure includes a first interlayer dielectric and at least one magnetoresistive random access memory (MRAM) cell disposed on the first interlayer dielectric, and the MRAM cell is disposed in the memory region; depositing a second interlayer dielectric covering the first interlayer dielectric and the at least one MRAM cell; depositing a mask layer conformally covering the second interlayer dielectric; perform a planarization process to remove the mask layer in the memory region; after the step of performing the planarization process, removing the mask layer in the logic region.

Abstract: A MEMS resonator comprising a baseplate wafer; a piezoelectric HF-VHF resonator that comprises a monolithic piezoelectric member having at least two separate spring piezoelectric support members integrally extending therefrom, each spring piezoelectric support member having at least a rounded corner; said piezoelectric resonator being attached to the baseplate wafer by said support members; wherein said monolithic piezoelectric member comprises first and second main surfaces joined by side edges; at least one of said side edges forming an angle of between 90 and 105 degrees with one of the first and second main surfaces.

Abstract: Formulations for stripping titanium nitride hard mask and removing titanium nitride etch residue comprise an amine salt buffer, a non-ambient oxidizer, and the remaining being liquid carrier includes water and non-water liquid carrier selected from the group consisting of dimethyl sulfone, lactic acid, glycol, and a polar aprotic solvent including but not limited to sulfolanes, sulfoxides, nitriles, formamides and pyrrolidones. The formulations have a pH <4, preferably <3, more preferably <2.5. The aqueous formulations having water as liquid carrier and semi-aqueous formulation having water and non-polar aprotic solvent(s) further contain acidic fluoride. The formulations offer high titanium nitride etch rates while provide excellent compatibility towards W, AlN, AlO, and low k dielectric materials. The formulations may comprise weakly coordinating anions, corrosion inhibitors, and surfactants.

Abstract: A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

Abstract: A solar cell manufacturing method includes: forming a first amorphous semiconductor layer of one conductivity type on a main surface of a semiconductor substrate; forming an insulation layer on the first amorphous semiconductor layer; etching to remove the insulation layer and the first amorphous semiconductor layer in a predetermined first region; forming a second amorphous semiconductor layer of an other conductivity type on the insulation layer after the etching, the other conductivity type being different from the one conductivity type; and etching to remove the second amorphous semiconductor layer in a predetermined second region, wherein the etching to remove the insulation layer and the first amorphous semiconductor layer in a predetermined first region includes: applying an etching paste to the insulation layer in the predetermined first region; and etching to remove the insulation layer and the first amorphous semiconductor layer in the predetermined first region using the etching paste.

Abstract: A method of forming logic cell contacts, forming CMOS integrated circuit (IC) chips including the FETs and the IC chips. After forming replacement metal gates (RMG) on fin field effect transistor (finFET) pairs, gates are cut on selected pairs, separating PFET gates from NFET gates. An insulating plug formed between the cut gates isolates the pairs of cut gates from each other. Etching offset gate contacts at the plugs partially exposes each plug and one end of a gate sidewall at each cut gate. A second etch partially exposes cut gates. Filling the open offset contacts with conductive material, e.g., metal forms sidewall cut gate contacts and stitches said cut gate pairs together.

Abstract: A semiconductor power device of the present invention includes a first electrode and a second electrode, a breakdown voltage holding layer that is made of a semiconductor having a predetermined thickness and a predetermined impurity concentration, to which the first electrode and the second electrode are joined, and that has an active region in which carriers to generate electric conduction between the first electrode and the second electrode move, and an insulation film that is formed on the breakdown voltage holding layer and that has a high dielectric-constant portion having a higher dielectric constant than SiO2 at a part contiguous to the breakdown voltage holding layer.

Abstract: A single wafer etching apparatus and various methods implemented in the single wafer etching apparatus are disclosed. In an example, etching a silicon nitride layer in a single wafer etching apparatus includes: heating a phosphoric acid to a first temperature; heating a sulfuric acid to a second temperature; mixing the heated phosphoric acid and the heated sulfuric acid; heating the phosphoric acid/sulfuric acid mixture to a third temperature; and etching the silicon nitride layer with the heated phosphoric acid/sulfuric acid mixture.

Abstract: In some cases, it is desirable to perform doping when manufacturing a solar cell to improve efficiency. Dopant diffusion may include the steps of: (a) an initial temperature ramp, (b) dopant vapor flow, (c) drive-in, and (d) cool down. However, doping may result in excessive doping, such as in regions where the solar cell has been nanoscale textured to provide black silicon, thereby creating a dead zone with excessive recombination of charge carriers. In the systems and method discussed herein, dopant vapor flow and drive-in steps may be performed at two different temperature set points to minimize or eliminate the formation of dead zones. In some embodiments, the dopant vapor flow may be performed at a lower temperature set point than the drive-in.

Abstract: A method for selectively removing silicon nitride is described. In particular, the method includes providing a substrate having a surface with silicon nitride exposed on at least one portion of the surface and SiGex (x is greater than or equal to zero) exposed on at least another portion of the surface, and dispensing an oxidizing agent onto the surface of the substrate to oxidize the exposed SiGex. Thereafter, the method includes dispensing a silicon nitride etching agent as a liquid stream onto the surface of the substrate to remove at least a portion of the silicon nitride.

Abstract: Photonic devices are created by laterally growing a semiconductor material (i.e., a localized semiconductor-on-insulator layer) over a localized buried oxide (BOX) created in a semiconductor by either a trench isolation process or thermal oxidation. In one embodiment, and after trench formation in a semiconductor substrate, the trench is filled with oxide to create a localized BOX. The top surface of the BOX is recessed to depth below the topmost surface of the semiconductor substrate to expose sidewall surfaces of the semiconductor substrate within each trench. A semiconductor material is then epitaxially grown from the exposed sidewall surfaces of the semiconductor substrate.

Abstract: A method of selectively removing silicon nitride from a substrate comprises providing a substrate having silicon nitride on a surface thereof; and dispensing phosphoric acid and sulfuric acid onto the surface of the substrate as a mixed acid liquid stream at a temperature greater than about 150° C. In this method, water is added to a liquid solution of the mixed acid liquid stream as or after the liquid solution of the mixed acid liquid stream passes through a nozzle.

Abstract: A double ITO structure, containing sequential layers of indium tin oxide (ITO), silicon dioxide (SiO2) (which may include a dopant material) and ITO, is selectively protected by a patterned photo-resist mask. The sequential layers are etched together in a single etching step using an etchant composition which is an acidic solution containing a transition metal chloride and hydrochloric acid (HCl). Thus, the double ITO structure is etched using a substantially fluoride-free etchant composition.

Abstract: Antimony oxide thin films are deposited by atomic layer deposition using an antimony reactant and an oxygen source. Antimony reactants may include antimony halides, such as SbCl3, antimony alkylamines, and antimony alkoxides, such as Sb(OEt)3. The oxygen source may be, for example, ozone. In some embodiments the antimony oxide thin films are deposited in a batch reactor. The antimony oxide thin films may serve, for example, as etch stop layers or sacrificial layers.

Abstract: A two-layered polysilicon capacitive element is manufactured to enable suppression of both of an increase in the applied electric field dependence of the capacitance value and the initial defect of the dielectric film. Included are a lower electrode into which phosphorous ions are implanted, a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film. The dielectric film includes a thermal oxide film formed by partially oxidizing a polysilicon film constituting the lower electrode and etching out its outer layer part, and a deposited oxide film formed on the thermal oxide film.

Abstract: Disclosed is a technique for attaining high etching selectivity of a silicon nitride film to a silicon oxide film. The etching method includes a step of supplying a silylating agent to a substrate having a silicon nitride film and a silicon oxide film exposed on the surface thereof to thereby form a silylated film as a protective film over the surface of the silicon oxide film. After this step, an etching solution is supplied to the substrate. It is thus possible to selectively etch only the silicon nitride film.

Abstract: An improved composition and method for cleaning a surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of the wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying a fluorine ion component, and the amounts of the fluorine ion component and an acid component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute.

Abstract: A method of manufacturing a semiconductor device includes forming a first layer on a semiconductor layer, forming a second layer on the first layer, forming a patterned mask on the second layer, etching and removing a portion of the second layer that is not covered by the patterned mask, wet etching the first layer to a width which is less than the width of the patterned mask, after the wet etching, forming an insulating layer on the semiconductor layer, removing the first layer and the second layer to form an opening in the insulating layer, and forming a gate electrode on a surface of the semiconductor layer exposed through the opening.

Abstract: A DRAM device includes a substrate including an active region having an island shape and a buried gate pattern. A mask pattern is over an upper surface portion of the substrate between portions of the buried gate pattern. A capping insulating layer fills a gap between portions of the mask pattern. A first pad contact penetrates the capping insulating layer and the mask pattern, and contacts a first portion of the substrate in the active region. Second pad contacts are under the capping insulating layer, and contact a second portion of the substrate in the active region positioned at both sides of the first pad contact. A spacer is between the first and second pad contacts to insulate the first and second pad contacts. A bit line configured to electrically connect with the first pad contact, and a capacitor configured to electrically connect with the second pad contacts, are provided.

Abstract: Disclosed is a method for producing ZnO contact layers for solar cells. The layers are etched using hydrofluoric acid so as to generate a texture.

Abstract: An inventive substrate treatment method includes a silylation step of supplying a silylation agent to a substrate, and an etching step of supplying an etching agent to the substrate after the silylation step. The method may further include a repeating step of repeating a sequence cycle including the silylation step and the etching step a plurality of times. The cycle may further include a rinsing step of supplying a rinse liquid to the substrate after the etching step. The cycle may further include a UV irradiation step of irradiating the substrate with ultraviolet radiation after the etching step. The method may further include a pre-silylation or post-silylation UV irradiation step of irradiating the substrate with the ultraviolet radiation before or after the silylation step.

Abstract: Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.

Abstract: A method of fabricating a semiconductor device includes forming a gate dielectric layer comprising an oxide, and at least one conductive layer on a substrate, forming a mask on the conductive layer and patterning the at least one conductive layer by etching the at least one conductive layer using the mask as an etch mask to thereby form a gate electrode, wherein the oxide of the gate dielectric layer and the material of the at least one conductive layer are selected such that a byproduct of the etching of the at least one conductive layer, formed on the mask during the etching of the at least one conductive layer, comprises an oxide having a higher etch rate with respect to an etchant than the oxide of the gate dielectric layer.

Abstract: A reaction block having a plurality of reaction chambers defined therein is provided. A bottom surface of each of the reaction chambers is configured to provide a seal for a corresponding reaction region on the substrate and around a periphery of the substrate. The reaction block includes a plurality of inlet channels and provides a gap between a top surface of the substrate and a bottom surface of the reaction block. The gap accepts a fluid from the inlet channels, wherein the reaction block includes a plurality of vacuum channels having access to the bottom surface of the reaction block to remove the fluid from the gap. A method of selectively etching a substrate for combinatorial processing is also provided.

Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a SiOCl-containing layer on an exposed surface of the spacer material to form a spacer protection layer.

Abstract: Provided are methods for processing semiconductor substrates having hafnium oxide structures as well as silicon nitride and/or silicon oxide structures. Etching solutions and processing conditions described herein provide high etching selectivity of hafnium oxide relative to these other materials. As such, the hafnium oxide structures can be removed (partially or completely) without significant damage to these other structures. In some embodiments, the etching selectivity of hafnium oxide relative to silicon oxide is at least about 10 and even at least about 30. Etching rates of hafnium oxide may be between 3 and 100 Angstroms per minute. A highly diluted water based solution of hydrofluoric acid, e.g., having a dilution ratio of 1000:1 to 10,000:1, may be used for etching to achieve these etching rates and selectivity levels. The solution may be maintained at a temperature of 25° C. to 90° C. during etching.

Abstract: A quart resonator for use in lower frequency applications (typically lower than the higher end of the UHF spectrum) where relatively thick quartz members, having a thickness greater than ten microns, are called for.

Abstract: Disclosed is a thin-film transistor (10) manufacturing method that includes a process for forming a nitrate film (12x) that includes residual nickel (22) on a surface thereof, by bringing a nitric acid solution into contact with a polysilicon layer (11x); and a process for removing the nitrate film (12x) that includes residual nickel (22) from the polysilicon layer (11x) surface. With this surface treatment process, a polysilicon layer (11) with reduced concentration of a surface residual nickel (22) is provided, and a thin-film transistor (10) having excellent surface smoothness is attained.

Abstract: A method for removing a plurality of dielectric materials from a supporting substrate by providing a substrate with a plurality of materials, contacting the substrate at a first temperature with a solution to more quickly remove a first dielectric material than a second dielectric material at the first temperature, and then contacting the substrate at a second temperature with a solution to more quickly remove the second dielectric material than the first dielectric material at the second temperature. Thus, the dielectric materials exhibit different etch rates when etched at the first and second temperatures. The solutions to which the first and second dielectric materials are exposed may contain phosphoric acid. The first dielectric material may be silicon nitride and the second dielectric material may be silicon oxide. Under these conditions, the first temperature may be about 175° C., and the second temperature may be about 155° C.

Abstract: A method for forming a silicon layer according to inventive concept comprises: preparing an SOI substrate; applying an etchant or vapor of the etchant to the SOI substrate; and irradiating a light to the SOI substrate.

Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing an integrated circuit comprising a p-type field effect transistor (pFET), recessing a surface region of the pFET using an ammonia-hydrogen peroxide-water (APM) solution to form a recessed pFET surface region, and depositing a silicon-based material channel on the recessed pFET surface region.

Abstract: Various lithography methods are disclosed. An exemplary lithography method includes forming a first patterned silicon-containing organic polymer layer over a substrate by removing a first patterned resist layer, wherein the first patterned silicon-containing organic polymer layer includes a first opening having a first dimension and a second opening having the first dimension, the first opening and the second opening exposing the substrate; forming a second patterned silicon-containing organic polymer layer over the substrate by removing a second patterned resist layer, wherein a portion of the patterned second silicon-containing organic polymer layer combines with a portion of the first patterned silicon-containing organic polymer layer to reduce the first dimension of the second opening to a second dimension; and etching the substrate exposed by the first opening having the first dimension and the second opening having the second dimension.

Abstract: A method for etching an ultra thin film is provided which includes providing a substrate having the ultra thin film formed thereon, patterning a photosensitive layer formed over the ultra thin film, etching the ultra thin film using the patterned photosensitive layer, and removing the patterned photosensitive layer. The etching process includes utilizing an etch material with a diffusion resistant carrier such that the etch material is prevented from diffusing to a region underneath the photosensitive layer and removing portions of the ultra thin film underneath the photosensitive layer.

Abstract: Methods and etchant compositions for wet etching to selectively remove a hafnium aluminum oxide (HfAlOx) material relative to silicon oxide (SiOx) are provided.

Abstract: A method of etching capable of rapidly and flatly performing wet etching on a Si substrate using fluonitric acid represented by HF(a)HNO3(b)H2O(c) (where the unit of a, b and c is wt % and a+b+c=100). The etching rate of an SiO2 layer with the highly concentrated fluonitric acid is significantly lowered by the appropriate selection of its composition as compared with the etching rate of the Si substrate, and etch the Si substrate until the SiO2 layer is exposed. In this way, it is possible to rapidly etch the Si substrate and significantly enhance the flatness of the etched surface.

Abstract: Disclosed herein are methods of controlling the etching of a layer of silicon nitride relative to a layer of silicon dioxide. In one illustrative example, the method includes providing an etch bath that is comprised of an existing etchant adapted to selectively etch silicon nitride relative to silicon dioxide, performing an etching process in the etch bath using the existing etchant to selectively remove a silicon nitride material positioned above a silicon dioxide material on a plurality of semiconducting substrates, determining an amount of the existing etchant to be removed based upon a per substrate silicon loading of the etch bath by virtue of etching the plurality of substrates in the etch bath and determining an amount of new etchant to be added to the etch bath based upon a per substrate silicon loading of the etch bath by virtue of etching the plurality of substrates in the etch bath.

Abstract: An RFID based thermal bubble type accelerometer includes a flexible substrate, an embedded system on chip (SOC) unit, an RFID antenna formed on the substrate and coupled to a modulation/demodulation module in the SOC unit, a cavity formed on the flexible substrate, and a plurality of sensing assemblies, including a heater and two temperature-sensing elements, disposed along the x-axis direction and suspended over the cavity. The two temperature-sensing elements, serially connected, are separately disposed at two opposite sides and at substantially equal distances from the heater. Two sets of sensing assemblies can be connected in differential Wheatstone bridge. The series-connecting points of the sensing assemblies are coupled to the SOC unit such that an x-axis acceleration can be obtained by a voltage difference between the connecting points. The x-axis acceleration can be sent by the RFID antenna to a reader after it is is modulated and encoded by the modulation/demodulation module.

Abstract: A method of producing a semiconductor substrate product, having the steps of: providing an etching liquid containing water, a hydrofluoric acid compound, and a water-soluble polymer; and applying the etching liquid to a semiconductor substrate, the semiconductor substrate having a silicon layer and a silicon oxide layer, the silicon layer containing an impurity, and thereby selectively etching the silicon oxide layer.

Abstract: A method for manufacturing a semiconductor substrate product having: providing an etching liquid containing water, a hydrofluoric acid compound and an organic solvent, and applying the etching liquid to a semiconductor substrate, the semiconductor substrate having a silicon layer and a silicon oxide layer, the silicon layer containing an impurity, and thereby selectively etching the silicon oxide layer.

Abstract: Methods of fabricating complementary metal-oxide-semiconductor (CMOS) imagers for backside illumination are disclosed. In one embodiment, the method may include forming at a front side of a substrate a plurality of high aspect ratio trenches having a predetermined trench depth, and forming at the front side of the substrate a plurality of photodiodes, where each photodiode is adjacent at least one trench. The method may further include forming an oxide layer on inner walls of each trench, removing the oxide layer, filling each trench with a highly doped material, and thinning the substrate from a back side opposite the front side to a predetermined final substrate thickness. In some embodiments, the substrate may have a predetermined doping profile, such as a graded doping profile, that provides a built-in electric field suitable to guide the flow of photogenerated minority carriers towards the front side.

Abstract: A method and apparatus for controlling a silicon nitride etching bath provides the etching bath including phosphoric acid heated to an elevated temperature. The concentration of silicon in the phosphoric acid is controlled to maintain a desired level associated with a desired silicon nitride/silicon oxide etch selectivity. Silicon concentration is measured while the silicon remains in soluble form and prior to silica precipitation. Responsive to the measuring, fresh heated phosphoric acid is added to the etching bath when necessary to maintain the desired concentration and silicon nitride:silicon oxide etch selectivity and prevent silica precipitation. The addition of fresh heated phosphoric acid enables the etching bath to remain at a steady state temperature. Atomic absorption spectroscopy may be used to monitor the silicon concentration which may be obtained by diluting a sample of phosphoric acid with cold deionized water and measuring before silica precipitation occurs.

Abstract: Etch solutions for selectively etching doped oxide materials in the presence of silicon nitride, titanium nitride, and silicon materials, and methods utilizing the etch solutions, for example, in construction of container capacitor constructions are provided. The etch solutions are formulated as a mixture of hydrofluoric acid and an organic acid having a dielectric constant less than water, optionally, with an inorganic acid, and a pH of 1 or less.

Abstract: A post-dry etching cleaning liquid composition for cleaning a substrate after dry etching is provided, the cleaning liquid composition containing at least one type of fluorine compound, glyoxylic acid, at least one type of organic acid salt, and water. With regard to the fluorine compound, ammonium fluoride may be used. With regard to the organic acid salt, at least one of ammonium oxalate, ammonium tartarate, ammonium citrate, and ammonium acetate may be used.

Abstract: At least part of a dielectric layer is implanted to form implanted regions. The implanted regions affect the etch rate of the dielectric layer during the formation of the openings through the dielectric layer. Metal contacts may be formed within these openings. The dielectric layer, which may be SiO2 or other materials, may be part of a solar cell or other device.

Abstract: A toughening agent composition for increasing the hydrophobicity of an organosilicate glass dielectric film when applied to said film. It includes a component capable of alkylating or arylating silanol moieties of the organosilicate glass dielectric film via silylation, and an activating agent selected from the group consisting of an amine, an onium compound and an alkali metal hydroxide.

Abstract: A method is provided for thinning a wafer, for example a wafer containing Through Silicon Vias (TSV). The method includes providing a bonding wafer coupled to a handling wafer, and performing a wafer edge trimming process that forms a trimmed bonding wafer, where the wafer edge trimming process removes an edge portion of the bonding wafer and exposes an upper surface of the handling wafer. The method further includes forming a protective mask on the trimmed bonding wafer and on the exposed upper surface of the handling wafer, planarizing the protective mask and the trimmed bonding wafer, and selectively removing the planarized protective mask by an etching process. In one embodiment, the removing includes performing a first wet etching process that selectively removes a portion of the planarized trimmed bonding wafer relative to the planarized protective mask, and performing a second wet etching process that selectively removes the planarized protective mask.

Abstract: There are provided a processing liquid for suppressing pattern collapse of a microstructure which includes at least one compound selected from the group consisting of an imidazolium halide containing an alkyl group having 12, 14 or 16 carbon atoms, a pyridinium halide containing an alkyl group having 14 or 16 carbon atoms and an ammonium halide containing an alkyl group having 16 or 18 carbon atoms, and water; and a method for producing a microstructure formed of silicon oxide using the processing liquid.

Abstract: Methods of making current tracks for semiconductors are disclosed. The methods involve selectively depositing a hot melt ink resist containing rosin resins and waxes on a silicon dioxide or silicon nitride layer coating a semiconductor followed by etching uncoated portions of the silicon dioxide or silicon nitride layer with an inorganic acid etch to expose the semiconductor and simultaneously inhibit undercutting of the hot melt ink resist. The etched portions may then be metallized to form a plurality of substantially uniform current tracks.

Abstract: Provided is an etching composition for electively removing silicon dioxide at a high etch rate, more particularly, a composition for wet etching of silicon dioxide, including 1 to 40 wt % of hydrogen fluoride (HF); 5 to 40 wt % of ammonium hydrogen fluoride (NH4HF2); and water, and further including a surfactant to improve selectivity of the silicon dioxide and a silicon nitride film. Since the composition for wet etching of silicon dioxide has the high etch selectivity of the silicon dioxide to the silicon nitride film, it is useful for selectively removing silicon dioxide.

Abstract: A blazed grating is disclosed as well as mode hop-free tunable lasers and a process for fabricating gratings of this type. The grating lies in a general plane and includes a plurality of elongate beams carrying mutually parallel respective reflection surfaces spaced apart from one another with a predefined pitch, each of these reflection surfaces having a normal direction inclined at a grating angle ? to the normal direction of the general plane. The grating includes a plurality of resilient suspension arms connected to the beams and intended to be fastened to a grating support. A first pair of comb electrodes is provided for applying a mechanical force to this assembly, being placed on a first side of the grating, along an axis transverse to the beams, and designed so as to allow the pitch of the grating to be modified in response to the application of the mechanical force.