Abstract: Provided is a fabrication method of a semiconductor device having an improved production yield. An insulating film for forming sidewall insulating films of a gate electrode is deposited on the main surface of a semiconductor wafer and then, subjected to the treatment for equalizing the film thickness distribution. In this treatment, the semiconductor wafer is fixed onto a spin stage of an etching apparatus and rotated; and an etchant is supplied from an etchant nozzle to the main surface of the rotating semiconductor wafer while moving thereabove the etchant nozzle from the peripheral side to the central side on the main surface of the semiconductor wafer. The moving speed of the etchant nozzle is controlled, depending on the thickness distribution of the insulating film and is made lower in a region where a change rate of the thickness of the insulating film in a radial direction of the semiconductor wafer is large than in a region where the change rate is small.

Abstract: A technology for reducing distance between adjacent pixel electrodes to smaller than the limit set by conventional process margin and also preventing adjacent pixel electrodes from being short circuited is provided.

Abstract: Provided is a method of manufacturing a capacitor of a semiconductor device, which can prevent tilting or an electrical short of a lower electrode. In the method, a mesh-type bridge insulating layer is formed above the contact plug on a mold oxide layer. The mold oxide layer and the bridge insulating layer are etched to define an electrode region. The mold oxide layer is removed using an etching gas having an etch selectivity of 500 or greater for the mold oxide layer with respect to the bridge insulating layer.

Abstract: Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed.

Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute.

Abstract: A method and system for release etching a micro-electrical-mechanical-systems (MEMS) device from a substrate. In one aspect, the invention is a method comprising (a) supporting at least one substrate having a sacrificial oxide and a non-sacrificial material in a process chamber at a pressure and at a temperature; (b) introducing a gas phase mixture comprising a halide-containing species and an alcohol vapor selected from a group consisting of ethanol, 1-propanol, and an aliphatic alcohol having four carbon groups into the process chamber, the gas phase mixture having a volumetric ratio of the halide-containing species to the alcohol vapor of approximately 2 or less; and (c) etching the sacrificial oxide with the gas phase mixture. In another aspect, the invention is a system for carrying out the method.

Abstract: The present invention relates to a novel printable etching medium having non-Newtonian flow behaviour for the etching of surfaces in the production of solar cells, and to the use thereof. The present invention furthermore also relates to etching and doping media which are suitable both for the etching of inorganic layers and also for the doping of underlying layers. In particular, they are corresponding particle-containing compositions by means of which extremely fine structures can be etched very selectively without damaging or attacking adjacent areas.

Abstract: Disclosed herein is a method for fabricating a capacitor of a semiconductor device. The method comprises the steps of forming an interlayer insulating film on a semiconductor substrate, forming contact plugs connected to the semiconductor substrate though the interlayer insulating film, forming a first storage node oxide film include a PSG film on the contact plugs, cleaning the semiconductor substrate on which the first storage node oxide film include a PSG film is formed, using isopropyl alcohol (IPA), to remove water-soluble compounds, and forming a second storage node oxide film on the first storage node oxide film.

Abstract: A method for fabricating substrate material to include trenches and unreleased beams with submicron dimensions includes etching a first oxide layer on the substrate to define a first set of voids in the first oxide layer to expose the substrate. A second oxide layer is accreted to the first oxide layer to narrow the first set of voids to become a second set of voids on the substrate. A polysilicon layer is deposited over the second oxide layer, the first oxide layer and the substrate. A third set of voids is etched into the polysilicon layer. Further etching widens the third set of voids to define a fourth set of voids to expose the first oxide layer and the substrate. The first oxide layer and the substrate is deeply etched to define beams and trenches in the substrate.

Abstract: A semiconductor device may be manufactured by a method that includes forming an etch stop layer on a semiconductor substrate, sequentially forming a first interlayer insulating layer, a first diffusion barrier, a second interlayer insulating layer, and a second diffusion barrier on the etch stop layer, forming a via hole exposing the etch stop layer by etching the second diffusion barrier, the second interlayer insulating layer, the first diffusion barrier, and the first interlayer insulating layer, forming a first trench overlapping the via hole by etching the second diffusion barrier and the second interlayer insulating layer, forming a second trench continuous to the first trench by etching the first diffusion barrier and part of the first interlayer insulating layer, and removing the etch stop layer exposed through the via hole, wherein the first and second trenches are etched under different dry etching conditions.

Abstract: A method for manufacturing a low temperature removable silicon dioxide hard mask for patterning and etching is provided, wherein tetra-ethyl-ortho-silane (TEOS) is used to deposit a silicon dioxide hard mask.

Abstract: An imprinting apparatus and method of fabrication provide a mold having a pattern for imprinting. The apparatus includes a semiconductor substrate polished in a [110] direction. The semiconductor substrate has a (110) horizontal planar surface and vertical sidewalls of a wet chemical etched trench. The sidewalls are aligned with and therefore are (111) vertical lattice planes of the semiconductor substrate. The semiconductor substrate includes a plurality of vertical structures between the sidewalls, wherein the vertical structures may be nano-scale spaced apart. The method includes wet etching a trench with spaced apart (111) vertical sidewalls in an exposed portion of the (110) horizontal surface of the semiconductor substrate along (111) vertical lattice planes. A chemical etching solution is used that etches the (111) vertical lattice planes slower than the (110) horizontal lattice plane. The method further includes forming the imprinting mold.

Abstract: Disclosed is a method for making flexible circuits in which portions of a tie layer are removed by etching the underlying polymer. Also disclosed are flexible circuits made by this method.

Abstract: Described herein are methods of forming a thin silicon dioxide layer having a thickness of less than eight angstroms on a semiconductor substrate to form the bottom layer of a gate dielectric. A silicon dioxide layer having a thickness of less than eight angstroms may be formed by two different methods. In one method, a sulfuric acid solution is applied to a semiconductor substrate to grow a silicon dioxide layer of less than eight angstroms. The growth of the silicon dioxide layer by the sulfuric acid solution is self-limiting. In another method, a hydrogen peroxide containing solution is applied to a semiconductor substrate for a time sufficient to grow a silicon dioxide layer having a thickness of greater than eight angstroms and then applying an etching solution to etch the silicon dioxide layer down to a thickness of less than eight angstroms.

Abstract: A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. The dielectric layer is etched with a chemical solution such as LAL. Prior to etching, the protruding portion of the electrode is removed or reduced to prevent any bubbles included in the chemical solution from adhering to the electrode. Thus, the chemical solution can etch the dielectric layers without being blocked by any bubbles included in a chemical solution.

Abstract: A substrate processing apparatus and a substrate processing method are provided wherein an oxide film which is thinner than the conventional films can be formed with uniform thickness when forming an oxide film on the front-side surface of a substrate. A substrate processing apparatus (12) for processing a substrate (W) by feeding a processing liquid comprises: a temperature regulator (133) to regulate the temperature of said processing liquid; and a underplate temperature adjuster (115) to adjust the temperature of an underplate (77) which is placed in proximity to the backside surface of said substrate W.

Abstract: A method of manufacturing a non-volatile memory device includes providing a floating gate layer over a semiconductor substrate. The floating gate layer and the semiconductor substrate are etched to form a trench. An isolation structure is formed in the trench. An upper portion of the isolation structure is etched, wherein an upper sidewall of the floating gate layer is exposed by the etching of the upper portion of the isolation structure. An oxide layer is formed on the floating gate layer to round an upper corner of the floating gate layer. A control gate layer is formed over the floating gate layer.

Abstract: An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon dioxide, a photoresist layer overlying a low-k dielectric layer, or both layers from the surface of a wafer. The composition is formulated according to the invention to provide a desired removal rate of the low-k dielectric and/or photoresist from the surface of the wafer. By varying the fluorine ion component, and the amounts of the fluorine ion component and acid, component, and controlling the pH, a composition can be formulated in order to achieve a desired low-k dielectric removal rate that ranges from slow and controlled at about 50 to about 1000 angstroms per minute, to a relatively rapid removal of low-k dielectric material at greater than about 1000 angstroms per minute.

Abstract: The variability of immersion processes for treatment of semiconductor devices can be significantly lowered by initiating the termination of a treatment process according to a predetermined treatment termination protocol in a manner that takes into account the contribution of, in particular, the treatment that is carried out during the period of time in the treatment process in which the treatment process is being terminated. In a preferred embodiment, conditions that indicate the progress of the treatment on a real time basis are monitored, and the timing of the initiation of the termination process is additionally based on the calculated amount of treatment and treatment rate of the process in progress.

Abstract: According to the present invention, a wet chemical oxidation and etch process cycle allows efficient removal of contaminated silicon surface layers prior to the epitaxial growth of raised source and drain regions, thereby effectively reducing the total thermal budget in manufacturing sophisticated field effect transistor elements. The etch recipes used enable a controlled removal of material, wherein other device components are not unduly degraded by the oxidation and etch process.

Abstract: Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching material on a microfeature workpiece includes providing a microfeature workpiece including a doped oxide layer and a nitride layer adjacent to the doped oxide layer. The method include selectively etching the doped oxide layer with an etchant comprising DI:HF and an acid to provide a pH of the etchant such that the etchant includes (a) a selectivity of phosphosilicate glass (PSG) to nitride of greater than 250:1, and (b) an etch rate through PSG of greater than 9,000 ?/minute.

Abstract: There is provided a method of manufacturing semiconductor device comprising removing an organic substance from a semiconductor surface having an oxide film thereon, the semiconductor surface being formed to have a line width of 50 nm or less; removing the oxide film from the semiconductor surface; drying the semiconductor surface without using an organic solvent; and forming a silicide layer on the semiconductor surface after drying the semiconductor surface.

Abstract: Disclosed herein is a method for forming an isolation film of a semiconductor memory device. According to the disclosure, in a pre-treatment cleaning process performed before a tunnel oxide film is formed, a SC-1 cleaning process is performed at a temperature ranging from 60° C. to 70° C. Therefore, oxide films in a cell region and a peripheral region are recessed even in the SC-1 cleaning process as well as a DHF cleaning process. A DHF cleaning time can be thus reduced. Accordingly, the method can minimize loss of a silicon substrate by DHF and can thus control the depth of a moat.

Abstract: A method for making nanoparticles, nanoparticle inks and device layers therefrom is disclosed. In accordance with the present invention, nanoparticles are isolated from a composite material that is formed by treating a metal oxide precursor to form the metal nanoparticles and a metal oxide matrix. The nanoparticles are then isolated from the composite material by etching at least a portion of the metal oxide matrix to release the metal nanoparticles. In accordance with the embodiments of the invention, the nanoparticles are treated with surfactants and wetting agents either while etching or after etching, are isolated from the etchant and dispersed in a solvent medium and/or are otherwise treated or modified for use in a nanoparticle inks. A layer of the metal nanoparticle ink can then be used to form doped, undoped, patterned and unpatterned device layers or structures in micro-devices.

Abstract: A new method is provided for the creation of an inductor. Layers of pad oxide, a thick layer of dielectric and an etch stop layer are successively created over the surface of a substrate. The layers of etch stop material and dielectric are patterned and etched, creating an inductor pattern whereby the inductor pattern created in the layer of dielectric is located close to the surface of the layer of dielectric. Optionally, support pillars for the inductor can be created at this time through the layer of dielectric. The inductor pattern in the layer of dielectric is filled with metal, the etch stop layer and the layer of dielectric is removed from above the metal fill, additionally exposing the layer of dielectric. The additionally exposed layer of dielectric is etched using a slope etcher.

Abstract: A method is provided for forming at least three devices with different gate oxide thicknesses and different associated operating voltages, in the same integrated circuit device. The method includes forming a plurality of gate oxides with different thicknesses in high voltage and low voltage areas in the same integrated circuit device. A dry etching operation is used to remove the relatively thick gate oxide from the high voltage area using photoresist masking of the low voltage area and a hard mask in the high voltage area, to mask the gate oxide films. A wet etching procedure is then used to remove the gate oxide film from the low voltage areas. The hard mask may be formed over a polysilicon structure.

Abstract: A system and method is disclosed for using a differential wet etch stop technique to provide a uniform oxide layer over a metal layer in a laser trimmed fuse. A layer of boron doped oxide with a slow etch rate is placed over the metal layer. A layer of phosphorus doped oxide with a fast etch rate is placed over the boron doped oxide. The time period required for a wet etch process to etch through the phosphorus doped oxide is calculated. The wet etch process is then applied to the phosphorus doped oxide for the calculated time period. The wet etch process slows significantly when it reaches the boron doped oxide. This method forms a uniform layer of boron doped oxide over the metal layer.

Abstract: The present invention relates to methods of making oxide layers, preferably ultrathin oxide layers, with a high level of uniformity. One such method includes the steps of forming a substantially saturated or saturated oxide layer directly or indirectly on a semiconductor surface of a semiconductor substrate, and etchingly reducing the thickness of the substantially saturated or saturated oxide layer by an amount such that the etched oxide layer has a thickness less than the substantially saturated or saturated oxide layer. In certain embodiments, methods of the present invention provide etched oxide layers with a uniformity of less than about +/?10%. The present invention also relates to microelectronic devices including made by methods of the present invention and manufacturing systems for carrying out methods of the present invention.

Abstract: An antimicrobial cleaning composition and methods for cleaning semiconductor substrates, particularly after chemical mechanical planarization or polishing, are provided. In one embodiment, the cleaning composition combines a solvent, a cleaning agent such as a hydroxycarboxylic acid or salt thereof, and at least one antimicrobial agent resulting in a cleaning composition in which microbial growth is inhibited. Examples of suitable antimicrobial agents include a benzoic acid or salt such as potassium or ammonium benzoate, and sorbic acid or salt such as potassium sorbate. The composition is useful for cleaning a wafer and particularly for removing residual particles after a conductive layer has been planarized to a dielectric layer under the conductive layer in a chemical mechanical planarization of a semiconductor wafer with abrasive slurry particles, particularly after a CMP of copper or aluminum films.

Abstract: A method for forming a silicon oxynitride layer, suitable to be used in the production of semiconductor devices, e.g. poly-silicon thin film transistors, is provided. A plasma surface treatment is performed over a substrate after a silicon nitride/silicon oxide layer has been formed on the substrate by a glow discharge system to transform the silicon nitride/silicon oxide layer into a silicon oxynitride layer. The semiconductor device may be completely manufactured in simplex equipment. Therefore, the production time and production cost are favorably reduced.

Abstract: Numerous embodiments of a method and apparatus for a capping layer are disclosed. In one embodiment, a method of forming a capping layer for a semiconductor device comprises forming one or more layers on at least a portion of the top surface of a semiconductor device, substantially planarizing at least one of the one or more layers, annealing at least a portion of the semiconductor device, and removing a substantial portion of the one or more layers, using one or more etching processes.

Abstract: Silicon oxide etching solutions containing the product of at least one bifluoride source compound dissolved in a solvent consisting of at least one carboxylic acid, and further comprising from about 0.5 to about 3 percent by solution weight of hydrofluoric acid and from about 1 to about 5 percent by solution weight of water, wherein the total concentration of bifluoride source compound is between about 1.25 and about 5.0 moles per kilogram of solvent. Methods for selectively removing silicon oxides and metal silicates from metal surfaces are also disclosed.

Abstract: The present invention relates to a method of manufacturing a semiconductor device. A minute pattern is formed using a hard mask film of a series of a nitride film as an etch mask. Before a hard mask film removal process is performed, the step of performing given etching using an oxide film etchant is added to remove an abnormal oxide film on the nitride film. It is thus possible to effectively remove the hard mask film. Generation of voids in a pattern below the hard mask film can be also effectively prevented using BOE in which the composition ratio of HF and NH4F and an etching temperature are optimized as an oxide film etchant.

Abstract: A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed in overlapping relation, with the gate having opposing edges and a center therebetween. At least one of chlorine or fluorine is concentrated in the gate oxide layer within the overlap more proximate at least one of the gate edges than the center. Preferably, the central region is substantially undoped with fluorine and chlorine. The chlorine and/or fluorine can be provided by forming sidewall spacers proximate the opposing lateral edges of the gate, with the sidewall spacers comprising at least one of chlorine or fluorine. The spacers are annealed at a temperature and for a time effective to diffuse the fluorine or chlorine into the gate oxide layer to beneath the gate.

Abstract: Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.

Abstract: A wafer has a trench, a STI layer formed in the trench, an HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode. The wafer is preheated and a bromine-rich gas plasma is provided to remove portions of the HfO2-containing gate dielectric.

Abstract: A method of forming a pattern finer than an existing pattern in a semiconductor device using an existing light source and a hard mask, and a method of removing the hard mask which is used as an etching mask. The method includes forming an oxide layer on a substrate; forming a polysilicon layer on the oxide layer; forming a hard mask on the polysilicon layer; depositing photoresist on the hard mask and patterning the hard mask by using the photoresist; and etching the polysilicon layer using the pattern embodied by the hard mask. By fabricating a gate oxide with a finer linewidth using a hard mask and existing equipment, the present invention can control the linewidth required in each product by using an etching process, and, therefore, has advantages such as expandability of process, extension of generality, and maximization of productivity in the production line.

Abstract: A method for use in manufacturing a semiconductor device includes forming a photoresist pattern on a substrate, performing first etching process in which an initial trench is formed using the photoresist pattern as a mask, and performing second distinct etching process to enlarge the initial trench. Thus, the initial trench can be formed using the photoresist pattern having a stable structure. Thereafter, the trench is enlarged using an etching solution having a composition based on the material in which the initial trench is formed, e.g., a silicon substrate or an insulation film. Therefore, a metal wiring, an isolation film or a contact can be formed in the enlarged trench to desired dimensions.

Abstract: A porous low-k film, a sacrificial film that can be dissolved in a pure water, an antireflection film and a resist film are successively formed on a dielectric film on a wafer and subsequently exposing the resist film to light in a prescribed pattern and developing the resist film so as to form a prescribed circuit pattern in the resist film. Then, the wafer W is etched so as to form a via hole in the porous low-k film, followed by processing the wafer with a hydrogen peroxide solution so as to denature the resist film. Further, the sacrificial film is dissolved in a pure water so as to strip the resist film and the antireflection film from the water. As a result, a via hole excellent in the accuracy of the shape is formed without doing damage to the dielectric film.

Abstract: Semiconductor devices having a contact window and fabrication methods thereof are provided. A lower dielectric layer, conductive patterns and an upper dielectric layer are formed sequentially on a semiconductor substrate. The lower dielectric layer has a higher isotropic etch rate than that of the upper dielectric layer. The upper dielectric layer and the lower dielectric layer are patterned by anisotropic etching to form a trench without exposing the semiconductor substrate. The resultant structure is subject to isotropic etching to expose the substrate and to form a contact window having a wider width in a lower region than in an upper region without damaging the semiconductor substrate.

Abstract: The present invention relates to a method for fabricating a semiconductor device. In more detail of the aforementioned method, a first mask layer covering a cell region is formed on an insulation layer in the cell region. Meanwhile, a second mask layer is formed in a peripheral circuit region with a predetermined distance from the first mask layer. The insulation layer is then etched with use of the first and the second mask layers as an etch mask to form a spacer at both sidewalls of each gate line pattern in the peripheral region and simultaneously form a guard beneath the second mask layer. The first and the second mask layers are removed thereafter. Next, a third mask layer opening the cell region but covering the whole regions including a guard region in the peripheral circuit region is formed. A wet etching process is performed to the insulation layer remaining in the cell region by using the third mask layer as an etch mask.

Abstract: A method and composition for removing silicon-containing sacrificial layers from Micro Electro Mechanical System (MEMS) and other semiconductor substrates having such sacrificial layers is described. The etching compositions include a supercritical fluid (SCF), an etchant species, a co-solvent, and optionally a surfactant. Such etching compositions overcome the intrinsic deficiency of SCFs as cleaning reagents, viz., the non-polar character of SCFs and their associated inability to solubilize polar species that must be removed from the semiconductor substrate. The resultant etched substrates experience lower incidents of stiction relative to substrates etched using conventional wet etching techniques.

Abstract: There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. A catalytic element for facilitating crystallization of an amorphous semiconductor thin film is added to the amorphous semiconductor thin film, and a heat treatment is carried out to obtain a crystalline semiconductor thin film. After the crystalline semiconductor thin film is irradiated with ultraviolet light or infrared light, a heat treatment at a temperature of 900 to 1200° C. is carried out in a reducing atmosphere. The surface of the crystalline semiconductor thin film is extremely flattened through this step, defects in crystal grains and crystal grain boundaries disappear, and the single crystal semiconductor thin film or substantially single crystal semiconductor thin film is obtained.

Abstract: Disclosed is a method of manufacturing a flash memory device using a STI process. Isolation films of a projection structure becomes isolation films of a nipple structure by means of a slant ion implant process and a wet etching process. A polysilicon layer is removed until the tops of the isolation films through two step processes of a CMP process and an etch-back process, thus forming floating gates and gates of high voltage and low voltage transistors of a cell. As such, as the isolation films of the nipple structure and the floating gates are formed at the same time, it is possible secure the overlay margin between an active region and the floating gates regardless of the shrinkage of the flash memory device. Also, moats can be prevented from being generated at the boundary between the active regions when the isolation films of the nipple structure are formed.

Abstract: The present invention relates to a method for selectively removing a high-k material comprising providing a high-k material on a semiconductor substrate, and contacting the high-k material with a solution comprising HF, an organic compound, and an inorganic acid.

Abstract: A method of preparing a silicon layer or substrate surface for growing an epitaxial layer of SiGe thereon. The process comprises removing native oxide from the surface of the silicon with an HF solution, and then oxidizing the exposed silicon surface to form a chemically formed layer of silicon oxide of the process damaged silicon surface. The chemically formed layer of silicon oxide is then removed by a second HF cleaning process so as to leave a smooth silicon surface suitable for growing a SiGe layer.

Abstract: In a method of forming an oxide layer, ozone is generated by reacting an oxygen gas having a first flow rate with a nitrogen gas having a second flow rate of more than about 1% of the first flow rate. A reactant including the ozone and nitrogen is provided onto a silicon substrate. A surface of the silicon substrate is oxidized via the reaction of the reactant with silicon in the silicon substrate. The flow rate of the nitrogen gas is increased while ozone serving as an oxidant is formed by reacting the nitrogen gas with the oxygen gas. Thus, the oxide layer or a metal oxide layer including nitrogen may be rapidly formed on the substrate.

Abstract: Where a thin film formed on a glass substrate is etched with a solution containing a fluoride, insoluble residues formed by the reaction of the solution with glass substrate components adhere to the back of the substrate to cause etching non-uniformity called roller marks. So, a solution is supplied directly to supporting members for supporting the glass substrate, or concentratedly to a region where the substrate and the supporting members come into contact and from a position opposite to the transporting direction of the substrate, or to both the supporting members and regions where the substrate and the supporting members come into contact. This enables the roller marks to be kept from forming, consequently making it possible to improve display quality of display devices.

Abstract: A method of fabricating an integrated circuit, having copper metallization formed by a dual damascene process, is disclosed. A layered insulator structure is formed over a first conductor (22), within which a second conductor (40) is formed to contact the first conductor. The layered insulator structure includes a via etch stop layer (24), an interlevel dielectric layer (26), a trench etch stop layer (28), an intermetal dielectric layer (30), and a hardmask layer (32). The interlevel dielectric layer (26) and the intermetal dielectric layer (30) are preferably of the same material. A via is partially etched through the intermetal dielectric layer (30), and through an optional trench etch stop layer (28). A trench location is then defined by photoresist (38), and this trench location is transferred to the hardmask layer (32).

Abstract: The present invention discloses an electrode structure of a light emitted diode and manufacturing method of the electrodes. After formed a pn junction of a light emitted diode on a substrate, a layer of SiO2 is deposited on the periphery of the die of the LED near the scribe line of the wafer, then a transparent conductive layer is deposited blanketly, then a layer of gold or AuGe etc. is formed with an opening on the center of the die. After forming alloy with the semiconductor by heat treatment to form ohmic contact, a strip of aluminum (Al) is formed on one side of the die on the front side for wire bonding and to be the positive electrode of the LED. The negative electrode is formed on the substrate by metal contact.