Layers Formed Of Diverse Composition Or By Diverse Coating Processes Patents (Class 438/763)
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Patent number: 8580584Abstract: A system and method of increasing productivity of OLED material screening includes providing a substrate that includes an organic semiconductor, processing regions on the substrate by combinatorially varying parameters associated with the OLED device production on the substrate, performing a first characterization test on the processed regions on the substrate to generate first results, processing regions on the substrate in a combinatorial manner by varying parameters associated with the OLED device production on the substrate based on the first results of the first characterization test, performing a second characterization test on the processed regions on the substrate to generate second results, and determining whether the substrate meets a predetermined quality threshold based on the second results.Type: GrantFiled: September 21, 2012Date of Patent: November 12, 2013Assignee: Intermolecular, Inc.Inventors: Yun Wang, Tony P. Chiang, Chi-I Lang
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Publication number: 20130292807Abstract: Embodiments related to methods for forming a film stack on a substrate are provided. One example method comprises exposing the substrate to an activated oxygen species and converting an exposed surface of the substrate into a continuous monolayer of a first dielectric material. The example method also includes forming a second dielectric material on the continuous monolayer of the first dielectric material without exposing the substrate to an air break.Type: ApplicationFiled: May 7, 2012Publication date: November 7, 2013Applicant: ASM IP HOLDINGS B.V.Inventors: Petri Raisanen, Michael Givens, Mohith Verghese
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Patent number: 8575021Abstract: Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer.Type: GrantFiled: March 14, 2013Date of Patent: November 5, 2013Assignee: Intermolecular, Inc.Inventors: Thomas R. Boussie, Tony P. Chiang, Anh Duong, Zachary Fresco, Nitin Kumar, Chi-I Lang, Sandra G. Malhotra, Jinhong Tong
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Patent number: 8575039Abstract: A surface treating method for treating a surface of a substrate inside a process chamber includes the steps of generating an atmosphere containing no moisture in the process chamber, heating the substrate inside the atmosphere containing no moisture in the process chamber; and causing a reaction between the substrate and an adhesion accelerating agent by feeding the adhesion accelerating agent gas into the process chamber.Type: GrantFiled: March 21, 2012Date of Patent: November 5, 2013Assignee: Tokyo Electron LimitedInventors: Tatsuya Yamaguchi, Hiroyuki Hashimoto
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Patent number: 8569753Abstract: The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.Type: GrantFiled: May 27, 2011Date of Patent: October 29, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Yoshinori Ieda, Keitaro Imai, Kiyoshi Kato, Yuto Yakubo, Yuki Hata
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Publication number: 20130280918Abstract: Described are apparatus and methods for forming silicon interfacial layers on germanium or III-V materials. Such silicon layers may be deposited by atomic layer deposition at specific temperatures to avoid interdiffusion of silicon and the germanium or III-V material.Type: ApplicationFiled: April 18, 2013Publication date: October 24, 2013Inventor: Khaled Z. AHMED
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Publication number: 20130280836Abstract: A method of selectively applying a material to a surface of a substrate from a stamp with a raised surface using an energy activated release layer is provided. The release layer is applied to at least a first portion of a surface of the stamp. A layer of the material is applied to the raised surface of the stamp. The raised surface of the stamp is placed in contact with the surface of the substrate such that the material layer is situated therebetween. Thereafter, the release layer is activated with energy, causing the material layer to release from the raised surface of the stamp, and to adhere to the surface of the substrate. Alternatively, the entire stamp surface may be coated with the release layer and the release layer may be selectively activated in the areas in which the material on the stamp surface is in contact with the substrate.Type: ApplicationFiled: April 20, 2012Publication date: October 24, 2013Applicant: EMAGIN CORPORATIONInventors: Amalkumar P. Ghosh, Ronald W. Wake
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Patent number: 8564025Abstract: An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and poly-Si surrounding the gate conductor and silicide forming metal disposed to react with the poly-Si to form a fully silicided (FUSI) material to induce radial strain in the nanowire.Type: GrantFiled: August 3, 2012Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Guy Cohen, Conal E. Murray, Jeffrey W. Sleight
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Patent number: 8558385Abstract: An interconnection architecture, for a semiconductor device (having regions arranged to include at least an inner region, an intermediate region located at least aside the inner region, and an outer region located at least on a side of the intermediate region opposite to the inner region, includes: one or more pairs of first and second signal lines, each pair extending from the inner region into the intermediate region; first portions and second portions of the first and second signal lines being parallel, respectively, the first portions being located in the inner region; the first and second portion of at least the first signal line not being collinear; and an intra-pair line-spacing, d(i), for each pair including the following magnitudes, d2 in the inner region, and d2? in the intermediate region, where d2<d2?.Type: GrantFiled: September 23, 2011Date of Patent: October 15, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jaeman Yoon, Yungi Kim, Kangyoon Lee, Youngwoong Son
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Publication number: 20130264659Abstract: Embodiments related to metal oxide protective layers formed on a surface of a halogen-sensitive metal-including layer present on a substrate processed in a semiconductor processing reactor are provided. In one example, a method for forming a metal oxide protective layer is provided. The example method includes forming a metal-including active species on the halogen-sensitive metal-including layer, the metal-including active species being derived from a non-halogenated metal oxide precursor. The example method also includes reacting an oxygen-containing reactant with the metal-including active species to form the metal oxide protective layer.Type: ApplicationFiled: April 4, 2012Publication date: October 10, 2013Applicant: ASM IP HOLDINGS B.V.Inventor: Sung-Hoon Jung
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Patent number: 8551891Abstract: Methods of treating the interior of a plasma region are described. The methods include a preventative maintenance procedure or the start-up of a new substrate processing chamber having a remote plasma system. A new interior surface is exposed within the remote plasma system. The (new) interior surfaces are then treated by sequential steps of (1) forming a remote plasma from hydrogen-containing precursor within the remote plasma system and then (2) exposing the interior surfaces to water vapor. Steps (1)-(2) are repeated at least ten times to complete the burn-in process. Following the treatment of the interior surfaces, a substrate may be transferred into a substrate processing chamber. A dielectric film may then be formed on the substrate by flowing one precursor through the remote plasma source and combining the plasma effluents with a second precursor flowing directly to the substrate processing region.Type: GrantFiled: June 20, 2012Date of Patent: October 8, 2013Assignee: Applied Materials, Inc.Inventors: Jingmei Liang, Lili Ji, Nitin K. Ingle
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Publication number: 20130260573Abstract: A method of making a lithography mask with a stress-relief treatment is disclosed. The method includes providing a substrate and depositing an opaque layer on the substrate. The opaque layer is patterned to form a patterned mask. A stress-relief treatment is applied to the patterned mask by using an radiation exposure.Type: ApplicationFiled: April 2, 2012Publication date: October 3, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Chang Lee, Yun-Yue Lin, Hung-Chang Hsieh, Chia-Jen Chen, Yih-Chen Su, Ta-Cheng Lien, Anthony Yen
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Patent number: 8535998Abstract: The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode.Type: GrantFiled: March 9, 2010Date of Patent: September 17, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fung Ka Hing, Haiting Wang, Han-Ting Tsai, Chun-Fai Cheng, Wei-Yuan Lu, Hsien-Ching Lo, Kuan-Chung Chen
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Patent number: 8536017Abstract: A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 ?m or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 ?m or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300° C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO2) and remove a void in the upper portion of the narrower trench.Type: GrantFiled: January 31, 2012Date of Patent: September 17, 2013Assignee: Renesas Electronics CorporationInventors: Masaru Kadoshima, Hiroshi Umeda, Tatsunori Kaneoka, Katsuyuki Horita
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Publication number: 20130230989Abstract: A method for fabricating a semiconductor device is provided, wherein the method comprises steps as follows: A first conductive-type metal-oxide-semiconductor transistor and a second conductive-type metal-oxide-semiconductor transistor are firstly formed on a substrate. Subsequently, a first stress-inducing dielectric layer and a first capping layer are formed in sequence on the first conductive-type metal-oxide-semiconductor transistor; and then a second stress-inducing dielectric layer and a second capping layer are formed in sequence on the second conductive-type metal-oxide-semiconductor transistor. Next, the fist capping layer is removed.Type: ApplicationFiled: March 5, 2012Publication date: September 5, 2013Applicant: United Microelectronics CorporationInventors: An-Chi LIU, Chih-Wen Teng, Tzu-Yu Tseng, Chi-Heng Lin
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Patent number: 8519470Abstract: A semiconductor chip includes a redistribution interconnect that is implemented by shorting bumps, and a semiconductor package and a system each including the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a passivation film disposed on the semiconductor substrate, and a plurality of pseudo bumps disposed on the passivation film. Each pseudo bump is directly connected to adjacent pseudo bumps to form at least one redistribution interconnect.Type: GrantFiled: March 31, 2011Date of Patent: August 27, 2013Assignee: Samsung Electronics Co., LtdInventors: Sun-won Kang, Hwan-sik Lim
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Patent number: 8507388Abstract: In some embodiments, a reducing gas ambient containing a reducing agent is established in a batch process chamber before substrates are subjected to a deposition. The reducing atmosphere is established before and/or during loading of the substrates into the process chamber, and can include flowing reducing gas into the process chamber while the chamber is open. The reducing gas can be a mixture of a reducing agent and an inert gas, with the reducing agent being a minority component of the reducing gas. Using the reducing gas ambient, oxidation of substrate surfaces is reduced.Type: GrantFiled: April 26, 2010Date of Patent: August 13, 2013Assignee: ASM International N.V.Inventors: Steven R. A. Van Aerde, Rene de Blank
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Patent number: 8507389Abstract: Methods for forming a dielectric layer on a substrate are provided herein. In some embodiments a method for forming a dielectric layer on a substrate may include exposing the substrate to a first source gas comprising a silicon precursor and an oxidizer for a first period of time to form a first layer comprising silicon and oxygen; and exposing the substrate to a second source gas comprising a metal precursor and the silicon precursor for a second period of time to form a second layer comprising silicon and a metal, where in the first layer and the second layer form the dielectric layer.Type: GrantFiled: July 14, 2010Date of Patent: August 13, 2013Assignee: Applied Materials, Inc.Inventors: Lucien Date, Paul William Turnbull
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Publication number: 20130203266Abstract: Disclosed herein are various methods of forming metal nitride layers on various types of semiconductor devices. In one example, the method includes forming a layer of insulating material above a semiconducting substrate, performing a physical vapor deposition process to form a metal nitride layer above the layer of insulating material, wherein the metal nitride layer has an intrinsic as-deposited stress level, and performing at least one process operation on the metal nitride layer to reduce a magnitude of the intrinsic as-deposited stress level in the metal nitride layer.Type: ApplicationFiled: February 2, 2012Publication date: August 8, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Bernd Hintze, Frank Koschinsky
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Patent number: 8501634Abstract: A gate structure and a method for fabricating the same are described. A substrate is provided, and a gate dielectric layer is formed on the substrate. The formation of the gate dielectric layer includes depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas. A gate is formed on the gate dielectric layer, so as to form the gate structure.Type: GrantFiled: March 10, 2011Date of Patent: August 6, 2013Assignee: United Microelectronics Corp.Inventors: Shao-Wei Wang, Gin-Chen Huang, Tsuo-Wen Lu, Chien-Liang Lin, Yu-Ren Wang
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Patent number: 8501609Abstract: A method for generating three-dimensional (3D) non-volatile memory (NVM) arrays includes forming multiple parallel horizontally-disposed mono-crystalline silicon beams that are spaced apart and arranged in a vertical stack (e.g., such that an elongated horizontal air gap is defined between each adjacent beam in the stack), forming separate charge storage layers on each of the mono-crystalline silicon beams such that each charge storage layer includes a high-quality thermal oxide layer that entirely covers (i.e., is formed on the upper, lower and opposing side surfaces of) each of the mono-crystalline silicon beams, and then forming multiple vertically-disposed poly-crystalline silicon wordline structures next to the stack such that each wordline structure is connected to each of the bitline structures in the stack by way of corresponding portions of the separate charge storage layers. The memory cells are accessed during read/write operations by way of the corresponding wordline and bitline structures.Type: GrantFiled: February 2, 2012Date of Patent: August 6, 2013Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Avi Strum
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Publication number: 20130196515Abstract: Methods for forming thin metal and semi-metal layers by thermal remote oxygen scavenging are described. In one embodiment, the method includes forming an oxide layer containing a metal or a semi-metal on a substrate, where the semi-metal excludes silicon, forming a diffusion layer on the oxide layer, forming an oxygen scavenging layer on the diffusion layer, and performing an anneal that reduces the oxide layer to a corresponding metal or semi-metal layer by oxygen diffusion from the oxide layer to the oxygen scavenging layer.Type: ApplicationFiled: February 1, 2012Publication date: August 1, 2013Applicant: TOKYO ELECTRON LIMITEDInventor: Robert D. Clark
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Publication number: 20130196514Abstract: Disclosed are method and apparatus for treating a substrate. The apparatus is a dual-function process chamber that may perform both a material process and a thermal process on a substrate. The chamber has an annular radiant source disposed between a processing location and a transportation location of the chamber. Lift pins have length sufficient to maintain the substrate at the processing location while the substrate support is lowered below the radiant source plane to afford radiant heating of the substrate. A method of processing a substrate having apertures formed in a first surface thereof includes depositing material on the first surface in the apertures and reflowing the material by heating a second surface of the substrate opposite the first surface. A second material can then be deposited, filling the apertures partly or completely. Alternately, a cyclical deposition/reflow process may be performed.Type: ApplicationFiled: March 14, 2013Publication date: August 1, 2013Applicant: Applied Materials, Inc.Inventors: Maurice E. EWERT, Anantha SUBRAMANI, Umesh M. KELKAR, Chandrasekhar BALASUBRAMANYAM, Joseph M. RANISH
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Patent number: 8497218Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).Type: GrantFiled: November 17, 2011Date of Patent: July 30, 2013Assignee: Nissan Motor Co., Ltd.Inventors: Satoshi Tanimoto, Noriaki Kawamoto, Takayuki Kitou, Mineo Miura
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Patent number: 8481430Abstract: The present invention provides a method of manufacturing a semiconductor device. The method includes stacking a SiO2 film, a N-containing stopper film, and a resist pattern in this order on a semiconductor substrate, performing etching on the stopper film and the SiO2 film with a F-containing etching gas, with the resist pattern serving as a mask to form an opening, and performing ashing on the resist pattern to remove the resist pattern, using a gas containing an oxygen gas and an inert gas under the condition that the ratio of the oxygen radical to the inert-gas radical becomes equal to or lower than 5.Type: GrantFiled: March 1, 2011Date of Patent: July 9, 2013Assignee: Renesas Electronics CorporationInventor: Ryou Sato
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Publication number: 20130171835Abstract: The purpose of the present invention to provide: a composition which can be used for water-repellent treating of the entire surface of a semiconductor substrate having a pattern formed by laminating a Si-containing insulating layer and a metal layer, at one time; and a method for water-repellent treatment of the semiconductor substrate surface using the composition. The present invention relates to: (1) a composition for water-repellent treatment of a semiconductor substrate surface comprising a) at least one kind of a compound selected from the group consisting of a long-chain alkyl tertiary amine and a long-chain alkyl ammonium salt, b) a base or an acid generating agent, having a condensed ring structure or forming a condensed ring structure by generating a base or an acid and c) a polar organic solvent, and (2) a method for water-repellent treatment of the semiconductor substrate surface having the pattern formed by laminating the Si-containing insulating layer and the metal layer, using the composition.Type: ApplicationFiled: September 7, 2011Publication date: July 4, 2013Applicant: WAKO PURE CHEMICAL INDUSTRIES, LTD.Inventors: Hironori Mizuta, Yoji Urano, Masahiko Kakizawa
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Publication number: 20130171834Abstract: Disclosed herein are methods of forming a film stack which may include the plasma accelerated deposition of a silicon nitride film formed from the reaction of nitrogen containing precursor with silicon containing precursor, the plasma accelerated substantial elimination of silicon containing precursor from the processing chamber, the plasma accelerated deposition of a silicon oxide film atop the silicon nitride film formed from the reaction of silicon containing precursor with oxidant, and the plasma accelerated substantial elimination of oxidant from the processing chamber. Also disclosed herein are process station apparatuses for forming a film stack of silicon nitride and silicon oxide films which may include a processing chamber, one or more gas delivery lines, one or more RF generators, and a system controller having machine-readable media with instructions for operating the one or more gas delivery lines, and the one or more RF generators.Type: ApplicationFiled: November 7, 2012Publication date: July 4, 2013Inventors: Jason Haverkamp, Pramod Subramonium, Joe Womack, Dong Niu, Keith Fox, John Alexy, Patrick Breiling, Jennifer O'Loughlin, Mandyam Spiram, George Andrew Antonelli, Bart van Schravendijk
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Publication number: 20130164945Abstract: A film deposition method includes an adsorption step of adsorbing a first reaction gas onto a substrate by supplying the first reaction gas from a first gas supplying portion for a predetermined period without supplying a reaction gas from a second gas supplying portion while separating a first process area and a second process area by supplying a separation gas from a separation gas supplying portion and rotating a turntable; and a reaction step of having the first reaction gas adsorbed onto the substrate react with a second reaction gas by supplying the second reaction gas from the second gas supplying portion for a predetermined period without supplying a reaction gas from the first gas supplying portion while separating the first process area and the second process area by supplying the separation gas from the separation gas supplying portion and rotating the turntable.Type: ApplicationFiled: December 26, 2012Publication date: June 27, 2013Applicant: Tokyo Electron LimitedInventor: Tokyo Electron Limited
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Patent number: 8470718Abstract: A vapor deposition reactor includes a chamber filled with a first material, and at least one reaction module in the chamber. The reaction module may be configured to make a substrate pass the reaction module through a relative motion between the substrate and the reaction module. The reaction module may include an injection unit for injecting a second material to the substrate. A method for forming thin film includes positioning a substrate in a chamber, filling a first material in the chamber, moving the substrate relative to a reaction module in the chamber, and injecting a second material to the substrate while the substrate passes the reaction module.Type: GrantFiled: August 11, 2009Date of Patent: June 25, 2013Assignee: Synos Technology, Inc.Inventor: Sang In Lee
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Patent number: 8470719Abstract: Provided are a nonvolatile memory device and a method of fabricating the same, in which a phase-change layer is formed using a solid-state reaction to reduce a programmable volume, thereby lessening power consumption. The device includes a first reactant layer, a second reactant layer formed on the first reactant layer, and a phase-change layer formed between the first and second reactant layers due to a solid-state reaction between a material forming the first reactant layer and a material forming the second reactant layer. The phase-change memory device consumes low power and operates at high speed.Type: GrantFiled: May 18, 2011Date of Patent: June 25, 2013Assignee: Electronics and Telecommunications Research InstituteInventors: Seung Yun Lee, Young Sam Park, Sung Min Yoon, Soon Won Jung, Byoung Gon Yu
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Patent number: 8471267Abstract: A semiconductor device of the present invention has a semiconductor element region 17 that is provided in part of a silicon carbide layer 3 and a guard-ring region 18 that is provided in another part of the silicon carbide layer 3 surrounding the semiconductor element region 17 when seen in a direction perpendicular to a principal surface of the silicon carbide layer 3.Type: GrantFiled: August 26, 2010Date of Patent: June 25, 2013Assignee: Panasonic CorporationInventors: Masashi Hayashi, Koichi Hashimoto, Kazuhiro Adachi
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Publication number: 20130149874Abstract: A method of manufacturing a semiconductor device is provided. The method includes: forming a thin film containing a predetermined element on a substrate by repeating a cycle, the cycle including: forming a first layer containing the predetermined element, nitrogen and carbon by alternately performing supplying a source gas containing the predetermined element and a halogen element to the substrate and supplying a first reactive gas containing three elements including the carbon, the nitrogen and hydrogen and having a composition wherein a number of carbon atoms is greater than that of nitrogen atoms to the substrate a predetermined number of times; forming a second layer by supplying a second reactive gas different from the source gas and the first reactive gas to the substrate to modify the first layer; and modifying a surface of the second layer by supplying a hydrogen-containing gas to the substrate.Type: ApplicationFiled: December 8, 2012Publication date: June 13, 2013Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventor: HITACHI KOKUSAI ELECTRIC INC.
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Publication number: 20130149873Abstract: A thin film including characteristics of low permittivity, high etching resistance and high leak resistance is to be formed. A method of manufacturing a semiconductor device includes forming a thin film containing a predetermined element on a substrate by performing a cycle a predetermined number of times, the cycle including: forming a first layer containing the predetermined element, nitrogen and carbon by alternately performing supplying a source gas containing the predetermined element and a halogen element to the substrate and supplying a first reactive gas containing three elements including the carbon, the nitrogen and hydrogen and having a composition wherein a number of carbon atoms is greater than that of nitrogen atoms to the substrate a predetermined number of times; and forming a second layer by supplying a second reactive gas different from the source gas and the first reactive gas to the substrate to modify the first layer.Type: ApplicationFiled: December 8, 2012Publication date: June 13, 2013Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventor: HITACHI KOKUSAI ELECTRIC INC.
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Patent number: 8455369Abstract: A trench embedding method includes forming an oxidization barrier film on a trench; forming an expandable film on the oxidization barrier film; embedding an embedding material that contracts by being fired on the trench; and firing the embedding material, wherein the forming of the oxidization barrier film includes: forming a first seed layer on the trench by supplying an aminosilane-based gas; and forming a silicon nitride film on the first seed layer, wherein the forming of the expandable film includes: forming a second seed layer on the silicon nitride film by supplying an aminosilane-based gas; and forming a silicon film on the second seed layer.Type: GrantFiled: December 22, 2011Date of Patent: June 4, 2013Assignee: Tokyo Electron LimitedInventors: Masahisa Watanabe, Mitsuhiro Okada
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Patent number: 8455293Abstract: A method for processing solar cells comprising: providing a vertical furnace to receive an array of mutually spaced circular semiconductor wafers for integrated circuit processing; composing a process chamber loading configuration for solar cell substrates, wherein a size of the solar cell substrates that extends along a first surface to be processed is smaller than a corresponding size of the circular semiconductor wafers, such that multiple arrays of mutually spaced solar cell substrates can be accommodated in the process chamber, loading the solar cell substrates into the process chamber; subjecting the solar cell substrates to a process in the process chamber.Type: GrantFiled: November 6, 2012Date of Patent: June 4, 2013Assignee: ASM International N.V.Inventors: Chris G. M. de Ridder, Klaas P. Boonstra, Adriaan Garssen, Frank Huussen
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Patent number: 8450218Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.Type: GrantFiled: December 28, 2011Date of Patent: May 28, 2013Assignee: Micron Technology, Inc.Inventors: Yunjun Ho, Brent Gilgen
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Publication number: 20130127023Abstract: The invention relates to a method for producing a graphene sheet on a platinum silicide, wherein the platinum silicide is in the form of a layer or a plurality of pins. This method comprises: a) producing a stack by (i) depositing a layer C1 of a diffusion barrier material on a substrate; (ii) depositing, on the layer C1, a layer C2 of a carbon-containing material, wherein said carbon-containing material optionally comprises silicon; (iii) depositing, on the layer C2, a layer C3 of platinum; (iv) depositing a layer C4 of a material of formula SiaCbHc on the layer C3 if the carbon-containing material of the layer C2 is free from silicon; and b) heat-treating the stack obtained at step a). It also relates to structures obtained using this method and the uses of these structures. Applications: manufacture of micro- and nanoelectronic devices, micro- and nanoelectromechanical devices, etc.Type: ApplicationFiled: November 6, 2012Publication date: May 23, 2013Applicant: Commissariat a l'energie atomique et aux energies alternativesInventor: Commissariat a l'energie atomique et aux energies
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Publication number: 20130122720Abstract: A high-k capacitor insulating film stable at a higher temperature is formed. There is provided a method of manufacturing a semiconductor device. The method comprises: forming a first amorphous insulating film comprising a first element on a substrate; adding a second element different from the first element to the first amorphous insulating film so as to form a second amorphous insulating film on the substrate; and annealing the second amorphous insulating film at a predetermined annealing temperature so as to form a third insulating film by changing a phase of the second amorphous insulating film. The concentration of the second element added to the first amorphous insulating film is controlled according to the annealing temperature.Type: ApplicationFiled: December 13, 2012Publication date: May 16, 2013Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventor: HITACHI KOKUSAI ELECTRIC INC.
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Patent number: 8435858Abstract: A semiconductor device manufacturing method includes: removing an insulating film on a semiconductor substrate by using wet etching and subsequently oxidizing a surface of the substrate by using a liquid oxidation agent without exposing this surface to an atmosphere, thereby forming a first insulating film containing an oxide of a constituent element of the substrate on the surface of the substrate; forming a second insulating film containing aluminum and another metal element on the first insulating film; forming a high-k insulating film containing at least one of hafnium and zirconium on the second insulating film; forming a metal film on the high-k insulating film; and conducting heat treatment to react the first insulating film and the second insulating film, thereby forming a third insulating film made of a mixture containing aluminum, the another metal element, the constituent element of the substrate, and oxygen.Type: GrantFiled: October 27, 2011Date of Patent: May 7, 2013Assignee: Kabshiki Kaisha ToshibaInventors: Seiji Inumiya, Tomonori Aoyama
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Patent number: 8435905Abstract: The present invention provides a manufacturing method of a semiconductor device that has a rapid film formation rate and high productivity, and to provide a substrate processing apparatus.Type: GrantFiled: June 13, 2006Date of Patent: May 7, 2013Assignee: Hitachi Kokusai Electric Inc.Inventors: Sadayoshi Horii, Hideharu Itatani, Kazuhiro Harada
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Publication number: 20130109195Abstract: Provided is a method of operating a film forming apparatus capable of suppressing generation of particles by improving an adhesion of a carbon film to surfaces of members which are formed of a quartz material and contact a processing space in a processing container. The method includes forming a carbon film on each of surfaces of a plurality of objects held by a holding unit in a processing container formed of a quartz material, wherein the method further includes forming an adhesion film to improve the adhesion of the carbon film, on surfaces of members which are formed of a quartz material and contact a processing space in the processing container. Accordingly, the adhesion of the carbon film to the surface of the member formed of a quartz material contacting the processing space in the processing container is improved, thereby suppressing generation of particles.Type: ApplicationFiled: October 26, 2012Publication date: May 2, 2013Applicant: TOKYO ELECTRON LIMITEDInventor: TOKYO ELECTRON LIMITED
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Publication number: 20130109196Abstract: A method of operating a film forming apparatus includes forming a carbon film on each of surfaces of a plurality of objects held by a holding unit in a processing container and performing a cleaning process with a cleaning gas to remove an unnecessary carbon film adhered on a inside of the processing container, wherein the method further includes, before the forming of the carbon film, forming, on a surface of a member contacting a processing space in the processing container, a tolerant pre-coating film which has a tolerance to the cleaning gas and improves adhesion of the carbon film to the surface of the member. Accordingly, the adhesion of the carbon film is improved, and further, the tolerant pre-coating film remains even when the cleaning process of removing the unnecessary carbon film is performed.Type: ApplicationFiled: October 26, 2012Publication date: May 2, 2013Applicant: TOKYO ELECTRON LIMITEDInventor: TOKYO ELECTRON LIMITED
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Publication number: 20130102160Abstract: Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops and may have sidewalls extending downwardly from the tops. A first material may be formed along the tops and sidewalls of the features. The first material may be formed by spin-casting a conformal layer of the first material across the features, or by selective deposition along the features relative to the substrate. After the first material is formed, fill material may be provided between the features while leaving regions of the first material exposed. The exposed regions of the first material may then be selectively removed relative to both the fill material and the features to create the pattern of openings.Type: ApplicationFiled: December 11, 2012Publication date: April 25, 2013Applicant: MICRON TECHNOLOGY, INC.Inventor: Micron Technology, Inc.
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Patent number: 8426320Abstract: The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps.Type: GrantFiled: June 20, 2011Date of Patent: April 23, 2013Assignee: Wostec, Inc.Inventors: Valery K. Smirnov, Dmitry S. Kibalov
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Patent number: 8421140Abstract: A capacitor structure and method of forming it are described. In particular, a high-K dielectric oxide is provided as the capacitor dielectric. The high-K dielectric is deposited in a series of thin layers and oxidized in a series of oxidation steps, as opposed to a depositing a single thick layer. Further, at least one of the oxidation steps is less aggressive than the oxidation environment or environments that would be used to deposit the single thick layer. This allows greater control over oxidizing the dielectric and other components beyond the dielectric.Type: GrantFiled: July 3, 2003Date of Patent: April 16, 2013Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Guy T. Blalock
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Patent number: 8415257Abstract: Amorphous carbon material may be deposited with superior adhesion on dielectric materials, such as TEOS based silicon oxide materials, in complex semiconductor devices by applying a plasma treatment, such as an argon treatment and/or forming a thin adhesion layer based on silicon dioxide, carbon-doped silicon dioxide, prior to depositing the carbon material. Consequently, the hard mask concept based on amorphous carbon may be applied with an increased degree of flexibility, since a superior adhesion may allow a higher degree of flexibility in selecting appropriate deposition parameters for the carbon material.Type: GrantFiled: October 6, 2010Date of Patent: April 9, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Hartmut Ruelke, Volker Jaschke
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Publication number: 20130084712Abstract: A semiconductor manufacturing method includes forming an oxide film on a substrate by performing a first cycle a predetermined number of times, including supplying a first source gas, an oxidizing gas and a reducing gas to the substrate heated to a first temperature in a process container under a sub-atmospheric pressure; forming a seed layer on a surface of the oxide film by supplying a nitriding gas to the substrate in the process container, the substrate being heated to a temperature equal to or higher than the first temperature and equal to or lower than a second temperature; and forming a nitride film on the seed layer formed on the surface of the oxide film by performing a second cycle a predetermined number of times, including supplying a second source gas and the nitriding gas to the substrate heated to the second temperature in the process container.Type: ApplicationFiled: September 14, 2012Publication date: April 4, 2013Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Kazuhiro YUASA, Naonori AKAE, Masato TERASAKI
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Publication number: 20130084713Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.Type: ApplicationFiled: October 26, 2012Publication date: April 4, 2013Inventors: Jong-Ho LEE, Nae-In Lee
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Publication number: 20130084711Abstract: Methods of treating the interior of a plasma region are described. The methods include a preventative maintenance procedure or the start-up of a new substrate processing chamber having a remote plasma system. A new interior surface is exposed within the remote plasma system. The (new) interior surfaces are then treated by sequential steps of (1) forming a remote plasma from hydrogen-containing precursor within the remote plasma system and then (2) exposing the interior surfaces to water vapor. Steps (1)-(2) are repeated at least ten times to complete the burn-in process. Following the treatment of the interior surfaces, a substrate may be transferred into a substrate processing chamber. A dielectric film may then be formed on the substrate by flowing one precursor through the remote plasma source and combining the plasma effluents with a second precursor flowing directly to the substrate processing region.Type: ApplicationFiled: June 20, 2012Publication date: April 4, 2013Applicant: Applied Materials, Inc.Inventors: Jingmei Liang, Lili Ji, Nitin K. Ingle
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Patent number: 8410001Abstract: An excellent type of a film is realized by modifying conventional types of films.Type: GrantFiled: March 14, 2011Date of Patent: April 2, 2013Assignee: Hitachi Kokusai Electric Inc.Inventors: Yushin Takasawa, Yoshiro Hirose, Tsukasa Kamakura, Yukinao Kaga