Using Electromagnetic Or Wave Energy Patents (Class 438/776)
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Patent number: 8153538Abstract: A process is disclosed for annealing a single crystal silicon wafer having a front surface and a back surface, and an oxide layer disposed on the front surface of the wafer extending over substantially all of the radial width. The process includes annealing the wafer in an annealing chamber having an atmosphere comprising oxygen. The process also includes maintaining a partial pressure of water above a predetermined value such that the wafer maintains the oxide layer through the annealing process. The annealed front surface is substantially free of boron and phosphorus.Type: GrantFiled: December 9, 2010Date of Patent: April 10, 2012Assignee: MEMC Electronic Materials, Inc.Inventors: Larry Wayne Shive, Brian Lawrence Gilmore
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Publication number: 20120052693Abstract: When alternately performing a film deposition step where a silicon-containing gas and O3 gas are alternately supplied to a substrate on a susceptor by rotating the susceptor thereby to forma thin film of the reaction product, and an alteration step where the reaction product is altered by irradiating plasma to the substrate, plasma intensity of the plasma is changed during film deposition. Specifically, the plasma intensity is lower when a thickness of the thin film is small (or at an initial stage of the film deposition—alteration step), and is increased as the thin film becomes thicker (or as the number of the film deposition steps is increased). Alternatively, the plasma intensity is higher when the thin film is relatively thin and then reduced.Type: ApplicationFiled: August 24, 2011Publication date: March 1, 2012Applicant: Tokyo Electron LimitedInventors: Shigenori OZAKI, Hitoshi Kato, Takeshi Kumagai
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Patent number: 8101490Abstract: A method for manufacturing a semiconductor device includes: irradiating a growth substrate with laser light to focus the laser light into a prescribed position inside a crystal for a semiconductor device or inside the growth substrate, the crystal for the semiconductor device being formed on a first major surface of the growth substrate; moving the laser light in a direction parallel to the first major surface; and peeling off a thin layer including the crystal for the semiconductor device from the growth substrate, a wavelength of the laser light being longer than an absorption end wavelength of the crystal for the semiconductor device or the growth substrate, the laser light being irradiated inside a crystal for the semiconductor device or inside the growth substrate.Type: GrantFiled: March 22, 2010Date of Patent: January 24, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masanobu Ando, Toru Gotoda, Toru Kita
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Publication number: 20110318940Abstract: A method of manufacturing a semiconductor device includes forming a layer containing a predetermined element on a substrate by supplying a source gas containing the predetermined element into a process vessel and exhausting the source gas from the process vessel to cause a chemical vapor deposition (CVD) reaction. A nitrogen-containing gas is supplied into the process vessel and then exhausted, changing the layer containing the predetermined element into a nitride layer. This process is repeated to form a nitride film on the substrate. The process vessel is purged by supplying an inert gas into the process vessel and exhausting the inert gas from the process vessel between forming the layer containing the predetermined element and changing the layer containing the predetermined element into the nitride layer.Type: ApplicationFiled: June 24, 2011Publication date: December 29, 2011Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Yosuke OTA, Yoshiro HIROSE, Naonori AKAE, Yushin TAKASAWA
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Patent number: 8067293Abstract: A semiconductor device and a method of manufacturing the same. The method includes preparing a semiconductor substrate having high-voltage and low-voltage device regions, forming a field insulating layer in the high-voltage device region, forming a first gate oxide layer on the semiconductor substrate, exposing the semiconductor substrate in the low-voltage device region by etching part of the first gate oxide layer and also etching part of the field insulating layer to form a stepped field insulating layer, forming a second gate oxide layer on the first gate oxide layer in the high-voltage device region and on the exposed semiconductor substrate in the low-voltage device region, and forming a gate over the stepped field insulating layer and part of the second gate oxide layer in the high-voltage device region adjoining the field insulating layer.Type: GrantFiled: October 1, 2009Date of Patent: November 29, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Cho Eung Park
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Publication number: 20110256734Abstract: Described are methods of making SiN materials on substrates, particularly SiN thin films on semiconductor substrates. Improved SiN films made by the methods are also included.Type: ApplicationFiled: April 11, 2011Publication date: October 20, 2011Inventors: Dennis M. Hausmann, Jon Henri, Mandyam Sriram, Bart J. van Schravendijk
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Patent number: 8038834Abstract: A plasma processing system includes a processing chamber, a substrate holder configured to hold a substrate for plasma processing, and a gas injection assembly. The gas injection assembly includes a first evacuation port located substantially in a center of the gas injection assembly and configured to evacuate gases from a central region of the substrate, and a gas injection system configured to inject gases in the process chamber. The plasma processing system also includes a second evacuation port configured to evacuate gases from a peripheral region surrounding the central region of the substrate.Type: GrantFiled: April 6, 2010Date of Patent: October 18, 2011Assignees: Tokyo Electron Limited, International Business Machines Corporation (“IBM”)Inventors: Merritt Funk, David V. Horak, Eric J. Strang, Lee Chen
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Patent number: 8021987Abstract: An insulting film is modified by subjecting the insulting film to a modification treatment comprising a combination of a plasma treatment and a thermal annealing treatment. There is provided a method of enhancing the characteristic of an insulating film by improving deterioration in the characteristic of the insulating film due to carbon, a suboxide, a dangling bond or the like contained in the insulating film.Type: GrantFiled: December 7, 2009Date of Patent: September 20, 2011Assignee: Tokyo Electron LimitedInventors: Takuya Sugawara, Yoshihide Tada, Genji Nakamura, Shigenori Ozaki, Toshio Nakanishi, Masaru Sasaki, Seiji Matsuyama, Kazuhide Hasebe, Shigeru Nakajima, Tomonori Fujiwara
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Patent number: 7977255Abstract: A method for forming a thin-film transistor gate insulating layer over a substrate disposed in a processing chamber is provided. The method includes: introducing a processing gas for producing a plasma in the processing chamber; heating the substrate to a substrate processing temperature of between 50 and 350° C.; and depositing silicon oxide, silicon oxynitride, or silicon nitride over the heated substrate by sputtering a target assembly at a medium frequency.Type: GrantFiled: September 16, 2010Date of Patent: July 12, 2011Assignee: Applied Materials, Inc.Inventors: Evelyn Scheer, Oliver Graw, Roland Weber, Udo Schreiber
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Patent number: 7960293Abstract: A method for forming an insulating film includes forming a silicon nitride film on a silicon surface by subjecting a target substrate wherein silicon is exposed in the surface to a treatment for nitriding the silicon, forming a silicon oxynitride film by heating the target substrate provided with the silicon nitride film in an N2O atmosphere, and nitriding the silicon oxynitride film.Type: GrantFiled: May 30, 2007Date of Patent: June 14, 2011Assignee: Tokyo Electron LimitedInventors: Minoru Honda, Yoshihiro Sato, Toshio Nakanishi
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Publication number: 20110124202Abstract: According to the present invention, when a nitridation process by plasma generated by a microwave is applied to a substrate with an oxide film having been formed thereon to form an oxynitride film, the microwave is intermittently supplied. By the intermittent supply of the microwave, ion bombardment is reduced in accordance with a decrease in electron temperature, and a diffusion velocity of nitride species in the oxide film lowers, which as a result makes it possible to prevent nitrogen from concentrating in a substrate-side interface of an oxynitride film to increase the nitrogen concentration therein. Consequently, it is possible to improve quality of the oxynitride film, resulting in a reduced leakage current, an improved operating speed, and improved NBTI resistance.Type: ApplicationFiled: February 1, 2011Publication date: May 26, 2011Applicant: Tokyo Electron LimitedInventors: Seiji MATSUYAMA, Toshio Nakanishi, Shigenori Ozaki, Hikaru Adachi, Koichi Takatsuki, Yoshihiro Sato
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Publication number: 20110124172Abstract: Provided are a method of forming an insulating layer and a method of manufacturing a transistor using the method. The method of forming the insulating layer includes forming a preliminary insulating layer including silicon oxide (SiO2) on a silicon (Si)-containing substrate. A reactive gas containing ammonia (NH3) gas is supplied to the preliminary insulating layer. Nitrogen radicals (N*) and hydrogen radicals (H*) are generated from the ammonia gas using plasma. The hydrogen radicals combine with oxygen of the preliminary insulating layer, and the nitrogen radicals combine with the silicon oxide so that an insulating layer including hydroxides (OH) and silicon oxynitride (SiON) can be formed.Type: ApplicationFiled: November 19, 2010Publication date: May 26, 2011Inventors: Seong-Hoon JEONG, Dong-Chan KIM, Yu-Gyun SHIN, Soo-Jin HONG, Deok-Hyung LEE
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Patent number: 7932549Abstract: A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.Type: GrantFiled: December 18, 2003Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Steven J. Holmes, Toshiharu Furukawa, Mark C. Hakey, David V. Horak, Charles W. Koburger, III, Larry A. Nesbit
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Patent number: 7928018Abstract: The application of oxynitriding treatment to electronic appliances involve the problem that N2 ions are formed to thereby damage any oxynitride film. It is intended to provide a method of plasma treatment capable of realizing high-quality oxynitriding and to provide a process for producing an electronic appliance in which use is made of the method of plasma treatment. There is provided a method of plasma treatment, comprising generating plasma with a gas for plasma excitation and introducing a treating gas in the plasma to thereby treat a treatment subject, wherein the treating gas contains nitrous oxide gas, this nitrous oxide gas introduced in a plasma of <2.24 eV electron temperature, so that the generation of ions tending to damage any insulating film is reduced to thereby realize high-quality oxynitriding. Further, there is provided a process for producing an electronic appliance in which use is made of the method of plasma treatment.Type: GrantFiled: March 31, 2005Date of Patent: April 19, 2011Assignee: Foundation for Advancement of International ScienceInventors: Tadahiro Ohmi, Akinobu Teramoto, Hiroshi Yamauchi, Yukio Hayakawa
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Patent number: 7910493Abstract: A nitrided region is formed on a surface of a polysilicon layer by a nitriding treatment wherein plasma of a processing gas is generated by introducing microwaves into a processing chamber by a planar antenna having a plurality of slots. Then, a CVD oxide film or the like is formed on the nitrided region and after patterning the polysilicon layer and the like after the prescribed shape, and then, a thermal oxide film is formed by thermal oxidation on exposed side walls and the like of the polysilicon layer by having the nitrided region as an oxidation barrier layer. Thus, generation of bird's beak can be suppressed in the process at a temperature lower than the temperature in a conventional process.Type: GrantFiled: April 14, 2006Date of Patent: March 22, 2011Assignee: Tokyo Electron LimitedInventors: Junichi Kitagawa, Takashi Kobayashi
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Patent number: 7898584Abstract: In one aspect, an image sensor is provided which includes an active pixel array and a control circuit connected to the active pixel array. The active pixel array of this aspect includes a plurality of first gate dielectric layers, and the control circuit includes a plurality of second gate dielectric layers, where the first gate dielectric layers are plasma nitrided silicon oxide layers.Type: GrantFiled: January 26, 2006Date of Patent: March 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong Ho Lyu, Duck Hyung Lee, Kab sung Uem, Hee Geun Jeong
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Patent number: 7897518Abstract: According to the present invention, when a nitridation process by plasma generated by a microwave is applied to a substrate with an oxide film having been formed thereon to form an oxynitride film, the microwave is intermittently supplied. By the intermittent supply of the microwave, ion bombardment is reduced in accordance with a decrease in electron temperature, and a diffusion velocity of nitride species in the oxide film lowers, which as a result makes it possible to prevent nitrogen from concentrating in a substrate-side interface of an oxynitride film to increase the nitrogen concentration therein. Consequently, it is possible to improve quality of the oxynitride film, resulting in a reduced leakage current, an improved operating speed, and improved NBTI resistance.Type: GrantFiled: April 9, 2010Date of Patent: March 1, 2011Assignee: Tokyo Electron LimitedInventors: Seiji Matsuyama, Toshio Nakanishi, Shigenori Ozaki, Hikaru Adachi, Koichi Takatsuki, Yoshihiro Sato
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Publication number: 20100317186Abstract: Embodiments described herein generally relate to flash memory devices and methods for manufacturing flash memory devices. In one embodiment, a method for selective removal of nitrogen from the nitrided areas of a substrate is provided. The method comprises positioning a substrate comprising a material layer disposed adjacent to an oxide containing layer in a processing chamber, exposing the substrate to a nitridation process to incorporate nitrogen onto the material layer and the exposed areas of the oxide containing layer, and exposing the nitrided material layer and the nitrided areas of the oxide containing layer to a gas mixture comprising a quantity of a hydrogen containing gas and a quantity of an oxygen containing gas to selectively remove nitrogen from the nitrided areas of the oxide containing layer relative to the nitrided material layer using a radical oxidation process.Type: ApplicationFiled: June 15, 2010Publication date: December 16, 2010Applicant: APPLIED MATERIALS, INC.Inventors: Johanes Swenberg, David Chu, Theresa Kramer Guarini, Yonah Cho, Udayan Ganguly, Lucien Date
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Patent number: 7811945Abstract: A selective plasma processing method, within a processing chamber of a plasma processing apparatus, acts oxygen-containing plasma on a target object having silicon and a silicon nitride layer to selectively oxidize the silicon with respect to the silicon nitride layer and to form a silicon oxide film. Further, the ratio of a thickness of a silicon oxynitride film formed within the silicon nitride layer to a thickness of the silicon oxide film formed by the oxidization is equal to or smaller than 20%.Type: GrantFiled: March 21, 2008Date of Patent: October 12, 2010Assignee: Tokyo Electron LimitedInventor: Masaru Sasaki
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Publication number: 20100230677Abstract: A thin film transistor in which deterioration at initial operation is not likely to be caused and a manufacturing method thereof. A transistor which includes a gate insulating layer at least whose uppermost surface is a silicon nitride layer, a semiconductor layer over the gate insulating layer, and a buffer layer over the semiconductor layer and in which the concentration of nitrogen in the vicinity of an interface between the semiconductor layer and the gate insulating layer, which is in the semiconductor layer is lower than that of the buffer layer and other parts of the semiconductor layer. Such a thin film transistor can be manufactured by exposing the gate insulating layer to an air atmosphere and performing plasma treatment on the gate insulating layer before the semiconductor layer is formed.Type: ApplicationFiled: March 2, 2010Publication date: September 16, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hidekazu MIYAIRI, Erika KATO, Kunihiko SUZUKI
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Patent number: 7795156Abstract: Disclosed is a producing method of a semiconductor device comprising a step of forming a tunnel insulating film of a flash device comprising a first nitridation step of forming a first silicon oxynitride film by nitriding a silicon oxide film formed on a semiconductor silicon base by one of plasma nitridation and thermal nitridation, the plasma nitridation carrying out nitridation process by using a gas activated by plasma discharging a first gas including a first compound which has at least a nitrogen atom in a chemical formula thereof, and the thermal nitridation carrying out nitridation process using heat by using a second gas including a second compound which has at least a nitrogen atom in a chemical formula thereof, and a second nitridation step of forming a second silicon oxynitride film by nitriding the first silicon oxynitride film by the other of the plasma nitridation and the thermal nitridation.Type: GrantFiled: October 31, 2005Date of Patent: September 14, 2010Assignee: Hitachi Kokusai Electric Inc.Inventors: Tadashi Terasaki, Akito Hirano, Masanori Nakayama, Unryu Ogawa
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Patent number: 7781350Abstract: In a method and system for controllable electrostatic-directed deposition of nanoparticles from the gas phase on a substrate patterned to have p-n junction(s), a bias electrical field is reversely applied to the p-n junction, so that uni-polarly charged nanoparticles are laterally confined on the substrate by a balance of electrostatic, van der Waals and image forces and are deposited on a respective p-doped or n-doped regions of the p-n junction when the applied electric field reaches a predetermined strength. The novel controllable deposition of nanoparticles employs commonly used substrate architectures for the patterning of an electric field attracting or repelling nanoparticles to the substrates and offers the opportunity to create a variety of sophisticated electric field patterns which may be used to direct particles with greater precision.Type: GrantFiled: February 24, 2006Date of Patent: August 24, 2010Assignee: University of MarylandInventors: Michael R. Zachariah, De-Hao Tsai, Raymond J. Phaneuf, Timothy D. Corrigan, Soo H. Kim
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Patent number: 7767538Abstract: It is made possible to form a silicon nitride film, an aluminum oxide film and a transition metal high-k insulation film of high quality. A manufacturing method includes: forming an insulation film having at least one kind of bonds selected out of silicon-nitrogen bonds, aluminum-oxygen bonds, transition metal-oxygen-silicon bonds, transition metal-oxygen-aluminum bonds, and transition metal-oxygen bonds on either a film having a semiconductor as a main component or a semiconductor substrate, and irradiating the insulation film with pulse infrared light having a wavelength corresponding to a maximum intensity in a wavelength region depending upon the insulation film and having a wavelength absorbed by the insulation film.Type: GrantFiled: August 21, 2006Date of Patent: August 3, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hirotaka Nishino, Koichi Kato
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Patent number: 7745809Abstract: Embodiments of the present invention provide an apparatus comprising a substrate comprising an emitter layer and at least one emitter interface adjacent to the emitter layer, and a metal protective layer on a top surface of the at least one emitter interface. A method of manufacturing such an apparatus is also disclosed. The method may include performing plasma nitridation directed at column micro-trench strips. Other embodiments are also described.Type: GrantFiled: April 3, 2008Date of Patent: June 29, 2010Assignee: Marvell International Ltd.Inventors: Pantas Sutardja, Albert Wu, Chien-Chuan Wei, Runzi Chang, Winston Lee, Peter Lee
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Patent number: 7727912Abstract: A method light enhanced atomic layer deposition for forming a film on a substrate. The method includes disposing the substrate in a process chamber of a light enhanced atomic layer deposition (LEALD) system configured to perform a LEALD process; and depositing a film on the substrate using the LEALD process, where the depositing includes (a) exposing the substrate to a first process material, (b) exposing the substrate to a second process material containing a reducing agent and irradiating the substrate with a first light radiation having either no or at least partial temporal overlap with the exposing of the substrate to the second process material, (c) repeating steps (a) and (b) until the desired film has been deposited. According to one embodiment of the invention, the deposited film can be a TaCN film or a TaC film.Type: GrantFiled: March 20, 2006Date of Patent: June 1, 2010Assignee: Tokyo Electron LimitedInventors: Tadahiro Ishizaka, Frank M. Cerio, Jr., Jacques Faguet
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Patent number: 7723241Abstract: According to the present invention, when a nitridation process by plasma generated by a microwave is applied to a substrate with an oxide film having been formed thereon to form an oxynitride film, the microwave is intermittently supplied. By the intermittent supply of the microwave, ion bombardment is reduced in accordance with a decrease in electron temperature, and a diffusion velocity of nitride species in the oxide film lowers, which as a result makes it possible to prevent nitrogen from concentrating in a substrate-side interface of an oxynitride film to increase the nitrogen concentration therein. Consequently, it is possible to improve quality of the oxynitride film, resulting in a reduced leakage current, an improved operating speed, and improved NBTI resistance.Type: GrantFiled: September 1, 2006Date of Patent: May 25, 2010Assignee: Tokyo Electron LimitedInventors: Seiji Matsuyama, Toshio Nakanishi, Shigenori Ozaki, Hikaru Adachi, Koichi Takatsuki, Yoshihiro Sato
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Patent number: 7723205Abstract: There is provided a semiconductor device, in which characteristics of the semiconductor device are improved by thinning a gate insulating film and a leak current can be reduced, and a manufacturing method thereof. An aluminum film which is a metal film is formed over a polycrystalline semiconductor film, and plasma oxidizing treatment is performed to the aluminum film, whereby an aluminum oxide film is formed by oxidizing the aluminum film, and a silicon oxide film is formed between the polycrystalline semiconductor film and the aluminum oxide film.Type: GrantFiled: September 14, 2006Date of Patent: May 25, 2010Assignee: Semiconductor Energy Laboratory Co., LtdInventor: Tetsuya Kakehata
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Publication number: 20100124825Abstract: A Cl2 gas plasma is generated at a site within a chamber between a substrate and a metal member. The metal member is etched with the Cl2 gas plasma to form a precursor. A nitrogen gas is excited in a manner isolated from the chamber accommodating the substrate. A metal nitride is formed upon reaction between excited nitrogen and the precursor, and formed as a film on the substrate. After film formation of the metal nitride, a metal component of the precursor is formed as a film on the metal nitride on the substrate. In this manner, a barrier metal film with excellent burial properties and a very small thickness is produced at a high speed, with diffusion of metal being suppressed and adhesion to the metal being improved.Type: ApplicationFiled: January 26, 2010Publication date: May 20, 2010Applicant: CANON ANELVA CORPORATIONInventors: Hitoshi Sakamoto, Naoki Yahata, Ryuichi Matsuda, Yoshiyuki Ooba, Toshihiko Nishimori
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Publication number: 20100105215Abstract: An insulting film is modified by subjecting the insulting film to a modification treatment comprising a combination of a plasma treatment and a thermal annealing treatment. There is provided a method of enhancing the characteristic of an insulating film by improving deterioration in the characteristic of the insulating film due to carbon, a suboxide, a dangling bond or the like contained in the insulating film.Type: ApplicationFiled: December 7, 2009Publication date: April 29, 2010Applicant: TOKYO ELECTRON LIMITEDInventors: Takuya SUGAWARA, Yoshihide TADA, Genji NAKAMURA, Shigenori OZAKI, Toshio NAKANISHI, Masaru SASAKI, Seiji MATSUYAMA, Kazuhide HASEBE, Shigeru NAKAJIMA, Tomonori FUJIWARA
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Publication number: 20100081290Abstract: A method of forming a gate dielectric layer includes forming a first dielectric layer over a semiconductor substrate using a first plasma, performing a first in-situ plasma nitridation of the first dielectric layer to form a first nitrided dielectric layer, forming a second dielectric layer over the first dielectric layer using a second plasma, performing a second in-situ plasma nitridation of the second dielectric layer to form a second nitrided dielectric layer; and annealing the first nitrided dielectric layer and the second nitrided dielectric layer, wherein the gate dielectric layer comprises the first nitrided dielectric layer and the second nitrided dielectric layer. In other embodiments, the steps of forming a dielectric layer using a plasma and performing an in-situ plasma nitridation are repeated so that more than two nitrided dielectric layers are formed and used as the gate dielectric layer.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Inventors: Tien Ying Luo, Olubunmi O. Adetutu
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Patent number: 7682973Abstract: A method of forming a Carbon NanoTube (CNT) structure and a method of manufacturing a Field Emission Device (FED) using the method of forming a CNT structure includes: forming an electrode on a substrate, forming a buffer layer on the electrode, forming a catalyst layer in a particle shape on the buffer layer, etching the buffer layer exposed through the catalyst layer, and growing CNTs from the catalyst layer formed on the etched buffer layer.Type: GrantFiled: January 23, 2007Date of Patent: March 23, 2010Assignee: Samsung SDI Co., Ltd.Inventors: Ha-Jin Kim, In-Taek Han, Young-Chul Choi, Kwang-Seok Jeong
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Patent number: 7678672Abstract: A device and method associated with carbon nanowires, such as single walled carbon nanowires having a high degree of alignment are set forth herein. A catalyst layer is deposited having a predetermined crystallographic configuration so as to control a growth parameter, such as an alignment direction, a diameter, a crystallinity and the like of the carbon nanowire. The catalyst layer is etched to expose a sidewall portion. The carbon nanowire is nucleated from the exposed sidewall portion. An electrical circuit device can include a single crystal substrate, such as Silicon, and a crystallographically oriented catalyst layer on the substrate having an exposed sidewall portion. In the device, carbon nanowires are disposed on the single crystal substrate aligned in a direction associated with the crystallographic properties of the catalyst layer.Type: GrantFiled: January 16, 2007Date of Patent: March 16, 2010Assignee: Northrop Grumman Space & Mission Systems Corp.Inventors: Vincent Gambin, Roger Su-Tsung Tsai
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Patent number: 7655574Abstract: An insulting film is modified by subjecting the insulting film to a modification treatment comprising a combination of a plasma treatment and a thermal annealing treatment. There is provided a method of enhancing the characteristic of an insulating film by improving deterioration in the characteristic of the insulating film due to carbon, a suboxide, a dangling bond or the like contained in the insulating film.Type: GrantFiled: November 30, 2005Date of Patent: February 2, 2010Assignee: Tokyo Electron LimitedInventors: Takuya Sugawara, Yoshihide Tada, Genji Nakamura, Shigenori Ozaki, Toshio Nakanishi, Masaru Sasaki, Seiji Matsuyama, Kazuhide Hasebe, Shigeru Nakajima, Tomonori Fujiwara
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Publication number: 20100015814Abstract: MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor material is forced lower into the stress-inducing layer. The stress-inducing layer may be either a recessed region or non-recessed region. A first method involves forming a stress-inducing layer, such as SiGe, in the source/drain regions and performing a nitridation or oxidation process. A nitride or oxide film is formed in the top portion of the stress-inducing layer, forcing the Ge lower into the stress-inducing layer. Another method embodiment involves forming a reaction layer over the stress-inducing layer and performing a treatment process to cause the reaction layer to react with the stress-inducing layer.Type: ApplicationFiled: July 21, 2008Publication date: January 21, 2010Inventors: Chien-Hao Chen, Pang-Yen Tsai, Chie-Chien Chang, Tze-Liang Lee, Shih-Chang Chen
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Patent number: 7645647Abstract: A thin film transistor includes a multi-coaxial silicon nanowire unit including a plurality of coaxial silicon nanowires on a substrate, the multi-coaxial silicon nanowire unit including a central portion and end portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain electrode on the respective end portions, respectively, so as to electrically connect to the multi-coaxial silicon nanowire unit.Type: GrantFiled: April 4, 2006Date of Patent: January 12, 2010Assignee: LG. Display Co., Ltd.Inventors: Gee-Sung Chae, Mi-Kyung Park
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Publication number: 20090302401Abstract: An integrated circuit having a substrate on which first and second active regions are defined. The first active region comprises a first transistor and the second active region comprises a second transistor having a first type stress. A barrier layer is provided over the substrate to reduce outdiffusion of dopants in the first active region.Type: ApplicationFiled: June 5, 2008Publication date: December 10, 2009Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Lee Wee TEO, Jae Gon LEE, Shyue Seng TAN, Elgin QUEK
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Publication number: 20090280650Abstract: Methods of depositing and curing a dielectric material on a substrate are described. The methods may include the steps of providing a processing chamber partitioned into a first plasma region and a second plasma region, and delivering the substrate to the processing chamber, where the substrate occupies a portion of the second plasma region. The methods may further include forming a first plasma in the first plasma region, where the first plasma does not directly contact with the substrate, and depositing the dielectric material on the substrate to form a dielectric layer. One or more reactants excited by the first plasma are used in the deposition of the dielectric material. The methods may additional include curing the dielectric layer by forming a second plasma in the second plasma region, where one or more carbon-containing species is removed from the dielectric layer.Type: ApplicationFiled: September 15, 2008Publication date: November 12, 2009Applicant: Applied Materials, Inc.Inventors: Dmitry Lubomirsky, Qiwei Liang, Jang Gyoo Yang
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Publication number: 20090275212Abstract: A semiconductor wafer implanted with impurities is loaded into a chamber. After oxygen gas is introduced around the semiconductor wafer, the semiconductor wafer is irradiated with a flash of light from flash lamps for an irradiation time not shorter than 0.1 milliseconds and not longer than 100 milliseconds, to thereby momentarily raise the surface temperature of the semiconductor wafer up to not lower than 800° C. and not higher than 1300° C. Since the temperature rises in an extremely short time, it is possible to activate the impurities while suppressing thermal diffusion thereof. Further, since an extremely thin oxide film is formed on a surface of the semiconductor wafer, this film serves as a protection film in a subsequent cleaning process, to prevent removal of the impurities.Type: ApplicationFiled: March 16, 2009Publication date: November 5, 2009Inventor: Shinichi KATO
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Patent number: 7611949Abstract: A method of fabricating a metal-oxide-semiconductor (MOS) transistor is provided. First, a patterned hard mask layer with an opening therein is formed over the substrate. A spacer is formed on the sidewall of the patterned hard mask layer in the opening. An isotropic etching process is performed on the substrate to form a recess in the substrate. An ion implant process is performed on the substrate in the lower portion of the recess using oxidation-restrained ions. The spacer is removed. Then, a thermal process is performed to form a gate oxide layer on the surface of the substrate within the recess such that the gate oxide layer in the upper portion of the recess is thicker than that in the lower portion of the recess.Type: GrantFiled: July 13, 2006Date of Patent: November 3, 2009Assignee: ProMOS Technologies, Inc.Inventors: San-Jung Chang, Jim Lin
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Publication number: 20090269940Abstract: In a substrate nitriding method for nitriding a target substrate by allowing a nitrogen-containing plasma to act on silicon on a surface of the substrate in a processing chamber of a plasma processing apparatus, the nitridation by the nitrogen-containing plasma is performed by controlling a sheath voltage Vdc around the substrate to be less than or equal to about 3.5 eV. The sheath voltage Vdc is a potential difference Vp?Vf between a plasma potential Vp in a plasma generating region and a floating potential Vf of the substrate.Type: ApplicationFiled: March 28, 2006Publication date: October 29, 2009Applicant: TOKYO ELECTRON LIMITEDInventors: Minoru Honda, Toshio Nakanishi
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Patent number: 7605008Abstract: A method and apparatus for igniting a gas mixture into plasma using capacitive coupling techniques, shielding the plasma and other contents of the plasma reactor from the capacitively-coupled electric field, and maintaining the plasma using inductive coupling are provided. For some embodiments, the amount of capacitive coupling may be controlled after ignition of the plasma. Such techniques are employed in an effort to prevent damage to the surface of a substrate from excessive ion bombardment caused by the highly energized ions and electrons accelerated towards and perpendicular to the substrate surface by the electric field of capacitively-coupled plasma.Type: GrantFiled: April 2, 2007Date of Patent: October 20, 2009Assignee: Applied Materials, Inc.Inventors: Thai Cheng Chua, James P. Cruse, Cory Czarnik
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Patent number: 7589027Abstract: Provided is a method of manufacturing a semiconductor device. A first gate oxide layer is formed on a semiconductor substrate in which a core region and an input/output region are defined. The first gate oxide layer of the core region is selectively removed, and a second gate oxide layer is formed under the first gate oxide layer of the input/output region and on the semiconductor substrate of the core region. Nitrogen annealing is performed to form a nitrogen-rich oxide layer under the second gate oxide layer. An additional thermal process is performed to diffuse nitrogen segregated on an interface between the first gate oxide layer and the second gate oxide layer of the input/output region to a surface of the semiconductor substrate. Impurities generated during the additional thermal process are discharged to the outside.Type: GrantFiled: December 26, 2006Date of Patent: September 15, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Young Seong Lee
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Patent number: 7585773Abstract: A semiconductor device is provided wherein at least one offset spacer is reduced and a non-conformal stress liner is thereafter deposited. By depositing the non-conformal stress liner in accordance with the present invention in close stress proximity to the FET, the carrier mobility and the performance of said device is significantly enhanced. The present invention is her directed to a method of fabricating said semiconductor device.Type: GrantFiled: November 3, 2006Date of Patent: September 8, 2009Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd.Inventors: Sunfei Fang, Jun Jung Kim, Thomas Dyer
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Publication number: 20090124096Abstract: The present invention relates to a method of fabricating a flash memory device, the method of the present invention comprises the steps of forming a tunnel insulating layer on a semiconductor substrate through a plasma oxidation process and performing a nitridation treatment to a surface of the tunnel insulating layer.Type: ApplicationFiled: June 28, 2008Publication date: May 14, 2009Applicant: Hynix Semiconductor Inc.Inventors: Jae Hyoung Koo, Kwon Hong, Jae Hong Kim, Eun Shil Park
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Patent number: 7485516Abstract: A method of formation of integrated circuit devices includes forming a gate electrode stack over a portion of a semiconductor. The stack includes a gate dielectric layer with a gate electrode thereabove. Implant diatomic nitrogen and/or nitrogen atoms into the substrate aside from the stack at a maximum energy less than or equal to 10 keV for diatomic nitrogen and at a maximum energy less than or equal to 5 keV for atomic nitrogen at a temperature less than or equal to 1000° C. for a time of less than or equal to 30 minutes. Then form silicon oxide offset spacers on sidewalls of the stack. Form source/drain extension regions in the substrate aside from the offset spacers. Form nitride sidewall spacers on outer surfaces of the offset spacers over another portion of the nitrogen implanted layer. Then form source/drain regions in the substrate aside from the sidewall spacers.Type: GrantFiled: November 21, 2005Date of Patent: February 3, 2009Assignee: International Business Machines CorporationInventors: Thomas W. Dyer, Jinhong Li, Zhijiong Luo
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Patent number: 7423312Abstract: The present invention provides an apparatus and method for a non-volatile memory comprising at least one array of memory cells with shallow trench isolation (STI) regions between bit lines for increased process margins. Specifically, in one embodiment, each of the memory cells in the array of memory cells includes a source, a control gate, and a drain, and is capable of storing at least one bit. The array of memory cells further includes word lines that are coupled to control gates of memory cells. The word lines are arranged in rows in the array. In addition, the array comprises bit lines coupled to source and drains of memory cells. The bit lines are arranged in columns in the array. Also, the array comprises at least one row of bit line contacts for providing electrical conductivity to the bit lines. Further, the array comprises shallow trench isolation (STI) regions separating each of the bit lines along the row of bit line contacts.Type: GrantFiled: July 20, 2004Date of Patent: September 9, 2008Assignee: Spansion LLCInventor: Satoshi Torii
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Publication number: 20080200039Abstract: The invention is directed to a nitridation process for a wafer. The nitridation process comprises steps of disposing the wafer on a top surface of a chuck in a nitridation process tool, wherein a plurality of concentric pipe coils is disposed close to the bottom surface of the chuck. Then, the chuck is heated and the chuck is regionally cooling down by applying a coolant into the concentric pipe coils, wherein the flow rates of the coolant in the concentric pipe coils are different from each other. Furthermore, a plasma nitridation process is performed on the wafer.Type: ApplicationFiled: February 16, 2007Publication date: August 21, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wenshen Li, Chien-Kee Pang, Ching-Yang Wen, Teng-Ming Hoong
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Patent number: 7413966Abstract: A method of forming a polycrystalline silicon active layer for use in a thin film transistor is provided. The method includes forming a buffer layer over a substrate, forming an amorphous silicon layer over the buffer layer, applying a catalytic metal to a surface of the amorphous silicon layer, crystallizing the amorphous silicon layer having the catalytic metal thereon into a polycrystalline silicon layer, annealing the polycrystalline silicon layer in an N2 gas atmosphere to stabilize the polycrystalline silicon layer, etching a surface of the polycrystalline silicon layer using an etchant, and patterning the polycrystalline silicon layer to form an island-shaped active layer.Type: GrantFiled: December 6, 2002Date of Patent: August 19, 2008Assignee: LG Phillips LCD Co., LtdInventors: Binn Kim, Jong-Uk Bae, Hae-Yeol Kim
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Patent number: 7410899Abstract: Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.Type: GrantFiled: September 20, 2005Date of Patent: August 12, 2008Assignee: Enthone, Inc.Inventors: Qingyun Chen, Charles Valverde, Vincent Paneccasio, Nicolai Petrov, Daniel Stritch, Christian Witt, Richard Hurtubise
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Publication number: 20080182426Abstract: A method for growing a nitride semiconductor has a first step for forming a surface reformation layer on a sapphire substrate, a second step for raising a temperature of the sapphire substrate with the surface reformation layer formed thereon up to a growth temperature of the nitride semiconductor in an atmosphere including ammonia, and a third step for growing a nitride semiconductor layer on a surface of the surface reformation layer. Alternatively, the second step is conducted in an atmosphere including an inert gas, or an atmosphere including the inert gas and hydrogen at a concentration of 10% or less relative to the inert gas.Type: ApplicationFiled: December 12, 2007Publication date: July 31, 2008Applicant: HITACHI CABLE, LTD.Inventor: Hajime Fujikura