Using Electromagnetic Or Wave Energy Patents (Class 438/776)
  • Patent number: 6660657
    Abstract: The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: December 9, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, John T. Moore, Neal R. Rueger
  • Publication number: 20030224616
    Abstract: A semiconductor device producing method using a plasma processing apparatus including a processing chamber, a substrate-supporting body which supports a substrate in the processing chamber, and a cylindrical electrode and a magnetic lines of force-forming member disposed around the processing chamber, comprises forming an oxide film on the substrate, and thereafter, by changing a high frequency impedance of the substrate-supporting body, continuously forming an oxynitride film by nitriding the oxide film by activated species of nitrogen which are activated by plasma.
    Type: Application
    Filed: March 26, 2003
    Publication date: December 4, 2003
    Inventors: Unryu Ogawa, Naoya Yamakado, Tadashi Terasaki, Shinji Yashima
  • Publication number: 20030224620
    Abstract: A method and an apparatus for smoothing surfaces on an atomic scale. The invention performs smoothing of surfaces by use of a low energy ion or neutral noble gas beam, which may be formed in an ion source or a remote plasma source. The smoothing process may comprise a post-deposition atomic smoothing step (e.g., an assist smoothing step) in a multilayer fabrication procedure. The invention utilizes combinations of relatively low particle energy (e.g., below the sputter threshold of the material) and near normal incidence angles, which achieve improved smoothing of a surface on an atomic scale with substantially no etching of the surface.
    Type: Application
    Filed: May 31, 2002
    Publication date: December 4, 2003
    Inventors: Jacques C.S. Kools, Adrian J. Devasahayam
  • Patent number: 6653184
    Abstract: The invention encompasses a method of forming an oxide region over a semiconductor substrate. A nitrogen-containing layer is formed across at least some of the substrate. After the nitrogen-containing layer is formed, an oxide region is grown from at least some of the substrate. The nitrogen of the nitrogen-containing layer is dispersed within the oxide region. The invention also encompasses a method of forming a pair of transistors associated with a semiconductor substrate. A substrate is provided. A first region of the substrate is defined, and additionally a second region of the substrate is defined. A first oxide region is formed which covers at least some of the first region of the substrate, and which does not cover any of the second region of the substrate. A nitrogen-comprising layer is formed across at least some of the first oxide region and across at least some of the second region of the substrate.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: November 25, 2003
    Assignee: Micron Technology, Inc.
    Inventor: John T. Moore
  • Publication number: 20030207592
    Abstract: A method of forming a capacitor includes forming first and second capacitor electrodes over a substrate. A capacitor dielectric region is formed intermediate the first and second capacitor electrodes, and includes forming a silicon nitride comprising layer over the first capacitor electrode. A silicon oxide comprising layer is formed over the silicon nitride comprising layer. The silicon oxide comprising layer is exposed to an activated nitrogen species generated from a nitrogen-containing plasma effective to introduce nitrogen into at least an outermost portion of the silicon oxide comprising layer. Silicon nitride is formed therefrom effective to increase a dielectric constant of the dielectric region from what it was prior to said exposing. Capacitors and methods of forming capacitor dielectric layers are also disclosed.
    Type: Application
    Filed: April 17, 2003
    Publication date: November 6, 2003
    Inventors: John T. Moore, Scott J. DeBoer
  • Patent number: 6620702
    Abstract: Methods are presented for reducing the thermal budget in a semiconductor manufacturing process that include for instance, depositing high dielectric constant films to form MIS capacitors, where processes including plasma nitridation and oxidation and deposition processes including ALD and PVD are selectively employed to lower the overall thermal budget thereby allowing smaller structures to be reliably manufactured.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: September 16, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wong-Cheng Shih, Lan-Lin Chao
  • Patent number: 6610614
    Abstract: A method of forming an ultra-thin dielectric layer, including the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: August 26, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Sunil Hattangady, Rajesh Khamankar
  • Patent number: 6610615
    Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes nitridizing a thin silicon oxide film in a low power, direct plasma formed from nitrogen. A gas having a lower ionization energy than nitrogen, such as for example, helium, may be used in combination with nitrogen to produce a lower power plasma resulting in a steeper concentration curve for nitrogen in the silicon oxide film.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: August 26, 2003
    Assignee: Intel Corporation
    Inventors: Robert McFadden, Jack Kavalieros, Reza Arghavani, Doug Barlage, Robert Chau
  • Patent number: 6610613
    Abstract: The invention grows SiO2 and silicon nitride films over silicon at temperatures in a range of room temperature to 700° C. The lower temperature oxidation is made possible by creation of reactive oxygen species and by supplying photon energy, ion energy or electron energy to a gas mixture containing noble gas(es) and oxidizing gas(es). It is also possible to fabricate silicon nitride films by supplying energy through photons, ions or electrons to a gas mixture containing noble gas(es) and nitridizing gas(es).
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: August 26, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Ramesh H. Kakkad
  • Publication number: 20030157773
    Abstract: A method for manufacturing a semiconductor device includes forming a first layer adjacent a semiconductor substrate. The first layer may comprise oxygen. The first layer may be subjected to a material comprising nitrogen to form a second layer. The second layer may be oxidized to form a dielectric layer which may have a relatively uniform nitrogen profile. Rapid thermal oxidation may be used to form the dielectric layer. The dielectric layer may have a physical thickness greater than a physical thickness of the second layer.
    Type: Application
    Filed: March 13, 2003
    Publication date: August 21, 2003
    Inventors: Jerry Hu, Paul E. Nicollian, Kwame N. Eason, Rajesh Khamankar, Mark S. Rodder, Sunil Hattangady
  • Publication number: 20030157771
    Abstract: A method of forming an ultra-thin gate dielectric by soft nitrogen-containing plasma. The method comprises a pre-nitridation step nitrifying a substrate surface by soft nitrogen-containing plasma, and a thermal oxidation step oxidizing the substrate surface to form an ultra-thin gate dielectric on the substrate surface. The plasma density of the soft nitrogen-containing plasma is about 109-1013 cm−3.
    Type: Application
    Filed: February 20, 2002
    Publication date: August 21, 2003
    Inventors: Tuung Luoh, Hans Lin, Yaw-Lin Hwang
  • Patent number: 6583064
    Abstract: A plasma processing chamber having a chamber liner and a liner support, the liner support including a flexible wall configured to surround an external surface of the chamber liner, the flexible wall being spaced apart from the wall of the chamber liner. The apparatus can include a heater thermally connected to the liner support so as to thermally conduct heat from the liner support to the chamber liner. The liner support can be made from flexible aluminum material and the chamber liner comprises a ceramic material. The flexible wall can include slots which divide the liner support into a plurality of fingers which enable the flexible wall to absorb thermal stresses.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: June 24, 2003
    Assignee: Lam Research Corporation
    Inventors: Thomas E. Wicker, Robert A. Maraschin, William S. Kennedy
  • Publication number: 20030080389
    Abstract: A method for manufacturing a semiconductor device includes forming a first layer adjacent a semiconductor substrate. The first layer may comprise oxygen. The first layer may be subjected to a material comprising nitrogen to form a second layer. The second layer may be oxidized to form a dielectric layer which may have a relatively uniform nitrogen profile. Rapid thermal oxidation may be used to form the dielectric layer. The dielectric layer may have a physical thickness greater than a physical thickness of the second layer.
    Type: Application
    Filed: October 31, 2001
    Publication date: May 1, 2003
    Inventors: Jerry Hu, Kwame N. Eason, Rajesh Khamankar, Mark S. Rodder, Paul E. Nicollian, Sunil Hattangady
  • Patent number: 6555485
    Abstract: This invention relates to a method for forming a gate dielectric layer, and, more particularly, to a method for treating a base oxide layer by using a remote plasma nitridation procedure and a thermal annealing treatment in turn to form the gate dielectric layer. The first step of the present invention is to form a base oxide layer on a substrate of a wafer. The base oxide layer can be formed using any kind of method. Then nitrogen ions are introduced into the base oxide layer using the remote plasma nitridation procedure to form a remote plasma nitrided oxide layer. Finally, the wafer is placed in a reaction chamber which comprises oxygen (O2) or nitric monoxide (NO) to treat the remote plasma nitrided oxide layer using the thermal annealing procedure and the gate dielectric layer of the present invention is formed.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: April 29, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Chuan-Hsi Liu, Hsiu-Shan Lin, Yu-Yin Lin, Tung-Ming Pan, Kuo-Tai Huang
  • Patent number: 6551914
    Abstract: A semiconductor device in which an interconnection material is buried in a hole formed in an interlevel insulating film arranged on a semiconductor substrate includes a protective layer formed on the surface of the interlevel insulating film that has a lower polishing rate than that of the interconnection material in chemical mechanical polishing. A method of manufacturing this semiconductor device is also disclosed.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: April 22, 2003
    Assignee: NEC Electronics Corporation
    Inventors: Mieko Suzuki, Akira Kubo
  • Patent number: 6541356
    Abstract: A method of forming a silicon-on-insulator (SOI) substrate having a buried oxide region that has a greater content of thermally grown oxide as compared to oxide formed by implanted oxygen ions is provided. Specifically, the inventive SOI substrate is formed by utilizing a method wherein oxygen ions are implanted into a surface of a Si-containing substrate that includes a sufficient Si thickness to allow for subsequent formation of a buried oxide region in the Si-containing substrate which has a greater content of thermally grown oxide as compared to oxide formed by the implanted oxygen ions followed by an annealing step.
    Type: Grant
    Filed: May 21, 2001
    Date of Patent: April 1, 2003
    Assignee: International Business Machines Corporation
    Inventors: Keith E. Fogel, Maurice H. Norcott, Devendra K. Sadana
  • Patent number: 6537927
    Abstract: A method and apparatus for heat-treating a semiconductor substrate to heat different areas of the substrate at different temperatures. The method includes using an apparatus having a chamber of a refractory material; a support plate located at a lower side in the chamber for supporting the semiconductor substrate; a heating device disposed at an upper side in the chamber; and, a heat resistance mask provided between the support plate and fabricated to have different heat transmission rates therein.
    Type: Grant
    Filed: June 3, 1999
    Date of Patent: March 25, 2003
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Jeong Hwan Son
  • Patent number: 6534421
    Abstract: The invention grows SiO2 films over silicon at temperatures as low as room temperature and at pressures as high as 1 atmosphere. The lower temperature oxidation is made possible by creation of oxygen atoms and radicals by adding noble gas(es) along with oxidizing gas(es) and applying RF power to create plasma. The invention also fabricates silicon nitride films by flowing nitrogen containing gas(es) with noble gas(es) and applying RF power to create plasma at pressures as high as one atmosphere. In addition, the above processes can also be performed using microwave power instead of RF power to create plasma.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: March 18, 2003
    Assignee: Seiko Epson Corporation
    Inventor: Ramesh H. Kakkad
  • Patent number: 6528434
    Abstract: The present invention provides a method of forming different thickness” of a gate oxide layer simultaneously, by employing a pulse Nitrogen plasma implantation. The method provides a semiconductor substrate with the surface of the silicon in the semiconductor substrate separated into a first region and a second region at least. Then a thin surface on the surface of the silicon of the first region is implanted using a first predetermined concentration of the Nitrogen ions. The thin surface on the surface of the silicon in the second region is implanted using a second predetermined concentration of the Nitrogen ions. An oxidation process is subsequently performed. The first predetermined thickness and the second predetermined thickness of the silicon oxide layer are formed simultaneously on the surface of the silicon in the first region and in the second region. The Nitrogen ions are implanted in the surface of the silicon by forming the pulse nitrogen plasma in-situ.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: March 4, 2003
    Assignee: Macronix International Co. Ltd.
    Inventor: Wei-Wen Chen
  • Patent number: 6518203
    Abstract: The present invention describes a method of processing a substrate. According to the present invention a dielectric layer is formed on the substrate. The dielectric layer is then exposed in a first chamber to activated nitrogen atoms formed in a second chamber to form a nitrogen passivated dielectric layer. A metal nitride film is then formed on the nitrogen passivated dielectric layer.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: February 11, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Pravin Narwankar, Turgut Sahin
  • Patent number: 6503846
    Abstract: An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% O2); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: January 7, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, James J. Chambers, Rajesh Khamankar, Douglas T. Grider
  • Patent number: 6486062
    Abstract: A nickel silicide layer is formed on a semiconductor device having a crystalline silicon source/drain region doped with arsenic. Arsenic is doped into the crystalline silicon, by implantation, for example, so that the concentration of arsenic is slightly below the surface of the silicon. Annealing restores the crystalline structure of the silicon after implantation of the arsenic. Amorphous silicon is selectively deposited over the source/drain regions and over the top of the gate electrode. Nickel is deposited over the entire semiconductor device and a second anneal reacts the nickel with the amorphous silicon. The second anneal is timed so that the nickel reacts with the amorphous silicon, and does not substantially react with the silicon source/drain regions containing arsenic. Preventing the nickel from substantially reacting with the silicon source/drain regions containing arsenic provides a smooth interface between the resulting nickel silicide and the silicon source/drain regions doped with arsenic.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: November 26, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: George J. Kluth, Matthew S. Buynoski
  • Publication number: 20020173166
    Abstract: An in-process microelectronic device may be treated by providing a process chamber with an in-process microelectronic device therein, providing an ozone generator and an ozone storage reservoir, the ozone storage reservoir in fluid communication with the ozone generator and the process chamber, generating ozone with the ozone generator for a first period of time and delivering the ozone to the ozone storage reservoir; and subsequently providing ozone from the ozone storage reservoir and the generator to the process chamber during a second period of time different from the first period of time and exposing the in-process microelectronic device thereto.
    Type: Application
    Filed: April 11, 2001
    Publication date: November 21, 2002
    Inventors: Kurt Christenson, Steven L. Nelson
  • Patent number: 6475928
    Abstract: The process comprises the following steps: a) pretreatment of a surface of the substrate by means of a cold gas plasma at low or medium pressure in order to clean the said surface; b) growth, from the said cleaned surface of the substrate, of a nitride barrier layer by means of a cold gas plasma made up of an N2/H2 mixture at low or medium pressure; and c) deposition, on the nitride barrier layer, of a Ta2O5 dielectric layer by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD).
    Type: Grant
    Filed: July 15, 1998
    Date of Patent: November 5, 2002
    Assignee: France Telecom
    Inventors: Marc Berenguer, Roderick Devine
  • Publication number: 20020160623
    Abstract: In this disclosure, we present processes of growing SiO2 films over silicon at temperatures as low as room temperature and at pressures as high as 1 atmosphere. The lower temperature oxidation was made possible by creation of oxygen atoms and radicals by adding noble gas(es) along with oxidizing gas(es) and applying RF power to create plasma. It was also possible to fabricate silicon nitride films by flowing nitrogen containing gas(es) with noble gas(es) and applying RF power to create plasma at pressures as high as one atmosphere. In addition, the above processes could also be carried out using microwave power instead of RF power to create plasma.
    Type: Application
    Filed: August 27, 2001
    Publication date: October 31, 2002
    Inventor: Ramesh H. Kakkad
  • Publication number: 20020098713
    Abstract: A cluster tool system having a computer memory. The memory has a variety of codes for operating a plasma immersion ion implantation chamber. In some embodiments, the cluster tool method also includes computer codes for a controlled cleaving process chamber, as well as others.
    Type: Application
    Filed: October 25, 2001
    Publication date: July 25, 2002
    Applicant: Francois J. Henley
    Inventors: Francois J. Henley, Nathan Cheung
  • Patent number: 6413881
    Abstract: A process for inhibiting the passage of dopant from a gate electrode into a thin gate oxide comprises nitridation of the upper surface of the thin gate oxide, prior to formation of the gate electrode over the gate oxide, to thereby form a barrier of nitrogen atoms in the upper surface region of the gate oxide adjacent the interface between the gate oxide and the gate electrode to inhibit passage of dopant atoms from the gate electrode into the thin gate oxide during annealing of the structure. In one embodiment, a selective portion of silicon oxide on a silicon substrate may be etched to thin the oxide to the desired thickness using a nitrogen plasma with a bias applied to the silicon substrate. Nitridation of the surface of the etched silicon oxide is then carried out in the same apparatus by removing the bias from the silicon substrate.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: July 2, 2002
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, John Haywood, James P. Kimball, Helmut Puchner, Ravindra Manohar Kapre, Nicholas Eib
  • Publication number: 20020076943
    Abstract: A method with which all semiconductor lasers can be used as products is provided by regulating reflectance variations of all the semiconductor laser end faces arranged in an electron beam deposition apparatus after completion of deposition to a predetermined range when semiconductor laser end faces are coated. An end face (3) that is placed at a position at which the film thickness is made relatively thicker than those of other coat batches due to the large flux of a deposition beam is inclined by an angle &bgr; to adjust the incident angle of the deposition beam. The relationship, actual film thickness (9b)=film thickness (9b) in direction of deposition beams central axis (8a)×cos &bgr;, is utilized to reduce the film thickness of the end face (3) to the predetermined range.
    Type: Application
    Filed: November 28, 2001
    Publication date: June 20, 2002
    Inventor: Masayuki Ohta
  • Patent number: 6395652
    Abstract: A method of manufacturing a thin film transistor, includes preparing a process chamber having a stage, providing a substrate on the stage of the process chamber, injecting a first mixed gas of NH3, N2 and SiH4 into the process chamber, forming a plasma in the process chamber and forming a silicon nitride film (SiNx) on the substrate, injecting a second mixed gas of H2 and SiH4 into the process chamber while removing the first mixed gas in the plasma state, forming a pure amorphous silicon film (a-Si:H) on the silicon nitride film using the second mixed gas, injecting a third mixed gas of H2, SiH4 and PH3 into the process chamber while removing the second mixed gas in the plasma state, and forming a doped amorphous silicon film (n+ a-Si:H) on the silicon nitride film using the second mixed gas.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: May 28, 2002
    Assignee: LG. Philips LCD Co., Ltd.
    Inventors: Cheol-Se Kim, Dong-Hee Kim, Myeung-Kyu Lee
  • Publication number: 20020055270
    Abstract: The present invention describes a method of processing a substrate. According to the present invention a dielectric layer is formed on the substrate. The dielectric layer is then exposed in a first chamber to activated nitrogen atoms formed in a second chamber to form a nitrogen passivated dielectric layer. A metal nitride film is then formed on the nitrogen passivated dielectric layer.
    Type: Application
    Filed: October 18, 2001
    Publication date: May 9, 2002
    Inventors: Pravin Narwankar, Turgut Sahin
  • Patent number: 6380104
    Abstract: A method for forming upon a semiconductor substrate employed within a microelectronics fabrication a composite gate insulating layer of MOS device comprising a silicon oxide dielectric layer and a high-K dielectric layer. The method employs thermal oxidation of a silicon semiconductor substrate to form an initial silicon oxide dielectric layer. A RPN plasma method is employed to form a layer of silicon nitride high-k dielectric material partly into the silicon oxide dielectric layer. The composite dielectric layer is dielectrically equivalent to the initial silicon oxide dielectric layer, with equivalent performance, reliability and manufacturability of the MOS device.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: April 30, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Mo-Chiun Yu
  • Patent number: 6368984
    Abstract: A method of forming an insulating film on a surface of a substrate includes the steps of heating the substrate in a processing chamber in an atmosphere containing water vapor maintained at 900° C. or higher to form a first insulating film on a surface of the substrate; and cooling down the substrate in the presence of water vapor to a temperature of 600° C. or less at a temperature decreasing rate of 15° C./sec or more so as to limit a thickness of a second insulating film formed at an interface between the first insulating film and the substrate.
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: April 9, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Tomita, Mamoru Takahashi, Yoshio Ozawa
  • Patent number: 6337289
    Abstract: The present invention describes a method of processing a substrate. According to the present invention a dielectric layer is formed on the substrate. The dielectric layer is then exposed in a first chamber to activated nitrogen atoms formed in a second chamber to form a nitrogen passivated dielectric layer. A metal nitride film is then formed on the nitrogen passivated dielectric layer.
    Type: Grant
    Filed: September 24, 1999
    Date of Patent: January 8, 2002
    Assignee: Applied Materials. Inc
    Inventors: Pravin Narwankar, Turgut Sahin
  • Patent number: 6331468
    Abstract: A process is described for using a silicon layer as an implant and out-diffusion layer, for forming defect-free source/drain regions in a semiconductor substrate, and also for subsequent formation of silicon nitride spacers. A nitrogen-containing dopant barrier layer is first formed over a single crystal semiconductor substrate by nitridating either a previously formed gate oxide layer, or a silicon layer formed over the gate oxide layer, to form a barrier layer comprising either a silicon, oxygen, and nitrogen compound or a compound of silicon and nitrogen. The nitridating may be carried out using a nitrogen plasma followed by an anneal. A polysilicon gate electrode is then formed over this barrier layer, and the exposed portions of the barrier layer remaining are removed. An amorphous silicon layer of predetermined thickness is then formed over the substrate and polysilicon gate electrode.
    Type: Grant
    Filed: May 11, 1998
    Date of Patent: December 18, 2001
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, Helmut Puchner, Ravindra A. Kapre, James P. Kimball
  • Patent number: 6331492
    Abstract: A method is disclosed for making gate oxides on a silicon wafer surface for multiple voltage applications comprising the steps of growing an oxide layer (12) on a wafer (10) surface, exposing the surface of the oxide layer (12) to a nitrogen ion containing plasma to form a nitrided layer (22). Next, a photoresist layer (14) is deposited over a portion of the oxide layer (12) and the isolation (30), followed by etching of the exposed nitrided layer 22 and a portion of the oxide layer (12) to create a thinner silicon dioxide layer (32). The photoresist layer (14) is removed, the wafer (10) is cleaned and then the thinner silicon dioxide layer (32) is removed prior to a final oxidation step to form a thinner silicon dioxide layer (34) having a different thickness than the silicon dioxide layer (12).
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: December 18, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: George R. Misium, Sunil V. Hattangady
  • Publication number: 20010046788
    Abstract: The invention grows SiO2 and silicon nitride films over silicon at temperatures in a range of room temperature to 700° C. The lower temperature oxidation is made possible by creation of reactive oxygen species and by supplying photon energy, ion energy or electron energy to a gas mixture containing noble gas(es) and oxidizing gas(es). It is also possible to fabricate silicon nitride films by supplying energy through photons, ions or electrons to a gas mixture containing noble gas(es) and nitridizing gas(es).
    Type: Application
    Filed: February 28, 2001
    Publication date: November 29, 2001
    Applicant: Seiko Epson Corporation
    Inventor: Ramesh Kakkad
  • Patent number: 6323097
    Abstract: A method and structure is disclosed to measure spacing and misalignment of features in semiconductor integrated circuits. Three equally spaced, parallel first level conductive lines are formed on a first insulating layer with staircase patterns projecting both out of and into the inner edges of the outer lines. A second insulating layer is deposited and step contact vias are opened through the second insulating layer over the steps of the staircase patterns. The inner edge of the step contact via coincides with the inner edge of the step. Contact pad vias are opened through the second insulating layer over the outer lines and the step contact vias and the contact pad vias are filled with conductive material. A second level conductive line is formed over the second insulating layer parallel to said first level conductive lines and above the central first level conductive line.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: November 27, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shien-Yang Wu, Tseng Chin Lo, Konrad Young
  • Patent number: 6316275
    Abstract: In a method for fabricating a semiconductor component, a first oxide layer is produced above a substrate. A capacitor is formed above the first oxide layer. The capacitor includes a bottom electrode and a top electrode and a metal-oxide-containing capacitor material layer deposited in between the electrodes. Prior to forming the capacitor, a plasma doping method is used to dope the first oxide layer with a barrier substance which builds up a hydrogen diffusion barrier in the first oxide layer.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: November 13, 2001
    Assignee: Infineon Technologies AG
    Inventor: Joachim Höpfner
  • Publication number: 20010021588
    Abstract: A method is disclosed for making gate oxides on a silicon wafer surface for multiple voltage applications comprising the steps of growing an oxide layer (12) on a wafer (10) surface, exposing the surface of the oxide layer (12) to a nitrogen ion containing plasma to form a nitrided layer (22). Next, a photoresist layer (14) is deposited over a portion of the oxide layer (12) and the isolation (30), followed by etching of the exposed nitrided layer 22 and a portion of the oxide layer (12) to create a thinner silicon dioxide layer (32). The photoresist layer (14) is removed, the wafer (10) is cleaned and then the thinner silicon dioxide layer (32) is removed prior to a final oxidation step to form a thinner silicon dioxide layer (34) having a different thickness than the silicon dioxide layer (12).
    Type: Application
    Filed: December 18, 1998
    Publication date: September 13, 2001
    Inventors: GEORGE R. MISIUM, SUNIL V. HATTANGADY
  • Patent number: 6287889
    Abstract: An improved gas phase synthesized diamond, CBN, BCN, or CN thin film having a modified region in which strain, defects, color and the like are reduced and/or eliminated. The thin film can be formed on a substrate or be a free-standing thin film from which the substrate has been removed. The thin film can be stably and reproducibly modified to have an oriented polycrystal structure or a single crystal structure. The thin film is modified by being subjected to and heated by microwave irradiation in a controlled atmosphere. The thin film has a modified region in which a line width of the diamond spectrum evaluated by Raman spectroscopy of 0.1 microns or greater is substantially constant along a film thickness direction of the thin film, and the line width of the modified region is 85% or less of a maximum line width of the residual portion of the film thickness.
    Type: Grant
    Filed: January 26, 2000
    Date of Patent: September 11, 2001
    Assignee: Applied Diamond, Inc.
    Inventors: Shoji Miyake, Shu-Ichi Takeda
  • Publication number: 20010016430
    Abstract: The present invention relates to a method of processing a semiconductor device and comprising the following steps of generating plasma in a processing chamber to form a thin film on a semiconductor device or to process a thin film formed on a semiconductor device, scanning a laser beam which intensity is modulated at a desired frequency inside the processing chamber where the semiconductor device is being processed by the plasma through a window. Receiving by a sensor through the window a back scattered light being scattered from fine particles suspended in said processing chamber by scanning the laser, detecting said desired frequency component from a signal outputted from the sensor, obtaining information from the detected desired frequency component relating to quantity, size and distribution of fine particles illuminated by said laser beam inside the processing chamber, and outputting said obtained information relating to quantity, size and distribution of the fine particles.
    Type: Application
    Filed: January 17, 2001
    Publication date: August 23, 2001
    Inventors: Hiroyuki Nakano, Toshihiko Nakata, Masayoshi Serizawa
  • Patent number: 6265327
    Abstract: Disclosed are a method and apparatus for forming an insulating film on the surface of a semiconductor substrate capable of improving the quality and electrical properties of the insulating film with no employment of high-temperature heating and with good controllability. After the surface of a silicon substrate is cleaned, a silicon dioxide film having a thickness of 1-20 nm is formed on the substrate surface. The silicon substrate is exposed to plasma generated by electron impact, while the silicon substrate is maintained at a temperature of 0° C. to 700° C. Thus, nitrogen atoms are incorporated into the silicon dioxide film, obtaining a modified insulating film having good electrical properties.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: July 24, 2001
    Assignees: Japan Science and Technology Corp., Matsushita Electronics Corp.
    Inventors: Hikaru Kobayashi, Kenji Yoneda
  • Patent number: 6251801
    Abstract: Disclosed is a method of manufacturing a semiconductor device, including the step of supplying an oxidizing gas and a nitriding gas onto one main surface of a semiconductor substrate while heating the substrate so as to oxynitride the surface region of the substrate, wherein the supplying step is performed such that the gaseous phase above the main surface of the substrate forms a first region having a substantially uniform temperature in a direction perpendicular to the main surface of the substrate and a second region interposed between the first region and the substrate and having a temperature gradient in a direction perpendicular to the main surface of the substrate such that the temperature is elevated toward the substrate, and the distance from the main surface of the substrate to the interface between the first and second regions is set at 9.5 cm or less.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: June 26, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuo Saki, Shuji Katsui
  • Patent number: 6235590
    Abstract: Techniques for fabricating integrated circuits having devices with gate oxides having different thicknesses and a high nitrogen content include forming the gate oxides at pressures at least as high as 2.0 atmospheres in an ambient of a nitrogen-containing gas. In one implementation, a substrate includes a first region for forming a first device having a gate oxide of a first thickness and a second region for forming a second device having a gate oxide of a second different thickness. A first oxynitride layer is formed on the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres. A portion of the first oxynitride layer is removed to expose a surface of the substrate on the second region. Subsequently, a second oxynitride is formed over the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres to form the first and second gate oxides.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: May 22, 2001
    Assignee: LSI Logic Corporation
    Inventors: David W. Daniel, Dianne G. Pinello, Michael F. Chisholm
  • Patent number: 6225167
    Abstract: A method is disclosed to form a plurality of oxides of different thicknesses with one step oxidation. In a first embodiment, a substrate is provided having a high-voltage cell area and a peripheral low-voltage logic area separated by a trench isolation region. The substrate is first nitrided. Then the nitride layer over the high-voltage area is removed, and the substrate is wet cleaned with HF solution. The substrate surface is next oxidized to form a tunnel oxide of desired thickness over the high-voltage. In a second embodiment, a sacrificial oxide is used over the substrate for patterning the high voltage cell area and the low-voltage logic area. The sacrificial oxide is removed from the low-voltage area and the substrate is nitrided after cleaning with a solution not containing HF, thus forming a nitride layer over the low-voltage area. Then, the sacrificial oxide is removed from the high-voltage area with an HF dip, and tunnel oxide of desired thickness is formed over the same area.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: May 1, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Mo-Chiun Yu, Wei-Ming Chen
  • Patent number: 6221792
    Abstract: A nitridization process to form a barrier layer on a substrate is described. The nitridization process includes depositing a layer of metal or metal silicide on a surface of the substrate, placing the substrate into a high density, low pressure plasma reactor, introducing into the high density low pressure plasma reactor a gas including nitrogen, and striking a plasma in the high density, low pressure plasma reactor under conditions that promote nitridization of at least a portion of the layer of metal or metal silicide to produce a composition of metal nitride or metal silicon nitride, respectively.
    Type: Grant
    Filed: June 24, 1997
    Date of Patent: April 24, 2001
    Assignee: Lam Research Corporation
    Inventors: Yun-Yen Jack Yang, Ching-Hwa Chen, Yea-Jer Arthur Chen
  • Patent number: 6177364
    Abstract: An interlayer dielectric for a damascene structure includes a first etch stop layer formed on a substrate. A first interlayer dielectric layer containing fluorine is formed on the first etch stop layer by deposition. A second etch stop layer is formed on the first interlayer dielectric layer. A second interlayer dielectric layer containing fluorine is formed on the second etch stop layer by deposition. The first and second interlayer dielectric layers and the first and second etch stop layers are etched to form at least one trench and at least one via. The at least one trench and the at least one via are treated with an H2/N2 plasma in-situ, wherein a fluorine-depleted region in the first and second interlayer dielectric layers is formed, and wherein a nitrided region is formed adjacent the fluorine-depleted region, with the nitrided region corresponding to a side surface of the at least one trench and the at least one via.
    Type: Grant
    Filed: December 2, 1998
    Date of Patent: January 23, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard J. Huang
  • Patent number: 6171977
    Abstract: A semiconductor wafer having an impurity diffusion layer formed in an inner surface of a trench is cleaned. The semiconductor wafer is inserted into a furnace, and NH3 gas is introduced into the furnace in the low-pressure condition to create an atmosphere in which the temperature is set at 800° C. to 1200° C. and the partial pressures of H2O and O2 are set at 1×10−4 Torr or less. A natural oxide film formed on the inner surface of the trench is removed, and substantially at the same time, a thermal nitride film is formed on the impurity diffusion layer. Then, a CVD silicon nitride film is formed on the thermal nitride film without exposing the thermal nitride film to the outside air in the same furnace. Next, a silicon oxide film is formed on the CVD nitride film. As a result, a composite insulative film formed of the thermal nitride film, CVD silicon nitride film and silicon oxide film is obtained. Then, an electrode for the composite insulative film is formed in the trench.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: January 9, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Kasai, Takashi Suzuki, Takanori Tsuda, Yuuichi Mikata, Hiroshi Akahori, Akihito Yamamoto
  • Patent number: 6140255
    Abstract: A method for depositing silicon nitride on a semiconductor wafer uses plasma enhanced chemical vapor deposition at very low temperatures. The temperature in a silicon nitride deposition chamber is set to be about 170.degree. C. or less. Silane gas (SiH.sub.4) flows into the silicon nitride deposition chamber with a flow rate in a range of from about 300 sccm (standard cubic cm per minute) to about 500 sccm. Nitrogen gas (N.sub.2) flows into the silicon nitride deposition chamber with a flow rate in a range of from about 500 sccm to about 2000 sccm. Ammonia gas (NH.sub.3) flows into the silicon nitride deposition chamber with a flow rate in a range of from about 1.0 slm to about 2.2 slm. A high frequency RF signal is applied on a showerhead within the deposition chamber. A low frequency RF signal is applied on a heating block for holding the semiconductor wafer.
    Type: Grant
    Filed: March 3, 1999
    Date of Patent: October 31, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Terri Jo Kitson, Khanh Nguyen
  • Patent number: 6136654
    Abstract: An embodiment of the instant invention is a method of forming a dielectric layer, the method comprising the steps of: providing a semiconductor substrate (substrate 12), the substrate having a surface; forming an oxygen-containing layer (layer 14) on the semiconductor substrate; and subjecting the oxygen-containing layer to a nitrogen containing plasma (plasma 16) so that the nitrogen is either incorporated into the oxygen-containing layer (see regions 18, 19, and 20) or forms a nitride layer at the surface of the substrate (region 22). Using this embodiment of the instant invention, the dielectric layer can be substantially free of hydrogen. Preferably, the oxygen-containing layer is an SiO.sub.2 layer or it is comprised of oxygen and nitrogen (preferably an oxynitride layer). The plasma is, preferably, a high-density plasma. Preferably, a source of nitrogen is introduced to the plasma to form the nitrogen containing plasma. The source of nitrogen is preferably comprised of a material consisting of: N.sub.
    Type: Grant
    Filed: December 4, 1997
    Date of Patent: October 24, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Kraft, Sunil Hattangady, Douglas T. Grider