Nitridation Patents (Class 438/775)
  • Patent number: 10290496
    Abstract: A substrate processing apparatus includes: a protrusion portion formed by a side peripheral wall of a processing container which swells outward, and configured to form a vertically elongated space communicating with a processing space for accommodating a substrate holder and performing a process; a gas discharge portion provided in the vertically elongated space, and configured to discharge a process gas into the processing space; an antenna provided in the protrusion portion along a vertical direction and supplied with a high-frequency power for converting the process gas into a plasma in the vertically elongated space; and a shield extending leftward and rightward in the protrusion portion at positions closer to the processing space than the antenna and configured to shield an electric field formed by the antenna and to suppress a formation of the plasma in the processing space.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: May 14, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jun Ogawa, Kazuo Yabe
  • Patent number: 9607908
    Abstract: Provided is a technique capable of uniformizing the characteristics of a film after a plurality of substrates are processed. A method of manufacturing a semiconductor device may include: (a) loading a substrate into a process chamber; (b) processing the substrate by performing: (b-1) supplying and exhausting a process gas into and from the process chamber without activating the process gas; (b-2) supplying and exhausting the process gas into and from the process chamber while activating the process gas; (b-3) measuring an amount of impurity desorbed from the substrate while performing (b-2); and (b-4) measuring a gas exhausted from the process chamber after performing (b-3); (c) calculating a process data based on: a first measurement data obtained by repeating (b-3); and a second measurement data obtained by repeating (b-4); and (d) determining whether to terminate (b) based on the process data.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: March 28, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC, INC.
    Inventor: Tsuyoshi Takeda
  • Patent number: 9330901
    Abstract: A method of forming a nitrogen-containing oxide film is disclosed. The method comprises (a) exposing a substrate to a first gas pulse having one of an oxygen-containing gas and a metal-containing gas; (b) exposing the substrate to a second gas pulse having the other of the oxygen-containing gas and the metal-containing gas to form an oxide film over the substrate; and (c) exposing the oxide film to a third gas pulse having a nitrogen-containing plasma to form a nitrogen-containing oxide film, wherein the nitrogen-containing oxide film has a nitrogen concentration between about 0.1 and about 3 atomic percent (at %).
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: May 3, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: An-Chun Tu, Chih-Hong Hwang, Yi Hsien Lu, Chun-Heng Chen, Chen-Chien Li, Chih-Jen Wu, Kuei-Shu Chang-Liao, Chen-Ming Huang
  • Patent number: 9318345
    Abstract: When forming strain-inducing dielectric material layers above transistors of different conductivity type, the patterning of at least one strain-inducing dielectric material may be accomplished on the basis of a process sequence in which a negative influence of a fluorine species in an oxygen plasma upon removing the resist mask is avoided or at least significantly suppressed. For example, a substantially oxygen-free plasma process may be applied for removing the resist material.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: April 19, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ronald Naumann, Volker Grimm, Andrey Zakharov, Ralf Richter
  • Patent number: 9218957
    Abstract: Embodiments of the present invention provide a thin film transistor, a manufacturing method thereof and a display device. The method for manufacturing the thin film transistor, comprising the following steps: providing a substrate; forming a semiconductor layer on the substrate; forming a gate insulating layer; and forming a gate electrode, wherein the gate insulating layer comprises a first gate insulating layer, the first gate insulating layer being formed by oxidizing a portion of the semiconductor layer, and the unoxidized portion of the semiconductor layer forming an active layer, and wherein the gate electrode is formed in such a way that the gate insulating layer is sandwiched between the gate electrode and the active layer.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: December 22, 2015
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yanzhao Li, Gang Wang, Li Sun, Shuang Guan
  • Patent number: 9184260
    Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. First sidewall spacers are formed adjacent to sidewalls of the gate electrode structure, and the first sidewall spacers include a nitride. An oxide etchant is applied to a surface of the semiconductor substrate after forming the first sidewall spacers. A second spacer material that includes a nitride is deposited over the semiconductor substrate and the first sidewall spacers to form a second spacer layer after applying the oxide etchant to the surface of the semiconductor substrate. The second spacer layer is etched with a second spacer etchant to form second sidewall spacers.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: November 10, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Joanna Wasyluk, Dominic Thurmer, Ardechir Pakfar, Markus Lenski
  • Patent number: 9166014
    Abstract: A gate structure is provided on a channel portion of a semiconductor substrate. The gate structure may include an electrically conducting layer present on a gate dielectric layer, a semiconductor-containing layer present on the electrically conducting layer, a metal semiconductor alloy layer present on the semiconductor-containing layer, and a dielectric capping layer overlaying the metal semiconductor alloy layer. In some embodiments, carbon and/or nitrogen can be present within the semiconductor-containing layer, the metal semiconductor alloy layer or both the semiconductor-containing layer and the metal semiconductor alloy layer. The presence of carbon and/or nitrogen within the semiconductor-containing layer and/or the metal semiconductor alloy layer provides stability to the gate structure. In another embodiment, a layer of carbon and/or nitrogen can be formed between the semiconductor-containing layer and the metal semiconductor alloy layer.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: October 20, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Nicolas L. Breil, Cyril Cabral, Jr., Martin M. Frank, Claude Ortolland
  • Patent number: 9099329
    Abstract: There is provided an In nanowire including a substrate, an indium thin film formed on the substrate, an insulating film formed on the indium thin film and having at least one through hole through formation of a pattern, and an In nanowire vertically protruded from the indium thin film through the at least one through hole.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: August 4, 2015
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hee Suk Chung, Gyu Seok Kim, Han Wool Kang, Kyung Ho Lee, Mi Yang Kim, Suk Jin Ham
  • Patent number: 9029251
    Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: May 12, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Jarvis Benjamin Jacobs, Ajith Varghese
  • Patent number: 9018109
    Abstract: A thin film transistor in which deterioration at initial operation is not likely to be caused and a manufacturing method thereof. A transistor which includes a gate insulating layer at least whose uppermost surface is a silicon nitride layer, a semiconductor layer over the gate insulating layer, and a buffer layer over the semiconductor layer and in which the concentration of nitrogen in the vicinity of an interface between the semiconductor layer and the gate insulating layer, which is in the semiconductor layer is lower than that of the buffer layer and other parts of the semiconductor layer. Such a thin film transistor can be manufactured by exposing the gate insulating layer to an air atmosphere and performing plasma treatment on the gate insulating layer before the semiconductor layer is formed.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: April 28, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Erika Kato, Kunihiko Suzuki
  • Patent number: 9012335
    Abstract: A silicon carbide semiconductor device having excellent electrical characteristics including channel mobility and a method for manufacturing the same are provided. The method for manufacturing a silicon carbide semiconductor device includes: an epitaxial layer forming step of preparing a semiconductor film of silicon carbide; a gate insulating film forming step of forming an oxide film on a surface of the semiconductor film; a nitrogen annealing step of performing heat treatment on the semiconductor film on which the oxide film is formed, in a nitrogen-containing atmosphere; and a post heat treatment step of performing, after the nitrogen annealing step, post heat treatment on the semiconductor film on which the oxide film is formed, in an atmosphere containing an inert gas. The heat treatment temperature in the post heat treatment step is higher than that in the nitrogen annealing step and lower than a melting point of the oxide film.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: April 21, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Takeyoshi Masuda, Keiji Wada
  • Patent number: 8940615
    Abstract: The present invention provides a method of forming an isolation structure. A substrate is provided, and a trench is formed in the substrate. Next, a semiconductor layer is formed on a surface of the trench. A nitridation is carried out to form a nitridation layer in the semiconductor layer. Lastly, an insulation layer is filled into the trench.
    Type: Grant
    Filed: September 9, 2012
    Date of Patent: January 27, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Te-Lin Sun, Chien-Liang Lin, Yu-Ren Wang
  • Patent number: 8937022
    Abstract: A method of manufacturing a semiconductor device includes: housing a substrate into a processing chamber; and forming a metal nitride film on the substrate by supplying a source gas containing a metal element, a nitrogen-containing gas and a hydrogen-containing gas into the processing chamber; wherein in forming the metal nitride film, the source gas and the nitrogen-containing gas are intermittently supplied into the processing chamber, or the source gas and the nitrogen-containing gas are intermittently and alternately supplied into the processing chamber, or the source gas is intermittently supplied into the processing chamber in a state that supply of the nitrogen-containing gas into the processing chamber is continued, and the hydrogen-containing gas is supplied into the processing chamber during at least supply of the nitrogen-containing gas into the processing chamber.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: January 20, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Arito Ogawa
  • Patent number: 8932964
    Abstract: A method of forming a dielectric layer, the method including sequentially forming a first oxide layer, a nitride layer, and a second oxide layer on a substrate by performing a plasma-enhanced atomic layer deposition process, wherein a first nitrogen plasma treatment is performed after forming the first oxide layer.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: January 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Jin Lee, Ji-Soon Park, Jong-Myeong Lee, Hyun-Bae Lee
  • Patent number: 8916484
    Abstract: Embodiments described herein generally relate to methods for manufacturing flash memory devices. In one embodiment, the method includes generating a plasma comprising nitrogen-containing radicals in a remote plasma applicator, flowing the plasma comprising nitrogen-containing radicals into a processing region of the processing chamber where a semiconductor device is disposed, wherein the semiconductor device has a substrate comprising an oxide layer formed thereon, exposing an exposed surface of the oxide layer to the nitrogen-containing radicals, and incorporating nitrogen in the exposed surface of the oxide layer of the substrate.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: December 23, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Christopher S. Olsen, Yoshitaka Yokota
  • Patent number: 8916483
    Abstract: Methods of fabricating semiconductor structures include the formation of molybdenum nitride at one or more surfaces of a substrate comprising molybdenum, and providing a layer of III-V semiconductor material, such as GaN, over the substrate. Semiconductor structures formed by methods described herein may include a substrate comprising molybdenum, molybdenum nitride at one or more surfaces of the substrate, and a layer of GaN bonded to the molybdenum nitride.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: December 23, 2014
    Assignee: SOITEC
    Inventor: Christiaan J. Werkhoven
  • Patent number: 8889523
    Abstract: A semiconductor process includes the following steps. A substrate having a recess is provided. A decoupled plasma nitridation process is performed to nitride the surface of the recess for forming a nitrogen containing liner on the surface of the recess. A nitrogen containing annealing process is then performed on the nitrogen containing liner.
    Type: Grant
    Filed: January 2, 2012
    Date of Patent: November 18, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Te-Lin Sun, Chien-Liang Lin, Yu-Ren Wang, Ying-Wei Yen
  • Patent number: 8853099
    Abstract: A nonvolatile resistive memory element has a novel variable resistance layer that includes a metal nitride, a metal oxide-nitride, a two-metal oxide-nitride, or a multilayer stack thereof. One method of forming the novel variable resistance layer comprises an interlayer deposition procedure, in which metal oxide layers are interspersed with metal nitride layers and then converted into a substantially homogeneous layer by an anneal process. Another method of forming the novel variable resistance layer comprises an intralayer deposition procedure, in which various ALD processes are sequentially interleaved to form a metal oxide-nitride layer. Alternatively, a metal oxide is deposited, nitridized, and annealed to form the variable resistance layer or a metal nitride is deposited, oxidized, and annealed to form the variable resistance layer.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: October 7, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Imran Hashim, Tim Minvielle, Takeshi Yamaguchi
  • Publication number: 20140291680
    Abstract: A silicon member and a method of producing the silicon member are provided. Cracking is suppressed in the silicon member even if the silicon member is used in a condition where it is heated. The silicon member 10 includes a coating layer 11 that coats a surface of the silicon member 10, wherein the coating layer 11 is composed of a product of silicon formed by reaction of the silicon on the surface, and a thickness of the coating layer is 15 nm or more and 600 nm or less. It is preferable that the coating layer is a silicon oxide film or a silicon nitride film.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 2, 2014
    Applicant: MITSUBISHI MATERIALS CORPORATION
    Inventor: Yoshinobu Nakada
  • Patent number: 8846538
    Abstract: Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: September 30, 2014
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Bomy Chen, Long Ching Wang, Sychi Fang
  • Patent number: 8828855
    Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Jarvis Benjamin Jacobs, Ajith Varghese
  • Patent number: 8809696
    Abstract: An object of the present invention is to provide a copper surface treatment method capable of keeping certainly a bonding strength between a copper surface and a resist, or between a copper surface and an insulating resin without forming irregularities having sizes of more than 1 ?m on the copper surface, and a copper treated with the method. The surface treatment method, comprising: a first step of forming, on a copper surface, a nobler metal than the copper discretely; a second step, subsequent to the first step, of forming copper oxide on the copper surface by oxidation with an alkaline solution containing an oxidizing agent; and third step of dissolving the copper oxide so as to be removed, thereby forming irregularities on the copper surface.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: August 19, 2014
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Tomoaki Yamashita, Sumiko Nakajima, Sadao Itou, Fumio Inoue, Shigeharu Arike
  • Patent number: 8802577
    Abstract: The present invention provides a method for forming a semiconductor device, as well as a semiconductor device. The method for manufacturing a semiconductor device, among others, includes providing a gate structure (240) over a substrate (210), the gate structure (240) including a gate electrode (248) located over a nitrided gate dielectric (243), and forming a nitrided region (310) over a sidewall of the nitrided gate dielectric (243).
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: August 12, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Jarvis B. Jacobs, Reima Tapani Laaksonen
  • Publication number: 20140220788
    Abstract: The present disclosure suppresses oxidation of a base film on a substrate surface during the formation of an oxide film. A method of manufacturing a semiconductor device according to the present disclosure includes forming an initial layer including a predetermined element and having a thickness of several atomic layers on a substrate in a process chamber by supplying a predetermined-element-containing gas to the substrate, and forming an oxide film including the predetermined element on the initial layer by performing a cycle a predetermined number of times, the cycle including supplying a precursor gas including the predetermined element to the substrate in the process chamber and supplying an oxygen-containing gas and a hydrogen-containing gas to the substrate heated in the process chamber under a pressure lower than an atmospheric pressure.
    Type: Application
    Filed: January 30, 2014
    Publication date: August 7, 2014
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Atsushi SANO, Yoshiro HIROSE, Naonori AKAE
  • Publication number: 20140199854
    Abstract: A method of forming a film is provided. The method includes at least the following steps. A first substrate and a second substrate are provided in a batch processing system, wherein a first surface of the first substrate is adjacent to a second surface of the second substrate, the first surface of the first substrate has a first surface condition, the second surface of the second substrate has a second surface condition, and the first surface condition is different from the second surface condition. A pretreatment gas is provided to the surfaces of the substrates for transforming the first surface condition and the second surface condition to a third surface condition. A reaction gas is provided to form the film on the surfaces, having the third surface condition, of the substrates.
    Type: Application
    Filed: January 16, 2013
    Publication date: July 17, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chung Chen, Tsuo-Wen Lu, Yu-Ren Wang
  • Patent number: 8753984
    Abstract: A method of forming a silicon nitride film on the surface of an object to be processed, the method including forming a seed layer functioning as a seed of the silicon nitride film on the surface of the object to be processed by using at least an aminosilane-based gas, prior to forming the silicon nitride film on the surface of the object to be processed.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: June 17, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Hiroki Murakami, Yosuke Watanabe, Kazuhide Hasebe
  • Patent number: 8741784
    Abstract: A process for fabricating a semiconductor device is described. A silicon oxide layer is formed. A nitridation process including at least two steps is performed to nitridate the silicon oxide layer into a silicon oxynitride (SiON) layer. The nitridation process comprises a first nitridation step and a second nitridation step in sequence, wherein the first nitridation step and the second nitridation step are different in the setting of at least one parameter.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: June 3, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Liang Lin, Te-Lin Sun, Ying-Wei Yen, Yu-Ren Wang
  • Patent number: 8729559
    Abstract: A relaxed epitaxial AlxInyGa(1-x-y)N layer on a substrate having a semipolar surface orientation includes a plurality of misfit dislocations in portions of the thickness of the epitaxial layer to reduce bi-axial strain to a relaxed state.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: May 20, 2014
    Assignee: Soraa, Inc.
    Inventors: Mike Krames, Mark D'Evelyn, Rajeev Pakalapati, Alex Alexander, Derrick Kamber
  • Patent number: 8728951
    Abstract: A method of processing a substrate includes performing a first exposure that comprises generating a plasma containing reactive gas ions in a plasma chamber and generating a bias voltage between the substrate and the plasma chamber. The method also includes providing a plasma sheath modifier having an aperture disposed between the plasma and substrate and operable to direct the reactive gas ions toward the substrate, and establishing a pressure differential between the plasma chamber and substrate region while the reactive gas ions are directed onto the substrate.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: May 20, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Xianfeng Lu, Deepak A. Ramappa
  • Publication number: 20140080317
    Abstract: A stress of a film formed on a substrate can be reduced. A method of manufacturing a semiconductor device includes: forming a film on the substrate by supplying a process gas to the substrate while heating the substrate to a first temperature; controlling a stress to the film by changing a stress value of the film formed on the substrate, by supplying a plasma-excited process gas to the substrate while changing a temperature of the substrate to a second temperature different from the first temperature; and unloading the substrate from the processor chamber.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 20, 2014
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yukinao KAGA, Masanori SAKAI, Takashi YOKOGAWA
  • Patent number: 8646407
    Abstract: A method is provided for using a film formation apparatus including a process container having an inner surface, which contains as a main component a material selected from the group consisting of quartz and silicon carbide. The method includes performing a film formation process to form a silicon nitride film on a product target substrate inside the process container, and then, unloading the product target substrate from the process container. Thereafter, the method includes supplying an oxidizing gas into the process container with no product target substrate accommodated therein, thereby performing an oxidation process to change by-product films deposited on the inner surface of the process container into a composition richer in oxygen than nitrogen, at a part of the by-product films from a surface thereof to a predetermined depth.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: February 11, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Hiroyuki Matsuura
  • Patent number: 8642374
    Abstract: An image sensor is described in which the imaging pixels have reduced noise by blocking nitridation in selected areas. In one example, a method includes forming a first and second gate oxide layer over a substrate, forming a layer of photoresist over the first gate oxide layer, applying nitridation to the photoresist and the second gate oxide layer such that the first gate oxide layer is protected from the nitridation by the photoresist, and forming a polysilicon gate over the first and second gate oxide layers.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: February 4, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Jeong-Ho Lyu, Sohei Manabe, Howard Rhodes
  • Publication number: 20140004713
    Abstract: According to an embodiment of present disclosure, a film formation method is provided. The film formation method includes supplying a first process gas as a source gas for obtaining a reaction product to a substrate while rotating a turntable and revolving the substrate, and supplying a second process gas as a gas for nitriding the first process gas adsorbed to the substrate to the substrate in a position spaced apart along a circumferential direction of the turntable from a position where the first process gas is supplied to the substrate. Further, the film formation method includes providing a separation region along the circumferential direction of the turntable between a first process gas supply position and a second process gas supply position, and irradiating ultraviolet rays on a molecular layer of the reaction product formed on the substrate placed on the turntable to control stresses generated in a thin film.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 2, 2014
    Inventors: Masanobu IGETA, Jun SATO, Kazuo YABE, Hitoshi KATO, Yusaku IZAWA
  • Patent number: 8557717
    Abstract: It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: October 15, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Koichi Muraoka, Koichi Kato, Yasushi Nakasaki, Yuichiro Mitani
  • Patent number: 8546273
    Abstract: Methods and apparatus for forming nitrogen-containing layers are provided herein. In some embodiments, a method of forming a nitrogen-containing layer may include placing a substrate having a first layer disposed thereon on a substrate support of a process chamber; heating the substrate to a temperature of at least about 250 degrees Celsius; and exposing the first layer to a radio frequency (RF) plasma formed from a process gas consisting essentially of ammonia (NH3) and an inert gas while maintaining the process chamber at a pressure of about 10 mTorr to about 40 mTorr to transform at least an upper portion of the first layer into a nitrogen-containing layer.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: October 1, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Malcolm J. Bevan, Johanes Swenberg, Son T. Nguyen, Wei Liu, Jose Antonio Marin, Jian Li
  • Patent number: 8547085
    Abstract: An arrangement for measuring process parameters within a processing chamber is provided. The arrangement includes a probe arrangement disposed in an opening of an upper electrode. Probe arrangement includes a probe head, which includes a head portion and a flange portion. The arrangement also includes an o-ring disposed between the upper electrode and the flange portion. The arrangement further includes a spacer made of an electrically insulative material positioned between the head portion and the opening of the upper electrode to prevent the probe arrangement from touching the upper electrode. The spacer includes a disk portion configured for supporting an underside of the flange portion. The spacer also includes a hollow cylindrical portion configured to encircle the head portion. The spacer forms a right-angled path between the o-ring and an opening to the processing chamber to prevent direct line-of-sight path between the o-ring and the opening to the processing chamber.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: October 1, 2013
    Assignee: Lam Research Corporation
    Inventors: Jean-Paul Booth, Douglas Keil
  • Patent number: 8546920
    Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Dinkar V. Singh, Jeffrey W. Sleight
  • Patent number: 8507922
    Abstract: Disclosed is a silicon carbide substrate which has less high frequency loss and excellent heat dissipating characteristics. The silicon carbide substrate (S) is provided with a first silicon carbide layer (1), which is composed of a polycrystalline silicon carbide, and a second silicon carbide layer (2), which is composed of polycrystalline silicon carbide formed on the surface of the first silicon carbide layer. The second silicon carbide layer (2) has a high-frequency loss smaller than that of the first silicon carbide layer (1), the first silicon carbide layer (1) has a thermal conductivity higher than that of the second silicon carbide layer (2), and on the surface side of the second silicon carbide layer (2), the high-frequency loss at a frequency of 20 GHz is 2 dB/mm or less, and the thermal conductivity is 200 W/mK or more.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: August 13, 2013
    Assignees: Mitsui Engineering & Shipbuilding Co., Ltd., Admap Inc.
    Inventors: Satoshi Kawamoto, Masaki Nakamura
  • Patent number: 8497190
    Abstract: A process for treating a semiconductor-on-insulator structure that has, in succession, a support substrate, a layer of an oxide or oxynitride of a semiconductor material, and a thin semiconductor layer of the semiconductor material. The process includes providing, on the surface of the thin layer, a mask defining exposed regions of the thin layer; providing a layer of nitride or oxynitride of the semiconductor material on the exposed regions of the thin layer; and applying a heat treatment causing at least some of the oxygen in the oxide or oxynitride layer to diffuse through the exposed regions. The nitride or oxynitride layer is provided at a thickness sufficient to provide a ratio of the rate of oxygen diffusion though the exposed regions to that through the regions covered with the mask that is greater than 2.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: July 30, 2013
    Assignee: Soitec
    Inventors: Didier Landru, Gregory Riou
  • Patent number: 8481433
    Abstract: Methods and apparatus for forming nitrogen-containing layers are provided herein. In some embodiments, a method includes placing a substrate having a first layer disposed thereon on a substrate support of a process chamber; heating the substrate to a temperature of at least about 250 degrees Celsius; and exposing the first layer to a radio frequency (RF) plasma formed from a process gas comprising nitrogen while maintaining the process chamber at a pressure of about 10 mTorr to about 40 mTorr to transform at least an upper portion of the first layer into a nitrogen-containing layer. In some embodiments, the process gas includes ammonia (NH3).
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: July 9, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Malcolm J. Bevan, Johanes Swenberg, Son T. Nguyen, Wei Liu, Jose Antonio Marin, Jian Li
  • Patent number: 8455293
    Abstract: A method for processing solar cells comprising: providing a vertical furnace to receive an array of mutually spaced circular semiconductor wafers for integrated circuit processing; composing a process chamber loading configuration for solar cell substrates, wherein a size of the solar cell substrates that extends along a first surface to be processed is smaller than a corresponding size of the circular semiconductor wafers, such that multiple arrays of mutually spaced solar cell substrates can be accommodated in the process chamber, loading the solar cell substrates into the process chamber; subjecting the solar cell substrates to a process in the process chamber.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: June 4, 2013
    Assignee: ASM International N.V.
    Inventors: Chris G. M. de Ridder, Klaas P. Boonstra, Adriaan Garssen, Frank Huussen
  • Patent number: 8440566
    Abstract: The method is adapted for forming an aluminum nitride thin film having a high density and a high resistance to thermal shock by a chemical vapor deposition process and includes steps of mixing a gas containing aluminum atoms (Al) and a gas containing nitrogen atoms (N) with a gas containing oxygen atoms (O) and feeding the mixture to a member to be covered by an aluminum nitride thin film.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: May 14, 2013
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Koji Kato, Shoji Kano, Waichi Yamamura
  • Patent number: 8440526
    Abstract: A method of fabricating a memory is provided. A substrate including a memory region and a periphery region is provided. A plurality of first gates is formed in the memory region and a plurality of first openings is formed between the first gates. A nitride layer is formed on the substrate in the memory region, and the nitride layer covers the first gates and the first openings. An oxide layer is formed on the substrate in the periphery region. A nitridization process is performed to nitridize the oxide layer into a nitridized oxide layer. A conductive layer is formed on the substrate, and the conductive layer includes a cover layer disposed on the substrate in the memory region and a plurality of second gates disposed on the substrate in the periphery region. The cover layer covers the nitride layer and fills the first openings.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 14, 2013
    Assignee: Winbound Electronics Corp.
    Inventors: Hsiu-Han Liao, Lu-Ping Chiang
  • Patent number: 8420407
    Abstract: A kind of growth method of Fe3Nin the MOCVD system, comprising following process: 1) make the surface nitridation of sapphire substrate; 2) pump in carrier gas N2, ammonia and organic gallium sources, and grow low temperature GaN buffer on substrate; 3) raise temperature and grow the GaN supporting layer; 4) pump in FeCp2 as Fe sources, then grow Fe3N on the GaN supporting layer; the Fe3N granular films and the Fe3N single crystal films are obtained.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: April 16, 2013
    Assignee: Nanjing University
    Inventors: Rong Zhang, Zili Xie, Bin Liu, Xiangqian Xiu, Henan Fang, Hong Zhao, Xuemei Hua, Ping Han, Peng Chen, Youdou Zheng
  • Patent number: 8410003
    Abstract: A method of manufacturing a semiconductor device includes forming a layer containing a predetermined element on a substrate by supplying a source gas containing the predetermined element into a process vessel and exhausting the source gas from the process vessel to cause a chemical vapor deposition (CVD) reaction. A nitrogen-containing gas is supplied into the process vessel and then exhausted, changing the layer containing the predetermined element into a nitride layer. This process is repeated to form a nitride film on the substrate. The process vessel is purged by supplying an inert gas into the process vessel and exhausting the inert gas from the process vessel between forming the layer containing the predetermined element and changing the layer containing the predetermined element into the nitride layer.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: April 2, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yosuke Ota, Yoshiro Hirose, Naonari Akae, Yushin Takasawa
  • Publication number: 20130034941
    Abstract: Methods of forming a semiconductor structure include providing an insulation layer on a semiconductor layer and diffusing cesium ions into the insulation layer from a cesium ion source outside the insulation layer. A MOSFET including an insulation layer treated with cesium ions may exhibit increased inversion layer mobility.
    Type: Application
    Filed: August 3, 2011
    Publication date: February 7, 2013
    Inventors: Sarit Dhar, Sei-Hyung Ryu, Anant Agarwal, John Robert Williams
  • Patent number: 8357608
    Abstract: An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si+C, B, Si+B, Si+B+C, and B+C containing precursor, and a N containing precursors at first times and removing the N precursor at second times and starting the flow of an oxidant gas and a porogen gas into the chamber. A dielectric layer is described comprising a network having inorganic random three dimensional covalent bonding throughout the network which contains at least one SiCN, SiCNH, SiN, SiNH, BN, BNH, CBN, CBNH, BSiN, BSiNH, SiCBN and SiCBNH as a first component and a low k dielectric as a second component adjacent thereto.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: January 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Stephen M Gates, Alfred Grill, Son Van Nguyen, Satyanarayana Venkata Nitta
  • Patent number: 8343618
    Abstract: A silicon wafer in which both occurrences of slip dislocation and warpage are suppressed in device manufacturing processes is a silicon wafer having BMDs having an octahedral shape, wherein BMDs located at a position below the silicon wafer surface to a depth of 20 ?m and having a diagonal length of 200 nm or more are present at a concentration of ?2×109/cm3, and BMDs located at a position below a depth ?50 ?m have a diagonal length of ?10 nm to ?50 nm and a concentration of ?1×1012/cm3.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: January 1, 2013
    Assignee: Siltronic AG
    Inventors: Masayuki Fukuda, Katsuhiko Nakai
  • Patent number: 8329536
    Abstract: To improve a charge retention characteristic of a nonvolatile memory transistor. A first insulating film, a charge trapping film, and a second insulating film are formed between a semiconductor substrate and a conductive film. The charge trapping film is formed of a silicon nitride film including an upper region having a low concentration of hydrogen and a lower region having a high concentration of hydrogen. Such a silicon nitride film is formed in such a manner that a silicon nitride film including 15 atomic % or more hydrogen is formed by a chemical vapor deposition method and an upper portion of the silicon nitride film is nitrided. The nitridation treatment is performed by nitriding the silicon nitride film by nitrogen radicals produced in plasma of a nitrogen gas.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: December 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kosei Noda
  • Patent number: RE45238
    Abstract: A silicon wafer in which both occurrences of slip dislocation and warpage are suppressed in device manufacturing processes is a silicon wafer having BMDs having an octahedral shape, wherein BMDs located at a position below the silicon wafer surface to a depth of 20 ?m and having a diagonal length of 200 nm or more are present at a concentration of ?2×109/cm3, and BMDs located at a position below a depth ?50 ?m have a diagonal length of ?10 nm to ?50 nm and a concentration of ?1×1012/cm3.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: November 11, 2014
    Assignee: Siltronic AG
    Inventors: Masayuki Fukuda, Katsuhiko Nakai