Abstract: A method for forming a semiconductor device (10) creates a dielectric layer (18) with high dielectric constant. An interfacial layer (14) is formed over a semiconductor substrate (12). A dielectric layer (16) is formed over the interfacial layer, wherein the dielectric layer has a high dielectric constant (K). The dielectric layer is thinned, such as by etching or chemical mechanical polishing, wherein a thickness of the thinned dielectric layer is less than a thickness of the dielectric layer prior to thinning. In one form, the method is used to form a transistor having a gate electrode layer formed over the thinned dielectric layer and source/drain diffusions (24, 26) within the semiconductor substrate.

Abstract: A method and apparatus are disclosed for reducing the concentration of chlorine and/or other bound contaminants within a semiconductor oxide composition that is formed by chemical vapor deposition (CVD) using a semiconductor-element-providing reactant such as dichlorosilane (DCS) and an oxygen-providing reactant such as N2O. In one embodiment, a DCS-HTO film is annealed by heating N2O gas to a temperature in the range of about 825° C. to about 950° C. so as to trigger exothermic decomposition of the N2O gas and flowing the heated gas across the DCS-HTO film so that disassociated atomic oxygen radicals within the heated N2O gas can transfer disassociating energy to chlorine atoms bound within the DCS-HTO film and so that the atomic oxygen radicals can fill oxygen vacancies within the semiconductor-oxide matrix of DCS-HTO film. An improved ONO structure may be formed with the annealed DCS-HTO film for use in floating gate or other memory applications.

Abstract: Silicon carbide structures are fabricated by fabricating a nitrided oxide layer on a layer of silicon carbide and annealing the nitrided oxide layer in an environment containing hydrogen. Such a fabrication of the nitrided oxide layer may be provided by forming the oxide layer in at least one of nitric oxide and nitrous oxide and/or annealing an oxide layer in at least one of nitric oxide and nitrous oxide. Alternatively, the nitrided oxide layer may be provided by fabricating an oxide layer and fabricating a nitride layer on the oxide layer so as to provide the nitrided oxide layer on which the nitride layer is fabricated. Furthermore, annealing the oxide layer may be provided as a separate step and/or substantially concurrently with another step such as fabricating the nitride layer or performing a contact anneal. The hydrogen environment may be pure hydrogen, hydrogen combined with other gases and/or result from a hydrogen precursor. Anneal temperatures of 400° C. or greater are preferred.

Abstract: A method for depositing a doped silicon dioxide layer is provided that allows the dopant concentration in the silicon dioxide layer to be controlled throughout the layer. By controlling the dopant concentration throughout the layer the etch profile of contact holes etched into the layer can be controlled and footing can be prevented or eliminated. During the deposition of the silicon dioxide, the amount of dopant is increased as the temperature of the wafer is increased and held constant while the temperature of the wafer is constant.

Abstract: A hard film is formed on an insulation film formed on a semiconductor substrate by vaporizing a silicon-containing hydrocarbon compound to provide a source gas, introducing a reaction gas composed of the source gas and optionally an additive gas such as alcohol to a reaction space of a plasma CVD apparatus, and applying low-frequency RF power and high-frequency RF power. The silicon-containing hydrocarbon compound includes a cyclic Si-containing hydrocarbon compound and/or a linear Si-containing hydrocarbon compound, as a basal structure, with reactive groups for form oligomers using the basal structure. The residence time of the reaction gas in the reaction space is lengthened by reducing the total flow of the reaction gas in such a way as to form a siloxan polymer film with a low dielectric constant.

Abstract: A cap layer that enables a photopatternable, spin-on material to be used in the formation of semiconductor device structures at wavelengths that were previously unusable. The photopatternable, spin-on material is applied as a layer to a semiconductor substrate. The cap layer and a photoresist layer are each formed over the photopatternable layer. The cap layer absorbs or reflects radiation and protects the photopatternable layer from a first wavelength of radiation used in patterning the photoresist layer. The photopatternable, spin-on material is convertible to a silicon dioxide-based material upon exposure to a second wavelength of radiation.

Abstract: A porous dielectric film for use in electronic devices is disclosed that is formed by removal of soluble nano phase porogens. A silicon based dielectric film having soluble porogens dispersed therein is prepared by chemical vapor deposition (CVD) or by spin on glass (S.O.G.). Examples of preferable porogens include compounds such as germanium oxide (GeO2) and boron oxide (B2O3). Hot water can be used in processing to wet etch the film, thereby removing the porogens and providing the porous dielectric film. The silicon based dielectric film may be a carbon doped silicon oxide in order to further reduce the dielectric constant of the film. Additionally, the porous dielectric film may be treated by an electron beam to enhance the electrical and mechanical properties of the film.

Abstract: According to the invention, while performing plasma-enhanced chemical vapor deposition on a substrate by exposing the substrate in a vacuum to a flow of particles generated by a plasma, which particles react to form a passivation layer on the substrate, a grid is interposed between the plasma and the substrate, thereby reducing the flow of charged particles towards the substrate while conserving a flow of neutral particles. The grid is formed of metal wires that are crossed at a pitch that is less than two or three times the Debye length (?D) of the plasma used, at least at the beginning of deposition. The aging properties of semiconductor components made by such a method is thereby improved.

Abstract: In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer.

Abstract: An architecture for creating multiple operating voltage MOSFETs. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and first and second spaced-apart doped regions formed in the surface. A third doped region forming a channel of different conductivity type than the first region is positioned over the first region. A fourth doped region of a different conductivity and forming a channel is positioned over the second region. The process of creating the gate structure for each of the two transistors allows for the formation of oxide layers of different thickness between the two transistors. The transistors are therefore capable of operating at different operating voltages (including different threshold voltages). Each transistor further includes fifth and sixth layers positioned respectively over the third and fourth regions and having an opposite conductivity type with respect to the third and fourth regions.

Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.

Abstract: A method of forming a polysilicon thin film transistor that includes depositing an amorphous silicon layer over a substrate, crystallizing the amorphous silicon layer into a polycrystalline silicon layer, patterning the polycrystalline silicon layer to form a polysilicon active layer for a thin film transistor, depositing silicon oxide over the polysilicon active layer to form a gate insulation layer under a vacuum condition, applying heat to anneal the gate insulation layer under a vacuum condition and forming a gate electrode on the annealed gate insulation layer.

Abstract: This invention includes methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation, and methods of forming bit line over capacitor arrays of memory cells. In one implementation, a semiconductor substrate having an exposed outer first surface comprising silicon-nitrogen bonds and an exposed outer second surface comprising at least one of silicon and silicon dioxide is provided. A layer comprising a metal is deposited over at least the outer second surface. A silanol is flowed to the metal of the outer second surface and to the outer first surface effective to selectively deposit a silicon dioxide comprising layer over the outer second surface as compared to the outer first surface. Other aspects and implementations are contemplated.

Abstract: A method of forming a silicon oxide layer in a semiconductor manufacturing process includes forming a planar spin on glass (SOG) layer by coating an SOG composition onto a semiconductor substrate having a stepped portion formed thereon, pre-baking the substrate at a temperature of from about 100 to about 500° C. for about 1 to about 10 minutes, maintaining a loading temperature of a furnace into which the substrate will be loaded at about 500° C. or less, loading the substrate into the furnace, and main-baking the substrate at a temperature of from about 500 to about 1200° C. for about 10 to about 120 minutes to form a silicon oxide layer on the substrate. The SOG layer is transformed into the silicon oxide layer through an optimized process condition. Thus, the silicon oxide layer may have minimal defects and a good layer property.

Abstract: A method and apparatus are disclosed for depositing a dielectric film in a gap having an aspect ratio at least as large as 6:1. By cycling the gas chemistry of a high-density-plasma chemical-vapor-deposition system between deposition and etching conditions, the gap may be substantially 100% filled. Such filling is achieved by adjusting the flow rates of the precursor gases such that the deposition to sputtering ratio during the deposition phases is within certain predetermined limits.

Abstract: A process is provided for depositing an undoped silicon oxide film on a substrate disposed in a process chamber. A process gas that includes SiF4, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 1011 ions/cm3 is formed from the process gas. The undoped silicon oxide film is deposited over the substrate with the plasma using a process that has simultaneous deposition and sputtering components.

Abstract: The present invention discloses a method for manufacturing semiconductor device wherein a cleaning process of a buffer layer is performed prior to a formation of a nitride film. The cleaning process allows to maintain the deposition thickness of the nitride film even when the time between the formation of the buffer layer and the formation of the nitride film is long.

Abstract: One embodiment of the present invention is an electron beam treatment apparatus that includes: (a) an array of lamps that output radiation; (b) a support mechanism adapted to support a substrate at a treatment position above the lamps; and (c) a lamp heat shield, disposed above the array, having a radiation absorption portion adapted to absorb radiation from at least a portion of the array, and a radiation reflection portion adapted to reflect radiation from at least a portion of the array towards the substrate when disposed at the treatment position.

Abstract: A method is provided for depositing a thin film on a substrate in a process chamber with reduced incidence of plasma charge damage. A process gas containing a precursor gases suitable for forming a plasma is flowed into a process chamber, and a plasma is generated from the process gas to deposit the thin film on the substrate. The precursor gases are flowed into the process chamber such that the thin film is deposited at the center of the substrate more rapidly than at an edge of the substrate.

Abstract: Embodiments of the present invention provide methods, apparatuses, and devices related to chemical vapor deposition of silicon oxide. In one embodiment, a single-step deposition process is used to efficiently form a silicon oxide layer exhibiting high conformality and favorable gap-filling properties. During a pre-deposition gas flow stabilization phase and an initial deposition stage, a relatively low ratio of silicon-containing gas:oxidant deposition gas is flowed, resulting in formation of highly conformal silicon oxide at relatively slow rates. Over the course of the deposition process step, the ratio of silicon-containing gas:oxidant gas is increased, resulting in formation of less-conformal oxide material at relatively rapid rates during later stages of the deposition process step.

Abstract: A method and system for forming a low defect oxide in a plasma processing chamber. By pulsing at least one of an RF power source and a processing gas, the growth of the oxide can be regulated. During periods in which the processing gas is not injected, an inert gas is injected to keep a substantially constant flow rate.

Abstract: A high density plasma chemical vapor deposition (HDP-CVD) process is used to deposit silicon dioxide in trenches of various widths. The thickness of the silicon dioxide filling both narrow and wide trenches is made more uniform by reducing an HDP-CVD etch to deposition ratio. The lowered etch to deposition ratio is achieved by lowering a ratio of oxygen to silane gas, by lowering the power of a high frequency bias signal, and by lowering the total gas flow rate.

Abstract: A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.

Abstract: A method of forming a silicon nitride-silicon dioxide, composite gate dielectric layer, offering reduced risk of boron penetration from an overlying boron doped polysilicon gate structure, has been developed. A porous, silicon rich silicon nitride layer is first deposited on a semiconductor substrate, allowing a subsequent thermal oxidation procedure to grow a thin silicon dioxide layer on the semiconductor substrate, underlying the porous, silicon rich silicon nitride layer. A two step anneal procedure is then employed with a first step performed in a nitrogen containing ambient to densify the porous, silicon rich silicon nitride layer, while a second step of the anneal procedure, performed in an inert ambient at a high temperature, reduces the foxed charge at the silicon dioxide-semiconductor interface.

Abstract: A nitrided oxide layer on a silicon carbide layer is processed by annealing the nitrided oxide layer in a substantially oxygen-free nitrogen containing ambient. The anneal may be carried out at a temperature of greater than about 900° C., for example, a temperature of about 1100° C., a temperature of about 1200° C. or a temperature of about 1300° C. Annealing the nitrided oxide layer may be carried out at a pressure of less than about 1 atmosphere, for example, at a pressure of from about 0.01 to about 1 atm or, in particular, at a pressure of about 0.2 atm. The nitrided oxide layer may be an oxide layer that is grown in a N2O and/or NO containing ambient, that is annealed in a N2O and/or NO containing ambient or that is grown and annealed in a N2O and/or NO containing ambient.

Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.

Abstract: A method of making a semiconductor device having a silicon dioxide based gate with improved dielectric properties including providing a silicon based substrate having active areas defined therein. Thermally growing a silicon dioxide based gate from the silicon based substrate. Nitriding the silicon dioxide based gate to provide a nitrided silicon dioxide based gate and to increase the dielectric constant of the silicon dioxide based gate without substantially increasing thickness of the silicon dioxide based gate.

Abstract: Compositions that can be used in semiconductor manufacturing processes, comprising perhydro-polysilazane having a weight average molecular weight of about 300 to about 3,000 and a polydispersity index of about 1.8 to about 3.0 are provided. Solutions comprising the compositions of the present invention, methods of forming films in a semiconductor manufacturing process, and methods of manufacturing semiconductor devices are also provided.

Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.

Abstract: A method is disclosed for removing liquids from a semiconductor substrate by contacting the liquid on the substrate with a liquid which attracts the liquid on the substrate, separating the liquids from the substrate, and inducing a phase transition in a layer on the substrate. In particular, the method is applicable to removing water from a water-containing layer on the substrate by contacting the layer with a hygroscopic liquid. Trenches on a substrate can be isolated by filling the trenches with a water-containing gel formed by reacting silane and hydrogen peroxide. The gel is contacted with sulfuric acid to remove a portion of the water from the gel before annealing to form silica in the trenches. Unlike filled trenches formed by conventional technology, there are no voids in the bottom of the trenches. The method is also applicable to forming dielectric layers which cover metal lines, low-dielectric layers, and interlayer dielectric layers.

Abstract: Methods for forming a thin film on an integrated circuit device including providing energy to reactants in a deposition chamber to activate the reactants. The activated reactants are then deposited on the substrate to form a thin film on the substrate. The reactants selected may be selectively activated so that different thin films are formed in a single chamber thereby reducing processing time.

Abstract: A method of fabricating a semiconductor device which includes introducing, after a step of patterning a gate electrode, nitrogen atoms into an oxide film covering a device region on a semiconductor substrate, by exposing said oxide film to an atmosphere containing-nitrogen, such that said nitrogen atoms do not reach a region underneath said gate electrode, covering, after said step of introducing nitrogen atoms, said oxide film including said gate electrode by a CVD oxide film continuously without taking out said semiconductor substrate out of a processing chamber and forming a sidewall oxide film on a sidewall surface of said gate electrode by etching back said CVD oxide film.

Abstract: The invention relates to a material including carbon, oxygen, silicon and hydrogen and having a dielectric constant of from about 2.1 to about 3.0 where an FTIR scan of the material includes at least two major peaks signifying Si—CH3 bonding. The invention further relates to a material which has a variable dielectric constant through the thickness of the material. Another aspect of the invention is the method of making the material.

Abstract: A fabrication process of a flash memory device includes microwave excitation of high-density plasma in a mixed gas of Kr and an oxidizing gas or a nitriding gas. The resultant atomic state oxygen O* or hydrogen nitride radicals NH* are used for nitridation or oxidation of a polysilicon electrode surface. It is also disclosed the method of forming an oxide film and a nitride film on a polysilicon film according to such a plasma processing.

Abstract: For suppressing decomposition of an organic group (for example, a CH3 group) which is bonded to an Si atom of an organic SOG film for use in a flattening process at the time of an ashing process, there is provided a method comprising the steps of: forming an organic SOG layer directly on a lower wiring layer or on a predetermined film including a hillock protection layer which is formed on the lower wiring layer in advance; forming an upper wiring layer on the organic SOG layer without using an etching back process; forming a via hole through an etching process by using a patterned resist layer provided on the upper wiring layer as a mask; performing an ashing process with a plasma by making ions or radicals which are induced from oxygen gas as a main reactant, under an atmospheric pressure ranging from 0.01 Torr to 30.0 Torr; and filling said via hole with a conductive material so as to electrically connect the lower wiring layer to the upper wiring layer.

Abstract: A semiconductor device of this invention includes a silicon nitride film formed on a semiconductor substrate and having a density of 2.2 g/cm3 or less, and a silicon oxide film formed on the silicon nitride film in an ambient atmosphere containing TEOS and O3.

Abstract: In a method of forming a fine pattern, a silicon-oxide-based film is formed directly or by way of another layer on a substrate or on an underlying layer. The silicon-oxide-based film is formed such that nitrogen content of the surface thereof assumes a value of 0.1 atm. % or less. A chemically-amplified photoresist layer is formed on the silicon-oxide-based film. A mask pattern of a mask is transferred onto the chemically-amplified photoresist layer upon exposure through the mask. Thus, there is prevented generation of a tapered corner in a portion of a resist pattern in the vicinity of a boundary area between the resist pattern and a substrate.

Abstract: A silicon oxide gap-filling process is described, wherein a CVD process having an etching effect is performed to fill up a trench with silicon oxide. The reaction gases used in the CVD process include deposition gases and He/H2 mixed gas as a sputtering-etching gas, wherein the percentage of the He/H2 mixed gas in the total reaction gases is raised with the increase of the aspect ratio of the trench.

Abstract: A method of forming semiconductor device treating a surface of a substrate to produce a discontinuous growth of a material on the surface through rapid thermal oxidation of the substrate surface at a temperature of less than about 700° C.

Abstract: A semiconductor device includes a substrate, a gate oxide film formed on the substrate, a gate electrode provided on the gate oxide film, first and second diffusion regions formed in the substrate at both lateral sides of the gate electrode. The gate electrode includes a first region located immediately underneath the gate electrode and a second region adjacent to the first region, wherein the first and second regions contain N atoms with respective concentrations such that the second region contains N with a higher concentration as compared with the first region.

Abstract: A method for fabricating a dielectric layer provides for use of a carbon source material separate from a halogen source material when forming a carbon and halogen doped silicate glass dielectric layer. The use of separate carbon and halogen source materials provides enhanced process latitude when forming the carbon and halogen doped silicate glass dielectric layer. Such a carbon and halogen doped silicate glass dielectric layer having a dielectric constant greater than about 3.0 is particularly useful as an intrinsic planarizing stop layer within a damascene method. A bilayer dielectric layer construction comprising a carbon and halogen doped silicate glass and a carbon doped silicate glass dielectric layer absent halogen doping is useful within a dual damascene method.

Abstract: A method of silanizing the surface of a low-k interlayer dielectric oxides (carbon doped oxides or organo-silicate glasses) to improve surface adhesion to adjacent thin film layers in damascene integration of microelectronic devices. A low-k interlayer dielectric oxide may be exposed to the vapor of a silane-coupling agent in order to modify its surface energy to improve adhesion with adjacent thin film layers. A low-k interlayer dielectric oxide can also be silanized by dipping the low-k interlayer dielectric oxide in a solution of silane-coupling agent. The silane-coupling agent will cause covalent bonds between the low-k interlayer dielectric oxide and the adjacent thin film thereby improving adhesion.

Abstract: Methods and apparatus are described for patterned deposition of nanostructure-containing materials by self-assembly and related articles. According to an exemplary embodiment self-assembly method for depositing nanostructure-containing materials includes forming a nanostructure-containing material. The nanostructure-containing material is chemically functionalized and dispersed in a liquid medium to form a suspension. At least a portion of a substrate having a surface that can attract the functionalized nanostructure-containing material is brought into contact with the suspension. The substrate is separated from the suspension. The nanostructure-containing material adheres to the portion of the substrate when separated from the suspension. According to another exemplary embodiment, hydrophilic and hydrophobic regions are formed on the surface of the substrate before bringing the substrate into contact with the suspension.

Abstract: A method of forming oxide-nitride-oxide (ONO) dielectric of a SONOS-type nonvolatile storage device is disclosed. According to a first embodiment, a method may include the steps of forming a tunneling dielectric (step 102), forming a charge storing dielectric (step 104), and forming a top insulating layer (step 106) all in the same wafer processing tool. According to various aspects of the embodiments, all layers of an ONO dielectric of a SONOS-type device may be formed in the same general temperature range. Further, a tunneling dielectric may include a tunnel oxide formed with a long, low pressure oxidation, and a top insulating layer may include silicon dioxide formed with a preheated source gas.

Abstract: A method of forming dual gate insulator layers, each with a specific insulator thickness, featuring a HF type pre-clean procedure performed prior to formation of each of the gate insulator layers, has been developed. After a first HF type pre-clean procedure a silicon nitride layer is deposited on the native oxide free, semiconductor substrate followed by selective removal of silicon nitride layer from a second portion of the semiconductor substrate. After a second HF type pre-clean procedure a silicon dioxide gate insulator layer is formed on the second portion of the native oxide free, semiconductor substrate, with the silicon dioxide gate insulator layer comprised with a different thickness than the silicon nitride gate insulator layer, located on a first portion of the semiconductor substrate. The procedure used to form the silicon dioxide gate insulator layer also removes bulk traps in the silicon nitride gate insulator layer.

Abstract: A method of forming capacitors with geometric deep trenches. First, a substrate with a pad structure formed thereon is provided, and a first hard mask layer is formed on the pad structure. Next, a second hard mask layer is formed on the first hard mask layer. Next, a spacer layer is formed in the first opening on the first hard mask layer to expose a second opening. Next, a third hard mask layer is filled the second opening, and the spacer layer is removed. Next, the first hard mask layer is etched to expose a third opening with a salient of the first hard mask layer, with the second hard mask layer and the third hard mask layer acting as masks. Finally, the first hard mask layer, the pad structure, and the substrate are etched to form a geometric deep trench.

Abstract: While a crucible containing an Si material and a substrate to be processed are set in a chamber, Ar gas is supplied into the chamber and the Si material is evaporated by heating, thereby forming a nanoparticle thin film of Si on the substrate. This substrate is then annealed in an oxygen atmosphere to oxidize Si, forming a nanoparticle oxide thin film consisting of SiO2.

Abstract: A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.

Abstract: A HDP CVD process for depositing a USG liner followed by a FSG dielectric layer on a metal line pattern is described. The substrate is heated in a chamber with a plasma comprised of Ar and O2. A USG liner is deposited in two steps wherein the first step is without an RF bias and the second step is with a moderate RF bias that does not damage the metal lines or an anti-reflective coating on the metal. The moderate RF bias is critical in forming a sputtering component that redeposits USG to form more uniform sidewalls and better coverage at top corners of metal lines. The USG deposition process has a good gap filling capability and significantly reduces device failure rate by preventing corrosion of metal lines during subsequent thermal process cycles. The method also includes a PECVD deposited FSG layer that is planarized to complete an IMD layer.

Abstract: Methods of manufacturing semiconductor devices are disclosed. In a disclosed example, a multi-layered insulating structure is deposited on a semiconductor substrate, an opening is formed in the multi-layered insulating structure above the semiconductor substrate, and a trench is formed in the semiconductor substrate under the opening. Then, a groove is formed on an edge position of an intermediate layer of the multi-layered insulating structure by wet-etching the intermediate layer of the multi-layered insulating layer transversely using a pull back process. Then, a liner oxide layer is deposited on the groove and the trench. An oxide layer then fills the trench and the groove without generating voids or divots in the oxide layer of the trench.