Silicon Oxide Formation Patents (Class 438/787)
  • Patent number: 7381620
    Abstract: A method includes forming at least a portion of a semiconductor device in a processing chamber containing oxygen and removing substantially all of the oxygen from the processing chamber. The method further includes forming remaining portions of the semiconductor device in the processing chamber without the presence of oxygen.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: June 3, 2008
    Assignee: Spansion LLC
    Inventors: Boon-Yong Ang, Hidehiko Shiraiwa, Simon S. Chan, Harpreet K. Sachar, Mark Randolph
  • Publication number: 20080121177
    Abstract: A gas distributor for use in a semiconductor process chamber comprises a body. The body includes a first channel formed within the body and adapted to pass a first fluid from a first fluid supply line through the first channel to a first opening. A second channel is formed within the body and adapted to pass a second fluid from a second fluid supply line through the second channel to a second opening. The first and second openings are arranged to mix the fluids outside the body after the fluids pass through the openings.
    Type: Application
    Filed: November 28, 2006
    Publication date: May 29, 2008
    Applicant: Applied Materials, Inc.
    Inventors: Won B. Bang, Srivivas D. Nemani, Phong Pham, Ellie Y. Yieh
  • Patent number: 7378356
    Abstract: A biased pulse DC reactor for sputtering of oxide films is presented. The biased pulse DC reactor couples pulsed DC at a particular frequency to the target through a filter which filters out the effects of a bias power applied to the substrate, protecting the pulsed DC power supply. Films deposited utilizing the reactor have controllable material properties such as the index of refraction. Optical components such as waveguide amplifiers and multiplexers can be fabricated processes performed on a reactor according to the present inention.
    Type: Grant
    Filed: March 16, 2002
    Date of Patent: May 27, 2008
    Assignee: SpringWorks, LLC
    Inventors: Hongmei Zhang, Mukundan Narasimhan, Ravi B. Mullapudi, Richard E. Demaray
  • Publication number: 20080119059
    Abstract: Methods for low thermal budget silicon dioxide chemical vapor deposition in single-wafer chambers are provided. In semiconductor manufacturing, Si2H6-based oxide deposition is worthy of consideration as a viable alternative to higher temperature thermal CVD processes. A process of forming a film on a substrate is provided, the process comprising: placing a substrate in a thermal low-pressure chemical vapor deposition single-wafer chamber; flowing disilane (Si2H6) into the chamber; flowing nitrous oxide (N2O) into the chamber at a ratio of at least approximately 300:1 N2O:Si2H6; heating the chamber at a temperature of from approximately 450° C. to approximately 550° C.; and forming the film on the substrate, wherein the film comprises silicon dioxide (SiO2).
    Type: Application
    Filed: November 20, 2006
    Publication date: May 22, 2008
    Inventors: Jacob W. Smith, R. Suryanarayanan Iyer, Yuji Maeda
  • Patent number: 7371695
    Abstract: A method for manufacturing a low temperature removable silicon dioxide hard mask for patterning and etching is provided, wherein tetra-ethyl-ortho-silane (TEOS) is used to deposit a silicon dioxide hard mask.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: May 13, 2008
    Assignee: ProMos Technologies Pte. Ltd.
    Inventors: Tai-Peng Lee, Barbara Haselden
  • Patent number: 7368381
    Abstract: The invention includes methods of forming films over substrates. A substrate is provided within a reaction chamber, and a mixture is also provided within the chamber. The mixture includes a precursor of a desired material within a supercritical fluid. The precursor is relatively reactive under one set of conditions and is relatively non-reactive under another set of conditions. The precursor and supercritical fluid mixture is initially provided in the chamber under the conditions at which the precursor is relatively non-reactive. Subsequently, and while maintaining the supercritical state of the supercritical fluid, the conditions within the reaction chamber are changed to the conditions under which the precursor is relatively reactive. The precursor reacts to form the desired material, and at least some of the desired material forms a film on the substrate.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: May 6, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Garo J Derderian, Cem Basceri
  • Patent number: 7368401
    Abstract: In one aspect of the invention, a method for forming an integrated circuit having an at least substantially doped porous dielectric includes forming a semiconductor device. The semiconductor device includes at least a portion of a semiconductor substrate. The method also includes forming a dielectric layer disposed outwardly from the semiconductor substrate and surrounding at least a portion of the semiconductor device. The dielectric layer includes an at least substantially porous dielectric material doped with at least one dopant. In addition, the method includes forming a contact layer disposed outwardly from the dielectric layer and operable to provide electrical connection to the semiconductor device.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: May 6, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Robert H. Havemann
  • Publication number: 20080102650
    Abstract: A method of forming a nitrided silicon oxide layer. The method includes: forming a silicon dioxide layer on a surface of a silicon substrate; performing a rapid thermal nitridation of the silicon dioxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form an initial nitrided silicon oxide layer; and performing a rapid thermal oxidation or anneal of the initial nitrided silicon oxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form a nitrided silicon oxide layer. Also a method of forming a MOSFET with a nitrided silicon oxide dielectric layer.
    Type: Application
    Filed: October 30, 2006
    Publication date: May 1, 2008
    Inventors: Edward Dennis Adams, Jay Sanford Burnham, Evgeni Gousev, James Spiros Nakos, Heather Elizabeth Preuss, Joseph Francis Shepard
  • Patent number: 7361614
    Abstract: This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing an aluminum containing organic precursor to a chamber containing a semiconductor substrate effective to deposit an aluminum comprising layer over the substrate. An alkoxysilanol is flowed to the substrate comprising the aluminum comprising layer within the chamber effective to deposit a silicon dioxide comprising layer over the substrate.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: April 22, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Chris W. Hill
  • Patent number: 7361611
    Abstract: Adding at least one non-silicon precursor (such as a germanium precursor, a carbon precursor, etc.) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate and/or makes possible tuning of properties of the film, such as tuning of the stress of the film. Also, in a doped silicon oxide or doped silicon nitride or other doped structure, the presence of the dopant may be used for measuring a signal associated with the dopant, as an etch-stop or otherwise for achieving control during etching.
    Type: Grant
    Filed: February 8, 2006
    Date of Patent: April 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ashima B. Chakravarti, Judson Holt, Kevin K. Chan, Sadanand V. Deshpande, Rangarajan Jagannathan
  • Publication number: 20080085612
    Abstract: Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.
    Type: Application
    Filed: October 5, 2006
    Publication date: April 10, 2008
    Inventors: John A. Smythe, Gurtej S. Sandhu, Brian J. Coppa, Shyam Surthi, Shuang Meng
  • Publication number: 20080085610
    Abstract: Methods for forming metal silicate films are provided. The methods comprise contacting a substrate with alternating and sequential vapor phase pulses of a silicon source chemical, metal source chemical, and an oxidizing agent, wherein the metal source chemical is the next reactant provided after the silicon source chemical. Methods according to some embodiments can be used to form silicon-rich hafnium silicate and zirconium silicate films with substantially uniform film coverages on substrate surface.
    Type: Application
    Filed: October 5, 2007
    Publication date: April 10, 2008
    Applicant: ASM AMERICA, INC.
    Inventors: Chang-Gong Wang, Eric Shero, Glen Wilk
  • Patent number: 7354873
    Abstract: A method for forming an insulation film having filling property on a semiconductor substrate by plasma reaction includes: vaporizing a silicon-containing hydrocarbon having a Si—O bond compound to provide a source gas; introducing the source gas and a carrier gas without an oxidizing gas into a reaction space for plasma CVD processing; and forming an insulation film constituted by Si, O, H, and optionally C or N on a substrate by plasma reaction using a combination of low-frequency RF power and high-frequency RF power in the reaction space. The plasma reaction is activated while controlling the flow of the reaction gas to lengthen a residence time, Rt, of the reaction gas in the reaction space.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: April 8, 2008
    Assignee: ASM Japan K.K.
    Inventors: Atsuki Fukazawa, Nobuo Matsuki, Seijiro Umemoto
  • Patent number: 7345000
    Abstract: A method and system for treating a dielectric film includes exposing at least one surface of the dielectric film to an alkyl silane, an alkoxysilane, an alkyl siloxane, an alkoxysiloxane, an aryl silane, an acyl silane, a cyclo siloxane, a polysilsesquioxane (PSS), an aryl siloxane, an acyl siloxane, or a halo siloxane, or any combination thereof. The dielectric film can include a low dielectric constant film with or without pores having an etch feature formed therein following dry etch processing. As a result of the etch processing or ashing, exposed surfaces in the feature formed in the dielectric film can become damaged, or activated, leading to retention of contaminants, absorption of moisture, increase in dielectric constant, etc. Damaged surfaces, such as these, are treated by performing at least one of healing these surfaces to, for example, restore the dielectric constant (i.e., decrease the dielectric constant) and cleaning these surfaces to remove contaminants, moisture, or residue.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: March 18, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Robert Kevwitch, Brandon Hansen, Dorel Ioan Toma, Jianhong Zhu
  • Publication number: 20080064227
    Abstract: An apparatus for chemical vapor deposition includes a reaction chamber providing a predetermined sealed space, a reaction gas supply unit for supplying a first reaction gas into the reaction chamber and a reaction gas supply line formed by operatively connecting the reaction gas supply unit and the reaction chamber. The reaction gas supply line allows the first reaction gas to flow through. The apparatus further includes a raw material supply unit for supplying at least one liquid raw material for generating a second reaction gas to be mixed with the first reaction gas supplied through the reaction gas supply line, a liquid raw material supply line allowing the at least one liquid raw material, which is supplied from the raw material supply unit, to flow into the reaction gas supply line, an injector for injecting the at least one liquid raw material to be vaporized at a portion where the liquid raw material supply line is connected to the reaction gas supply line.
    Type: Application
    Filed: June 14, 2007
    Publication date: March 13, 2008
    Inventor: Jin-Sung KIM
  • Patent number: 7341761
    Abstract: Methods of preparing a carbon doped oxide (CDO) layers having a low dielectric constant are provided. The methods involve, for instance, providing a substrate to a deposition chamber and exposing it to one or multiple carbon-doped oxide precursors having molecules with at least one carbon—carbon triple bond, or carbon—carbon double bond, or a combination of these groups and depositing the carbon doped oxide dielectric layer under conditions in which the resulting dielectric layer has a dielectric constant of not greater than about 2.7.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: March 11, 2008
    Assignee: Novellus Systems, Inc.
    Inventors: Qingguo Wu, Haiying Fu, Xingyuan Tang
  • Publication number: 20080054358
    Abstract: A method of manufacturing a thin film including the steps of: providing a film manufacturing apparatus including a first discharge electrode, a second discharge electrode placed opposed to the first discharge electrode and a high frequency power source, which supplies high frequency power between the first discharge electrode and a second discharge electrode; placing a substrate on which a conductive line pattern has been formed on the second discharge electrode; applying the high frequency power from the high frequency power supply while generating plasma by using discharged gas under an atmospheric pressure or a near-atmospheric pressure; and forming a thin film on the substrate, wherein a space ratio (W/L) of a line width W (W>0) of the conductive line pattern to a spatial distance L between the first discharge electrode and the substrate is set not more than 0.1.
    Type: Application
    Filed: August 22, 2007
    Publication date: March 6, 2008
    Inventors: Masakazu OKADA, Yuya HIRAO
  • Patent number: 7335609
    Abstract: A chemical vapor deposition method for forming a dielectric material in a trench formed on a substrate. The method includes flowing a silicon-containing precursor into a process chamber housing the substrate, flowing an oxidizing gas into the chamber, and providing a hydroxyl-containing precursor in the process chamber. The method also includes reacting the silicon-containing precursor, oxidizing gas and hydroxyl-containing precursor to form the dielectric material in the trench. The ratio of the silicon-containing precursor to the oxidizing gas flowed into the chamber is increased over time to alter a rate of deposition of the dielectric material.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: February 26, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Nitin K. Ingle, Shan Wong, Xinyun Xia, Vikash Banthia, Won B. Bang, Yen-Kun V. Wang
  • Patent number: 7329612
    Abstract: A semiconductor device is manufactured by the steps of generating a film forming gas by setting a flow rate ratio of H2O to any one of a silicon-contained organic compound having a siloxane bond and a silicon-contained organic compound having a CH3 group to 4 or more and adjusting a gas pressure to 1.5 Torr or more, applying a power to the film forming gas to generate a plasma thereof so as to react it, and thus forming a low-dielectric insulating film (62) on a substrate (61), plasmanizing a process gas containing at least any one of He, Ar, H2 or deuterium, and bringing the low-dielectric insulating film (62) into contact with the plasma of the process gas.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: February 12, 2008
    Assignee: Semiconductor Process Laboratory Co., Ltd.
    Inventors: Yoshimi Shioya, Yuhko Nishimoto, Kazuo Maeda
  • Patent number: 7326657
    Abstract: A method for providing a dielectric film having enhanced adhesion and stability. The method includes a post deposition treatment that densifies the film in a reducing atmosphere to enhance stability if the film is to be cured ex-situ. The densification generally takes place in a reducing environment while heating the substrate. The densification treatment is particularly suitable for silicon-oxygen-carbon low dielectric constant films that have been deposited at low temperature.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: February 5, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Li-Qun Xia, Frederic Gaillard, Ellie Yieh, Tian H. Lim
  • Publication number: 20080020594
    Abstract: In a method of manufacturing a phase-changeable memory device, a lower electrode is formed on a substrate. Silicon oxynitride is then deposited on the lower electrode at a temperature of about 450° C. to about 650° C. to form an insulating interlayer that is relatively dense on the lower electrode. The insulating interlayer is partially etched to form a contact hole exposing the lower electrode. A phase-changeable material layer pattern filling up the contact hole is formed on the insulating interlayer such that the phase-changeable material layer pattern makes contact with the lower electrode.
    Type: Application
    Filed: July 13, 2007
    Publication date: January 24, 2008
    Inventors: Do-Hyung Kim, Ju-Bum Lee
  • Patent number: 7320944
    Abstract: A method of forming a phosphosilicate glass, includes flowing a pre-deposition gas comprising an inert gas into a deposition chamber containing a substrate, where the temperature of the substrate is at a pre-deposition temperature of at least 400° C; continuously increasing the temperature of gas in the chamber to a deposition temperature and simultaneously continuously increasing a flow rate of phosphine and silane until a phosphine:silane deposition ratio is achieved; and depositing the phosphosilicate glass on the substrate at the deposition temperature and at the phosphine:silane deposition ratio.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: January 22, 2008
    Assignee: Cypress Semiconductor Corporation
    Inventors: Michal Efrati Fastow, Ryan Holler
  • Patent number: 7317220
    Abstract: A semiconductor assembly providing even nucleation between silicon and oxide surfaces for growing uniformly thin silicon nitride layers used in semiconductor devices is disclosed. First, a nonconductive nitride-nucleation enhancing monolayer is formed over a semiconductor assembly having both nitridation receptive and resistive materials. For purposes of the present invention, a nitride-nucleation enhancing monolayer is a material that will readily accept the bonding of nitrogen atoms to the material itself. Next, a silicon nitride layer is formed over the nonconductive nitride-nucleation enhancing monolayer. The nonconductive nitride-nucleation enhancing monolayer provides even nucleation over both the nitridation receptive material and the nitridation resistive material for silicon nitride, thereby allowing for the growth of a uniformly thin nitride layer.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: January 8, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Er-Xuan Ping
  • Patent number: 7314837
    Abstract: A method is disclosed for removing liquids from a semiconductor substrate by contacting the liquid on the substrate with a liquid which attracts the liquid on the substrate, separating the liquids from the substrate, and inducing a phase transition in a layer on the substrate. In particular, the method is applicable to removing water from a water-containing layer on the substrate by contacting the layer with a hygroscopic liquid. Trenches on a substrate can be isolated by filling the trenches with a water-containing gel formed by reacting silane and hydrogen peroxide. The gel is contacted with sulfuric acid to remove a portion of the water from the gel before annealing to form silica in the trenches. Unlike filled trenches formed by conventional technology, there are no voids in the bottom of the trenches. The method is also applicable to forming dielectric layers which cover metal lines, low-dielectric layers, and interlayer dielectric layers.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: January 1, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Weimin Li
  • Patent number: 7312164
    Abstract: A method for applying a passivation layer selectively on an exposed silicon surface includes use of a liquid phase solution supersaturated in silicon dioxide. The application is conducted at substantially atmospheric temperature and pressure and achieves an effective passivation layer in an abbreviated immersion time, and without subsequent heat treatment. In one embodiment, rapid coating of a wafer back side with silicon dioxide permits the use of a high-speed electroless process for plating the bond pad with a solder-enhancing material. In another embodiment, the walls of via holes and microvia holes in a silicon body may be passivated by applying the supersaturated solution prior to plugging the holes with conductive material.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: December 25, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Joseph T. Lindgren
  • Publication number: 20070287300
    Abstract: Disclosed is a method of forming a layer of material using an atomic layer deposition (ALD) process in a process chamber of a process tool. In one illustrative embodiment, the method includes identifying a target characteristic for the layer of material, determining a precursor pulse time for introducing a precursor gas into the process chamber during the ALD process to produce the target characteristic in the layer of material, and performing the ALD process that comprises a plurality of steps wherein the precursor gas is introduced into the chamber for the determined precursor pulse time to thereby form the layer of material.
    Type: Application
    Filed: June 9, 2006
    Publication date: December 13, 2007
    Inventors: NEAL RUEGER, John Smythe
  • Patent number: 7306985
    Abstract: A gate insulating film having an insulating film that contains at least nitrogen is formed on a substrate, and the gate insulating film is subjected to heat treatment for about 500 milliseconds or less using a flash lamp. Thereafter, a gate electrode is formed on the gate insulating film. Specifically, for example, a laminated film of SiO2 film and an SixN(1-x) film, a laminated film of an SiO2 film, HfSiO film, and an SixN(1-x) film, or the like, is formed in forming the gate insulating film.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: December 11, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Takaoki Sasaki, Takeshi Hoshi
  • Patent number: 7304003
    Abstract: An oxidizing method for an object to be processed according to the present invention includes: an arranging step of arranging a plurality of objects to be processed in a processing container whose inside can be vacuumed, the processing container having a predetermined length, a main supplying unit of an oxidative gas and a supplying unit of a reducing gas being provided at one end of the processing container, a sub supplying unit of the oxidative gas being provided on a way in a longitudinal direction of the processing container; an atmosphere forming step of supplying the oxidative gas and the reducing gas into the processing container in order to form an atmosphere having active oxygen species and active hydroxyl species in the processing container; and an oxidizing step of oxidizing surfaces of the plurality of objects to be processed in the atmosphere.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: December 4, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Keisuke Suzuki, Toshiyuki Ikeuchi, Kimiya Aoki
  • Patent number: 7297642
    Abstract: A method is provided for forming a rare earth (RE) element-doped silicon (Si) oxide film with nanocrystalline (nc) Si particles. The method comprises: providing a first target of Si, embedded with a first rare earth element; providing a second target of Si; co-sputtering the first and second targets; forming a Si-rich Si oxide (SRSO) film on a substrate, doped with the first rare earth element; and, annealing the rare earth element-doped SRSO film. The first target is doped with a rare earth element such as erbium (Er), ytterbium (Yb), cerium (Ce), praseodymium (Pr), or terbium (Tb). The sputtering power is in the range of about 75 to 300 watts (W). Different sputtering powers are applied to the two targets. Also, deposition can be controlled by varying the effective areas of the two targets. For example, one of the targets can be partially covered.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: November 20, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Wei Gao, Tingkai Li, Robert A. Barrowcliff, Yoshi Ono, Sheng Teng Hsu
  • Patent number: 7297620
    Abstract: In methods of forming an oxide layer and an oxynitride layer, a substrate is loaded into a reaction chamber having a first pressure and a first temperature. The oxide layer is formed on the substrate using a reaction gas while increasing a temperature of the reaction chamber from the first temperature to a second temperature under a second pressure. Additionally, the oxide layer is nitrified in the reaction chamber to form the oxynitride layer on the substrate. When the oxide layer and/or the oxynitride layer are formed on the substrate, minute patterns of a semiconductor device, for example a DRAM device, an SRAM device or an LOGIC device may be easily formed on the oxide layer or the oxynitride layer.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: November 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Hun-Hyeoung Leam, Seok-Woo Nam, Bong-Hyun Kim, Woong Lee, Sang-Hoon Lee
  • Patent number: 7294528
    Abstract: Supercritical fluid-assisted deposition of materials on substrates, such as semiconductor substrates for integrated circuit device manufacture. The deposition is effected using a supercritical fluid-based composition containing the precursor(s) of the material to be deposited on the substrate surface. Such approach permits use of precursors that otherwise would be wholly unsuitable for deposition applications, as lacking requisite volatility and transport characteristics for vapor phase deposition processes.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: November 13, 2007
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Chongying Xu, Thomas H. Baum
  • Patent number: 7294585
    Abstract: Low dielectric materials and films comprising same have been identified for improved performance when used as performance materials, for example, in interlevel dielectrics integrated circuits as well as methods for making same. In one aspect of the present invention, the performance of the dielectric material may be improved by controlling the weight percentage of ethylene oxide groups in the at least one porogen.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: November 13, 2007
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Brian Keith Peterson, John Francis Kirner, Scott Jeffrey Weigel, James Edward MacDougall, Lisa Deis, legal representative, Thomas Albert Braymer, Keith Douglas Campbell, Martin Devenney, C. Eric Ramberg, Konstantinos Chondroudis, Keith Cendak, Thomas Alan Deis, deceased
  • Patent number: 7294588
    Abstract: A process is provided for depositing an silicon oxide film on a substrate disposed in a process chamber. A process gas that includes a halogen source, a fluent gas, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 1011 ions/cm3 is formed from the process gas. The silicon oxide film is deposited over the substrate with a halogen concentration less than 1.0%. The silicon oxide film is deposited with the plasma using a process that has simultaneous deposition and sputtering components. The flow rate of the halogen source to the process chamber to the flow rate of the silicon source to the process chamber is substantially between 0.5 and 3.0.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: November 13, 2007
    Assignee: Applied Materials, Inc.
    Inventors: M. Ziaul Karim, DongQing Li, Jeong Soo Byun, Thanh N. Pham
  • Patent number: 7285503
    Abstract: A method of forming a cap layer over a dielectric layer on a substrate including forming a plasma from a process gas including oxygen and tetraethoxysilane, and depositing the cap layer on the dielectric layer, where the cap layer comprises a thickness of about 600 ? or less, and a compressive stress of about 200 MPa or more. Also, a method of forming a cap layer over a dielectric layer on a substrate including forming a process gas by flowing together about 200 mgm to about 8000 mgm of tetraethoxysilane, about 2000 to about 20000 sccm of oxygen (O2), and about 2000 sccm to about 20000 sccm of carrier gas, generating a plasma from the process gas, where one or more RF generators supply about 50 watts to about 100 watts of low frequency RF power to the plasma, and about 100 watts to about 600 watts of high frequency RF power to the plasma, and depositing the cap layer on the dielectric layer.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: October 23, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Vu Ngoc Tran Nguyen, Bok Hoen Kim, Kang Sub Yim
  • Patent number: 7285502
    Abstract: A method for forming a porous insulative structure on a semiconductor device structure includes forming a layer of unconsolidated electrically insulative, or dielectric, material with microcapsules dispersed therethrough on at least a portion of the surface of the semiconductor device structure. The microcapsules may be hollow or include a removable filler. Once the layer has been formed, the unconsolidated material is at least partially consolidated. Filler, if any, may be removed from the microcapsules to provide a porous insulative layer or structure. This layer or structure may be configured to support conductive elements or other features of the semiconductor device.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: October 23, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Tongbi Jiang
  • Publication number: 20070243722
    Abstract: A method of manufacturing a device on a silicon carbide substrate is disclosed. The device includes an oxide layer which has silicon oxide as a main component on the silicon carbide semiconductor substrate. The method includes depositing and oxide layer on a surface of the silicon carbide semiconductor substrate; raising a temperature of the oxide layer in a non-oxidizing atmosphere to a temperature bringing the oxide layer into a liquefied state; and then rapidly cooling the oxide layer down to a temperature equal to or less than 1140° C. to form the oxide layer including silicon oxide as a main component. The silicon carbide semiconductor device has improved channel mobility to lower on-resistance by decreasing an interface state density at an interface between the oxide insulator film that has silicon oxide as its main component and the silicon carbide semiconductor substrate.
    Type: Application
    Filed: April 18, 2007
    Publication date: October 18, 2007
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD
    Inventors: Shun-ichi NAKAMURA, Yoshiyuki YONEZAWA
  • Patent number: 7273822
    Abstract: Methods and apparatus are provided for forming thin films for semiconductor devices, which enable supplying and removing reactants containing constituent elements of a thin film to be formed, by preheating and supplying a process gas and a purging gas at a predetermined temperature in forming the thin film on a substrate. For example, a method for forming a thin film includes supplying a first reactant to a chamber to chemically adsorb the first reactant onto a substrate, the first reactant being bubbled by a first gas that is preheated, purging the chamber to remove residues on the substrate having the first reactant chemically adsorbed, and forming the thin film by a means of chemical displacement by supplying a second reactant to the chamber to chemically adsorb the second reactant onto the substrate.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: September 25, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyun Yeo, Young-Wook Park, Ki-Chul Kim, Jae-Jong Han
  • Patent number: 7270765
    Abstract: To provide a composition for forming a dielectric layer excellent in dielectric constant and withstand voltage properties, a MIM capacitor and a process for its production. A composition for forming a dielectric layer, which comprises fine particles of perovskite type dielectric crystal, glass frit, and a hydrolysable silicon compound or its oligomer, and a MIM capacitor comprising a substrate, and a bottom electrode layer, a dielectric layer having a structure such that fine particles of perovskite type dielectric crystal are dispersed in a silicon oxide matrix containing glass-forming ions and a top electrode, formed on the substrate in this order.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: September 18, 2007
    Assignee: Asahi Glass Company, Limited
    Inventors: Hiroyuki Tomonaga, Katsuaki Miyatani, Yoshihisa Beppu, Kumiko Takahashi, Kazuo Sunahara
  • Patent number: 7271112
    Abstract: Methods of forming conformal films with increased density are described. The methods may be used to improve gap fill in semiconductor device manufacturing by eliminating seams and voids. The methods involve operating at high reactant partial pressure. Additionally, film properties may be further enhanced by optimizing the temperature of the substrate during exposure to the metal-containing and/or silicon-containing precursor gases commonly used in conformal film deposition techniques such as ALD and PDL.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: September 18, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: George D. Papasouliotis, Raihan M. Tarafdar, Adrianne K. Tipton, Ron Rulkens, Dennis M. Hausmann, Jeff Tobin
  • Patent number: 7268089
    Abstract: A method of forming a PE-TEOS layer of a semiconductor IC device provides uniformly thick PE-TEOS layers on a batch of wafers. First, a loading wafer cassette is prepared to provide the wafers to be processed. Next, a process atmosphere is pre-created in a processing chamber. Then the wafers are supplied in sequence into the chamber from the loading wafer cassette and the wafers are mounted on a heater table in the chamber. Next, the PE-TEOS layer is deposited on the wafers by spraying a process gas into the chamber through showerheads. Next, the wafers are discharged from the chamber. Once the chamber is cleared of wafers, the inside of the chamber is cleaned by supplying a cleaning gas into the chamber, and exciting the cleaning gas with RF power. Subsequently, more TEOS gas is supplied into the chamber through the showerheads without being excited by RF power to especially reduce the temperature of the showerheads and that prevailing inside the chamber.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: September 11, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Bong-Jun Jang
  • Patent number: 7265064
    Abstract: In a method of manufacturing a semiconductor device, semiconductor circuit elements or wiring patterns are formed on a semiconductor substrate then, a porous semiconductor oxide film is formed as an interlayer insulating film on the semiconductor substrate including the semiconductor circuit elements or wiring patterns by oxidizing semiconductor substance in a mixture gas containing an oxygen gas in a chamber.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: September 4, 2007
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Hiroshi Morisaki, Shinji Nozaki
  • Publication number: 20070202710
    Abstract: A method for fabricating a semiconductor device includes forming a layer to be etched, forming a hard mask pattern over the layer, and etching the layer to form a pattern. The hard mask pattern has an atomic percentage of a silicon-hydrogen bond varying with a thickness of the hard mask pattern.
    Type: Application
    Filed: December 29, 2006
    Publication date: August 30, 2007
    Inventors: Ki-Won Nam, Ky-Hyun Han
  • Patent number: 7259111
    Abstract: A method of depositing a organosilicate dielectric layer exhibiting high adhesion strength to an underlying substrate disposed within a single processing chamber without plasma arcing. The method includes positioning a substrate within a processing chamber having a powered electrode, flowing an interface gas mixture into the processing chamber, the interface gas mixture comprising one or more organosilicon compounds and one or more oxidizing gases, depositing a silicon oxide layer on the substrate by varying process conditions, wherein DC bias of the powered electrode varies less than 60 volts.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: August 21, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Deenesh Padhi, Ganesh Balasubramanian, Annamalai Lakshmanan, Zhenjiang Cui, Juan Carlos Rocha-Alvarez, Bok Hoen Kim, Hichem M'Saad, Steven Reiter, Francimar Schmitt
  • Patent number: 7253065
    Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: August 7, 2007
    Assignee: International Business Machines Corporation
    Inventors: Joerg Appenzeller, Phaedon Avouris, Kevin K. Chan, Philip G. Collins, Richard Martel, Hon-Sum Philip Wong
  • Patent number: 7250380
    Abstract: This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing an aluminum containing organic precursor to a chamber containing a semiconductor substrate effective to deposit an aluminum comprising layer over the substrate. An alkoxysilanol is flowed to the substrate comprising the aluminum comprising layer within the chamber effective to deposit a silicon dioxide comprising layer over the substrate.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: July 31, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Chris W. Hill
  • Publication number: 20070161254
    Abstract: Lowering the temperature at which an oxide layer is formed produces a passivation layer with improved adhesion characteristics and crack resistance. The method of forming the passivation layer includes first forming an intermetal dielectric layer over a lower metal layer of a semiconductor device. A via is formed in the intermetal dielectric layer. A metal line is formed on the via. A passivation layer is formed over the substrate including the metal line, the passivation layer being formed at a temperature of 300˜350° C. by a high density plasma chemical vapor deposition process.
    Type: Application
    Filed: December 26, 2006
    Publication date: July 12, 2007
    Inventor: Tae Young Lee
  • Publication number: 20070161259
    Abstract: Disclosed herein is a method of fabricating a two dimensional (2D) nanostructure. The method includes heating a substrate within a vacuum chamber, injecting a metallic material into the vacuum chamber, adsorbing the metallic material on a surface of the substrate, and cooling the substrate to fabricate the 2D nanostructure on the surface of the substrate. The 2D nanostructures can be fabricated as monolayers.
    Type: Application
    Filed: October 11, 2006
    Publication date: July 12, 2007
    Applicant: SAMSUNG ELECTRONICS CO. LTD.
    Inventors: Se-ahn Song, Alexander V. Latyshev, Ludmila I. Fedina, Anton K. Gutakovskii, Sergey S. Kosolobov
  • Patent number: 7241703
    Abstract: A method of forming films in a semiconductor device that can appropriately control a resistance value of a thin film resistance on an ozone TEOS film while preventing a metal thin film from remaining around a surface step unit after the metal thin film was dry etched. First, as shown in FIG. 1A, a step unit with the height of about 1 ?m is formed by forming elements such as HBT on a semiconductor substrate made up of semi-insulating GaAs. Next, as shown in FIG. 1B, a first ozone TEOS film with the thickness of 900 nm by a Normal pressure CVD method using mixed gas of tetraethoxysilane with ozone. Then, a second ozone TEOS film with the thickness of 100 nm is formed by reducing the ozone concentration to 10 g/m3, while maintaining the substrate temperature at 350° C.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: July 10, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Hikita, Yasuhiro Uemoto
  • Patent number: 7238625
    Abstract: The present invention provides a method for processing a semiconductor device wherein a dielectric layer is partially converted into a silicon-oxy-nitride by incorporation of nitrogen atoms into the dielectric layer, which comprises a silicon oxide. Before the introduction of the nitrogen atoms into the dielectric layer, the dielectric layer is provided as a silicon oxide in which the atomic silicon to oxygen ration is greater than ½. In this way, MOS transistors are obtained with a high quality interface between the dielectric region and semiconductor substrate, and a dielectric region which is impermeable to impurity atoms from the gate region and which has a thickness which is substantially equal to the dielectric layer as deposited.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: July 3, 2007
    Assignees: Interuniversitair Microelektronika Centrum (IMEC), Koninklijke Philips Electronics N.V.
    Inventors: Vincent Charles Venezia, Florence Nathalie Cubaynes
  • Patent number: 7235498
    Abstract: This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous oxide (N2O) and ozone (O3). The presence of O3 in the oxidizing ambiance greatly enhances the oxidation rate compared to an ambiance in which N2O is the only oxidizing agent. In addition to enhancing the oxidation rate of silicon, it is hypothesized that the presence of O3 interferes with the growth of a thin silicon oxynitride layer near the interface of the silicon dioxide layer and the unreacted silicon surface which makes oxidation in the presence of N2O alone virtually self-limiting. The presence of O3 in the oxidizing ambiance does not impair oxide reliability, as is the case when silicon is oxidized with N2O in the presence of a strong, fluorine-containing oxidizing agent such as NF3 or SF6.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: June 26, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Singh Sandhu, Randhir P S Thakur