Abstract: A method for pre-treating an epitaxial layer performed before evaluation of the epitaxial layer by making the epitaxial layer contact with a metal electrode by a capacitance-voltage measurement, the method comprising; applying carbon-bearing compound to a surface of the epitaxial layer; subsequently irradiating ultraviolet light to the surface of the epitaxial layer; and thereby forming an oxide film on the surface of the epitaxial layer.

Abstract: A single chip wireless sensor (1) comprises a microcontroller (2) connected by a transmit/receive interface (3) to a wireless antenna (4). The microcontroller (2) is also connected to an 8 kB RAM (5), a USB interface (6), an RS232 interface (8), 64 kB flash memory (9), and a 32 kHz crystal (10). The device (1) senses humidity and temperature, and a humidity sensor (11) is connected by an 18 bit ?? A-to-D converter (12) to the microcontroller (2) and a temperature sensor (13) is connected by a 12 bit SAR A-to-D converter (14) to the microcontroller (2). The device (1) is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process.

Abstract: Methods for reducing and inhibiting defect formation on silicon dioxide formed by atomic layer deposition (ALD) are disclosed. Defect reduction is accomplished by performing processing on the silicon dioxide subsequent to deposition by ALD. The post-deposition processing may include at least one of a pump/purge cycle and a water exposure cycle performed after formation of the silicon dioxide on a substrate.

Abstract: A corrosion resistant component of a plasma chamber includes a liquid crystalline polymer. In a preferred embodiment, the liquid crystalline polymer (LCP) is provided on an aluminum component having an anodized or non-anodized surface. The liquid crystalline polymer can also be provided on an alumina component. The liquid crystalline polymer can be deposited by a method such as plasma spraying. The liquid crystalline polymer may also be provided as a preformed sheet or other shape adapted to cover the exposed surfaces of the reaction chamber. Additionally, the reactor components may be made entirely from liquid crystalline polymer by machining the component from a solid block of liquid crystalline polymer or molding the component from the polymer. The liquid crystalline polymer may contain reinforcing fillers such as glass or mineral fillers.

Abstract: Properties of a hard mask liner are used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack. According to one embodiment, there is provided a method in which there is defined a portion on a surface of an IC interconnect stack as being specific to air cavity introduction, with the defined portion being smaller than the surface of the substrate. At least one metal track is produced within the interconnect stack, and there is deposited at least one interconnect layer having a sacrificial material and a permeable material within the interconnect stack. There is defined at least one trench area surrounding the defined portion and forming at least one trench, and a hard mask layer is deposited to coat the trench. At least one air cavity is formed below the defined portion of the surface by using a removal agent for removing the sacrificial material to which the permanent material is resistant.

Abstract: A heat processing method for a semiconductor process includes placing a plurality of target substrates stacked at intervals in a vertical direction within a process field of a process container. Each of the target substrates includes a process object layer on its surface. Then, the method includes supplying an oxidizing gas and a deoxidizing gas to the process field while heating the process field, thereby causing the oxidizing gas and the deoxidizing gas to react with each other to generate oxygen radicals and hydroxyl group radicals, and performing oxidation on the process object layer of the target substrates by use of the oxygen radicals and the hydroxyl group radicals. Then, the method includes heating the process object layer processed by the oxidation, within an atmosphere of an annealing gas containing ozone or oxidizing radicals, thereby performing annealing on the process object layer.

Abstract: A method for forming a diffused, doped backside layer on a device wafer oxide bonded to a handle wafer in an integrated circuit is provided. The method comprises forming a thermal bond oxide layer on a backside surface of the device wafer of the integrated circuit. Implanting the bond oxide with a diffusing dopant. Diffusing dopant from the bond oxide into the backside surface of the device wafer. Depositing an oxide layer on the bond oxide and bonding the deposited oxide layer to the handle wafer of the integrated circuit.

Abstract: A method for manufacturing a semiconductor device which includes: alternately supplying a silicon source and an oxidant to deposit a silicon oxide film on a surface of a semiconductor substrate, wherein the silicon source is supplied under a supply condition where an adsorption amount of molecules of the silicon source on the semiconductor substrate is increased without causing an adsorption saturation of the molecules of the silicon source on the semiconductor substrate, and wherein the oxidant is supplied under a supply condition where impurities remain in the molecules of the silicon source adsorbed on the semiconductor substrate.

Abstract: The present invention contemplates a variety of methods and techniques for fabricating an improved carbon nanotube (CNT) device such as an AFM probe. A CNT is first formed on a desired location such as a substrate. The CNT and substrate are then covered with a protective layer through a CVD or other suitable process. Then a length of the CNT is exposed through etching or other suitable process, the exposed length being formed to a length suitable for a desired application for the CNT device.

Abstract: Semiconductor devices containing a CVD BPSG layer and an undoped CVD oxide cap layer are described. The cap layer can be any silicon oxide material with a thickness between about 50 ? and about 350 ?. The cap layer may be formed using a low temperature CVD process that is controlled for density by adjusting the amount of silicon precursor in the gas-phase. In some embodiments, the cap layer is deposited on the BPSG layer followed immediately by the BPSG film deposition prior to any annealing of the BPSG layer. The cap layer may prevent dopant out-diffusion and/or out-gassing during storage and high-temperature annealing, and moisture penetration into the BPSG layer, as well as suppress defect nucleation on the as-deposited BPSG surface and defect formation during high temperature annealing, while still allowing flow ability of the BPSG layer. Other embodiments are also described.

Abstract: A method of forming a device includes forming protective shells about metallic nanocrystals supported by a substrate. The metallic nanocrystals having protective shells are encapsulated with a layer formed with process parameters that are not compatible with the integrity of unprotected metallic nanocrystals.

Abstract: A method for using a film formation apparatus includes, in order to inhibit metal contamination: performing a cleaning process using a cleaning gas on an inner wall of a process container and a surface of a holder with no productive target objects held thereon; and then, performing a coating process of forming a silicon nitride film by alternately supplying a silicon source gas and a nitriding gas to cover with the silicon nitride film the inner wall of the process container and the surface of the holder with no productive target objects held thereon.

Abstract: A method of fabricating a liquid crystal display device includes performing a first mask process to form a gate line, a gate pad, and a gate electrode on a substrate. The method of fabricating a liquid crystal display device further includes performing a second mask process to form an active layer on the gate electrode, performing a third mask process to form a pixel electrode contacting the active layer, and performing a fourth mask process to form a source electrode and a drain electrode on the active layer.

Abstract: A method is provided for forming a rare earth element-doped silicon oxide (SiO2) precursor with nanocrystalline (nc) Si particles. In one aspect the method comprises: mixing Si particles into a first organic solvent, forming a first solution with a first boiling point; filtering the first solution to remove large Si particles; mixing a second organic solvent having a second boiling point, higher than the first boiling point, to the filtered first solution; and, fractionally distilling, forming a second solution of nc Si particles. The Si particles are formed by immersing a Si wafer into a third solution including hydrofluoric (HF) acid and alcohol, applying an electric bias, and forming a porous Si layer overlying the Si wafer. Then, the Si particles are mixed into the organic solvent by depositing the Si wafer into the first organic solvent, and ultrasonically removing the porous Si layer from the Si wafer.

Abstract: A method for producing an inkjet head for jetting an ink from a nozzle that is formed on a nozzle main body formed of a metal material, the method includes smoothening a surface of the nozzle main body, applying a silica sol solution to the nozzle main body so as to form a silica sol film, wherein the silica sol solution has a concentration that is controlled to avoid a nozzle clogging in the nozzle main body, heating the silica sol film formed on the nozzle main body to thereby convert the silica sol film into an SiO2 film, applying an ink repellent agent solution to the SiO2 film and drying to thereby form an ink repellent film, wherein the ink repellent agent solution is prepared by dissolving a compound having an alkoxysilane residue at an end of a perfluoro polyether chain in a solvent.

Abstract: A hermetic interconnect is fabricated on a substrate by forming a stud of conductive material over a metallization layer, and then overcoating the stud of conductive material and the metallization layer with a layer of compliant dielectric material. In one embodiment, the layer of compliant dielectric material is low Young's modulus silicon dioxide, formed by sputter-deposition at low temperature, in a low pressure argon atmosphere. The interconnect may provide electrical access to a micromechanical device, which is enclosed with a capping wafer hermetically sealed to the substrate with an AuInx alloy bond.

Abstract: This method for manufacturing an SOI wafer includes: a step of forming insulating films in a front surface and a mirror-polished rear surface of an active layer wafer; a step of removing the insulating film in the front surface of the active layer wafer; a step of subjecting the active layer wafer to a rapid thermal annealing process; a step of bonding the active layer wafer and a support wafer with the insulating film formed in the rear surface therebetween so as to form a bonded wafer; a step of subjecting the bonded wafer to a heat treatment for bonding enhancement which enhances a bonding strength between the active layer wafer and the support wafer; and a step of thinning the active layer wafer in the bonded wafer so as to form an SOI layer.

Abstract: A spin-on glass (SOG) composition and a method of forming a silicon oxide layer utilizing the SOG composition are disclosed. The method includes coating on a semiconductor substrate having a surface discontinuity, an SOG composition containing polysilazane having a compound of the formula —(SiH2NH)n— wherein n represents a positive integer, a weight average molecular weight within the range of about 3,300 to 3,700 to form a planar SOG layer. The SOG layer is converted to a silicon oxide layer with a planar surface by curing the SOG layer. Also disclosed is a semiconductor device made by the method.

Abstract: A method for forming an insulation film on a semiconductor substrate by plasma reaction includes: vaporizing a silicon-containing hydrocarbon having a Si—O bond compound to provide a source gas; introducing the source gas and a carrier gas without an oxidizing gas into a reaction space for plasma CVD processing; and forming an insulation film constituted by Si, C, O, and H on a substrate by plasma reaction using a combination of low-frequency RF power and high-frequency RF power in the reaction space. The plasma reaction is activated while controlling the flow of the reaction gas to lengthen a residence time, Rt, of the reaction gas in the reaction space.

Abstract: A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3.

Abstract: There are provided lamella structured thin films having ultralow dielectric constants and high hardness, and the method for manufacturing the same. In the lamella structured thin film, silica layers and air layers are alternately and repeatedly stacked on the surface of a wafer in the vertical direction. The method of manufacturing the lamella structured thin film includes, agitating silica sol solution containing surfactant and silica precursor, spin-coating the solution on silicon wafer, aging the wafer, and annealing the wafer to remove the surfactant and organic materials from the wafer. The lamella structured thin film has excellent mechanical strength and high chemical stability, and in particular, has significantly low dielectric constant of no more than 2.5 and high hardness. In the method of manufacturing the lamella structured thin film, semiconductor processes can be made simple and economical since only pure silica is used and no additionally surface treatment is performed.

Abstract: A neutral beam-assisted atomic layer chemical vapor deposition (ALCVD) apparatus is provided for uniformly depositing an oxide layer filling a planarization layer or a trench to increase uniformity and density of the oxide layer using neutral beams generated by a neutral beam generator without a seam or void occurring in an atomic layer deposition (ALD) or ALD-like chemical vapor deposition (CVD) process, thereby solving problems on the void or seam and low density occurring when a high-density planarization layer or a shallow trench having a width of 65 nm or less is formed, and improving a next generation oxide layer isolation process.

Abstract: A silicon-containing insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas including di-iso-propylaminosilane gas and a second process gas including an oxidizing gas or nitriding gas. The film is formed by performing a plurality of times a cycle alternately including first and second steps. The first step performs supply of the first process gas, thereby forming an adsorption layer containing silicon on a surface of the target substrate. The second performs supply of the second process gas, thereby oxidizing or nitriding the adsorption layer on the surface of the target substrate. The second step includes an excitation period of supplying the second process gas to the process field while exciting the second process gas by an exciting mechanism.

Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500 ° C. to about 1300 ° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.

Abstract: A method in which a SOI substrate structure is fabricated by oxidation of graded porous Si is provided. The graded porous Si is formed by first implanting a dopant (p- or n-type) into a Si-containing substrate, activating the dopant using an activation anneal step and then anodizing the implanted and activated dopant region in a HF-containing solution. The graded porous Si has a relatively coarse top layer and a fine porous layer that is buried beneath the top layer. Upon a subsequent oxidation step, the fine buried porous layer is converted into a buried oxide, while the coarse top layer coalesces into a solid Si-containing over-layer by surface migration of Si atoms.

Abstract: The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature of greater than or equal to 350° C. while exposing the construction to a deuterium-enriched ambient.

Abstract: A process for forming dielectric films containing at least metal atoms, silicon atoms, and oxygen atoms on a silicon substrate comprises a first step of oxidizing a surface portion of the silicon substrate to form a silicon dioxide film; a second step of forming a metal film on the silicon dioxide film in a non-oxidizing atmosphere; a third step of heating in a non-oxidizing atmosphere to diffuse the metal atoms constituting the metal film into the silicon dioxide film; and a fourth step of oxidizing the silicon dioxide film containing the diffused metal atoms to form the film containing the metal atoms, silicon atoms, and oxygen atoms.

Abstract: A method for forming dielectric films including metal nitride silicate on a silicon substrate, comprises a first step of depositing a film containing metal and silicon on a silicon substrate in a non-oxidizing atmosphere using a sputtering method; a second step of forming a film containing nitrogen, metal and silicon by nitriding the film containing metal and silicon; and a third step of forming a metal nitride silicate film by oxidizing the film containing nitrogen, metal and silicon.

Abstract: A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region; performing a first rapid thermal annealing (RTA) process; removing the spacer and forming a high tensile stress film over the surface of the gate and the source/drain region; and performing a second rapid thermal annealing process.

Abstract: Adhesion of a porous low K film to an underlying barrier layer is improved by forming an intermediate layer lower in carbon content, and richer in silicon oxide, than the overlying porous low K film. This adhesion layer can be formed utilizing one of a number of techniques, alone or in combination. In one approach, the adhesion layer can be formed by introduction of a rich oxidizing gas such as O2/CO2/etc. to oxidize Si precursors immediately prior to deposition of the low K material. In another approach, thermally labile chemicals such as alpha-terpinene, cymene, and any other non-oxygen containing organics are removed prior to low K film deposition. In yet another approach, the hardware or processing parameters, such as the manner of introduction of the non-silicon containing component, may be modified to enable formation of an oxide interface prior to low K film deposition.

Abstract: The present invention provides a semiconductor device that can restrict the dissolution hindering phenomenon in a chemically amplified resist film. More specifically, after the formation of a contact pattern on a semiconductor substrate, a wiring pattern is formed on the contact pattern. A SiC film, a first SiOC film, a SiC film, a second SiOC film, a USG film as a diffusion preventing film, and a silicon nitride film as a reflection preventing film, are formed on the wiring pattern. A dual damascene structure is then formed using the chemically amplified resist film and another chemically amplified resist film. In this manner, the N2 gas generated during the formation of the silicon nitride film as a reflection preventing film can be prevented from diffusing into the second SiOC film formed under the silicon nitride film. Accordingly, the reaction of the N2 gas with the H group contained in the second SiOC film and the generation of an amine group such as NH in the second SiOC film can be prevented.

Abstract: A method of manufacturing a semiconductor device according to one aspect of the present invention comprises: forming a gate insulation film on a semiconductor substrate in which element separation regions are formed; depositing a gate lower layer material on the semiconductor substrate via the gate insulation film; depositing a gate upper layer material, which is composed of a material different from the gate lower layer material, on the gate lower layer material; forming a gate comprising a gate upper layer and a gate lower layer by selectively processing the gate upper layer material and the gate lower layer material; increasing the size of the gate upper layer in a horizontal direction with respect to the semiconductor substrate by carrying out a chemical reaction processing treatment to which the gate upper layer has a higher reaction speed than the gate lower layer; forming an impurity implantation region by implanting ions into the semiconductor substrate using the gate upper layer as a mask; and formin

Abstract: A method of forming a silicon oxide layer on a substrate. The method includes providing a substrate and forming a first silicon oxide layer overlying at least a portion of the substrate, the first silicon oxide layer including residual water, hydroxyl groups, and carbon species. The method further includes exposing the first silicon oxide layer to a plurality of silicon-containing species to form a plurality of amorphous silicon components being partially intermixed with the first silicon oxide layer. Additionally, the method includes annealing the first silicon oxide layer partially intermixed with the plurality of amorphous silicon components in an oxidative environment to form a second silicon oxide layer on the substrate. At least a portion of amorphous silicon components are oxidized to become part of the second silicon oxide layer and unreacted residual hydroxyl groups and carbon species in the second silicon oxide layer are substantially removed.

Abstract: A method of manufacturing a semiconductor device includes forming a trench for isolation on a surface of a substrate including a semiconductor substrate, filling the trench with a solution containing a perhydrosilazane polymer by applying the solution on the substrate, converting the solution into a film containing the perhydrosilazane polymer by heating the solution, and converting the film into a silicon dioxide film including heating the film at a first temperature in an atmosphere containing vapor, and heating the film heated at the first temperature at a second temperature lower than the first temperature in an atmosphere containing vapor or in pure water.

Abstract: Semiconductor devices, in particular nitride semiconductor devices for use in the manufacture of laser diodes, prevent peeling-off of the electrode, and at the same time reduces the complexity of processes and a reduction in yield. A nitride semiconductor device according to the invention includes a P-type nitride semiconductor layer with a ridge on its surface, an SiO2 film covering at least the side face of the ridge, an adherence layer formed on a surface of the SiO2 film and composed mainly of silicon, and a P-type electrode formed on the upper surface of the ridge and on a surface of the adherence layer.

Abstract: A vertical plasma processing apparatus for a semiconductor process for performing a plasma process on target substrates all together includes an exciting mechanism configured to turn at least part of a process gas into plasma. The exciting mechanism includes first and second electrodes provided to a plasma generation box and facing each other with a plasma generation area interposed therebetween, and an RF power supply configured to supply an RF power for plasma generation to the first and second electrodes and including first and second output terminals serving as grounded and non-grounded terminals, respectively. A switching mechanism is configured to switch between a first state where the first and second electrodes are connected to the first and second output terminals, respectively, and a second state where the first and second electrodes are connected to the second and first output terminals, respectively.

Abstract: A semiconductor device having improved adhesiveness between films composing an interlayer insulating film is presented by providing multilayered films in the interlayer insulating films having film density distribution, in which the film density is gradually changes. A SiOC film is deposited to a thickness of 300 nm via a plasma CVD process, in which a flow rate of trimethylsilane gas is stepwise increased. In this case, the film density of the deposited SiOC film is gradually decreased by stepwise increasing the flow rate of trimethylsilane gas. Since trimethylsilane contains methyl group, trimethylsilane has more bulky molecular structure in comparison with monosilane or the like. Thus, the film density is decreased by increasing the amount of trimethylsilane in the reactant gas.

Abstract: A method of making a doped silicon oxide thin film using a doped silicon oxide precursor solution includes mixing a silicon source in an organic acid and adding 2-methoxyethyl ether to the silicon source and organic acid to from a preliminary precursor solution. The resultant solution is heated, stirred and filtered. A doping impurity is dissolved in 2-methoxyethanol to from a doped source solution, and the resultant solution mixed with the previously described resultant solution to from a doped silicon oxide precursor solution. A doped silicon oxide thin film if formed on a wafer by spin coating. The thin film and the wafer are baked at progressively increasing temperatures and the thin film and the wafer are annealed.

Abstract: Gate and storage dielectric systems and methods of their fabrication are presented. A passivated overlayer deposited between a layer of dielectric material and a gate or first storage plate maintains a high K (dielectric constant) value of the dielectric material. The high K dielectric material forms an improved interface with a substrate or second plate. This improves dielectric system reliability and uniformity and permits greater scalability, dielectric interface compatibility, structural stability, charge control, and stoichiometric reproducibility. Furthermore, etch selectivity, low leakage current, uniform dielectric breakdown, and improved high temperature chemical passivity also result.

Abstract: A semiconductor device manufacturing method including a process of forming a silicon oxide film by thermally oxidizing silicon in the atmosphere of oxygen gas or in the atmosphere of mixed gas of oxygen and hydrogen at a temperature of 800° C. or more in the state in which at least the silicon surface serving as a light-receiving portion of a photodiode is exposed, and a process of depositing a silicon nitride film on the silicon oxide film. At least the silicon oxide film and the silicon nitride film are finally left on the surface of the photodiode as an antireflection film.

Abstract: A method of depositing a silicon and nitrogen containing film on a substrate. The method includes introducing silicon-containing precursor to a deposition chamber that contains the substrate, wherein the silicon-containing precursor comprises at least two silicon atoms. The method further includes generating at least one radical nitrogen precursor with a remote plasma system located outside the deposition chamber. Moreover, the method includes introducing the radical nitrogen precursor to the deposition chamber, wherein the radical nitrogen and silicon-containing precursors react and deposit the silicon and nitrogen containing film on the substrate. Furthermore, the method includes annealing the silicon and nitrogen containing film in a steam environment to form a silicon oxide film, wherein the steam environment includes water and acidic vapor.

Abstract: Methods of achieving high breakdown voltages in semiconductor devices by suppressing the surface flashover using high dielectric strength insulating encapsulation material are generally described. In one embodiment of the present invention, surface flashover in AlGaN/GaN heterostructure field-effect transistors (HFETs) is suppressed by using high dielectric strength insulating encapsulation material. Surface flashover in as-fabricated III-Nitride based HFETs limits the operating voltages at levels well below the breakdown voltages of GaN.

Abstract: For avoiding the metallic inner surface of a PECVD reactor to influence thickness uniformity and quality uniformity of a ?c-Si layer (19) deposited on a large-surface substrate, (15) before each substrate is single treated at least parts of the addressed wall are precoated with a dielectric layer (13).

Abstract: Porous dielectric layers are produced by embedding and removing nanoparticles in composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.

Abstract: A method of manufacturing a high voltage semiconductor device including forming a P-type region implanted with P-type impurities and an N-type region implanted with N-type impurities in a silicon substrate. The method further includes forming a silicon nitride layer pattern and a pad oxide layer pattern to expose a surface of the silicon substrate, forming a trench by etching the exposed silicon substrate using the silicon nitride layer pattern as an etch mask, forming a trench oxide layer pattern in the trench by removing the silicon nitride layer pattern and the pad oxide layer pattern, and simultaneously forming a deep P-well and a deep N-well by driving P-type impurities in the P-type region and N-type impurities in the N-type region into the silicon substrate, while forming a gate oxide layer on a silicon substrate including the trench oxide layer pattern.

Abstract: A method for patterning a polished silicon surface is disclosed, the method including steps leading to an organic monolayer on at least a part of the silicon surface, the monolayer being functionalized in specific desired locations. The method can be used to produce a device comprising one or more FET structures, the gate of the FET being formed by the functionalized organic monolayer. The functionalized monolayer preferably contains oligosaccharides or oligopeptides which are capable of interacting with biological substance, such that the device acts as a bio-sensor.

Abstract: A method of forming a silicon-containing film comprising providing a substrate in a reaction chamber, injecting into the reaction chamber at least one silicon-containing compound; injecting into the reaction chamber at least one co-reactant in the gaseous form; and reacting the substrate, silicon-containing compound, and co-reactant in the gaseous form at a temperature equal to or less than 550° C. to obtain a silicon-containing film deposited onto the substrate. A method of preparing a silicon nitride film comprising introducing a silicon wafer to a reaction chamber; introducing a silicon-containing compound to the reaction chamber; purging the reaction chamber with an inert gas; and introducing a nitrogen-containing co-reactant in gaseous form to the reaction chamber under conditions suitable for the formation of a monomolecular layer of a silicon nitride film on the silicon wafer.

Abstract: A processing chamber is seasoned by providing a flow of season precursors to the processing chamber. A high-density plasma is formed from the season precursors by applying at least 7500 W of source power distributed with greater than 70% of the source power at a top of the processing chamber. A season layer having a thickness of at least 5000 ? is deposited at one point using the high-density plasma. Each of multiple substrates is transferred sequentially into the processing chamber to perform a process that includes etching. The processing chamber is cleaned between sequential transfers of the substrates.

Abstract: A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

Abstract: Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.