Using Electromagnetic Or Wave Energy (e.g., Photo-induced Deposition, Plasma, Etc.) Patents (Class 438/788)
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Patent number: 8637403Abstract: A method of manufacturing a semiconductor structure includes varying local chemical mechanical polishing (CMP) abrading rates of an insulator film by selectively varying a carbon content of the insulator film.Type: GrantFiled: December 12, 2011Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Yoba Amoah, Graham M. Bates, Joseph P. Hasselbach, Thomas L. McDevitt, Eva A. Shah
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Patent number: 8603908Abstract: A method for preventing formation of metal silicide material on a wafer bevel is provided, where the wafer bevel surrounds a central region of the wafer. The wafer is placed in bevel plasma processing chamber. A protective layer is deposited on the wafer bevel. The wafer is removed from the bevel plasma processing chamber. A metal layer is deposited over at least part of the central region of the wafer, wherein part of the metal layer is deposited over the protective layer. Semiconductor devices are formed while preventing metal silicide formation on the wafer bevel.Type: GrantFiled: May 6, 2011Date of Patent: December 10, 2013Assignee: Lam Research CorporationInventors: Andreas Fischer, William Scott Bass
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Patent number: 8597978Abstract: A method for forming a semiconductor device includes physically attaching a first semiconductor die to front surface of a first substrate. The first die is electrically connected to routings on front surface of the first substrate. The routings are electrically connected with conductive pads on back surface of the first substrate. A second semiconductor die is physically attached to front surface of a second substrate. The die is electrically connected to routings on front surface of second substrate. These routings are electrically connected with conductive pads on front surface of the second substrate. A third semiconductor die is physically attached to the second die. The third die is electrically attached to the second die through a plurality of through substrate vias (TSVs) within the second die. The conductive pads on back surface of first substrate are electrically connected to the conductive pads on front surface of second substrate.Type: GrantFiled: May 17, 2012Date of Patent: December 3, 2013Assignee: Texas Instruments IncorporatedInventors: Kurt Wachtler, Margaret Rose Simmons-Matthews
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Patent number: 8598706Abstract: A method for forming an interlayer dielectric film by a plasma CVD method, including turning off a radio frequency power and purging with an inert gas simultaneously.Type: GrantFiled: September 17, 2008Date of Patent: December 3, 2013Assignee: Renesas Electronics CorporationInventors: Hironori Yamamoto, Fuminori Ito, Yoshihiro Hayashi
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Publication number: 20130316547Abstract: A method for processing a wafer with a wafer bevel that surrounds a central region is provided. The wafer is placed in a bevel plasma processing chamber. A protective layer is deposited on the wafer bevel without depositing the protective layer over the central region. The wafer is removed from the bevel plasma processing chamber. The wafer is further processed.Type: ApplicationFiled: August 2, 2013Publication date: November 28, 2013Inventors: Andreas Fischer, William Scott Bass
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Patent number: 8586486Abstract: A method of patterning a material layer of a semiconductor device is disclosed, the method including treating a material layer above a semiconductor substrate with plasma oxygen; depositing a layer of photoresist over a first surface of the material layer after the treating of the material layer; patterning the layer of photoresist, thereby forming a patterned photoresist, exposing portions of the material layer; etching the exposed portions of at least the material layer to form at least one contact via in the material layer extending to a source or drain region of a device at a surface of the substrate; and removing the patterned photoresist from the first surface of the material layer.Type: GrantFiled: December 16, 2011Date of Patent: November 19, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jen-Yi Chen, Kun-Ei Chen, Ling-Sung Wang, Chen-Chieh Chiang
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Patent number: 8575041Abstract: Damaged surface areas of low-k dielectric materials may be efficiently repaired by avoiding the saturation of dangling silicon bonds after a reactive plasma treatment on the basis of OH groups, as is typically applied in conventional process strategies. The saturation of the dangling bond may be accomplished by directly initiating a chemical reaction with appropriate organic species, thereby providing superior reaction conditions, which in turn results in a more efficient restoration of the dielectric characteristics.Type: GrantFiled: September 15, 2011Date of Patent: November 5, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Matthias Schaller, Daniel Fischer, Thomas Oszinda
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Publication number: 20130288486Abstract: The invention relates to a method of depositing silicon dioxide films using plasma enhanced chemical vapour deposition (PECVD) and more particularly using tetraethyl orthosilicate (TEOS). The process can be carried out at standard temperatures and also at low temperatures which is useful for manufacturing wafers with through silicon vias.Type: ApplicationFiled: April 24, 2013Publication date: October 31, 2013Applicant: SPTS TECHNOLOGIES LIMITEDInventors: KATHRINE CROOK, ANDREW PRICE, MARK CARRUTHERS, DANIEL ARCHARD, STEPHEN BURGESS
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Patent number: 8569183Abstract: Semiconductor devices and methods for making such devices are described. The semiconductor devices contain dielectric layers that have been deposited and/or flowed by the application of microwave energy (“MW dielectric layers”). The dielectric layers can be made by providing a substrate in a reaction chamber, flowing a precursor gas mixture (containing atoms that react to form a dielectric material) in the reaction chamber, and then subjecting the gas mixture to microwave energy at a frequency and power density sufficient to cause the atoms of the precursor gas mixture to react and deposit to form a dielectric layer on the substrate. As well, the devices can be made by applying microwave energy to an already-deposited dielectric film at a frequency and power density sufficient to cause the atoms of the deposited dielectric material to flow.Type: GrantFiled: February 25, 2011Date of Patent: October 29, 2013Assignee: Fairchild Semiconductor CorporationInventor: Robert J. Purtell
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Publication number: 20130277723Abstract: Some embodiments include methods of forming silicon dioxide in which silicon dioxide is formed across silicon utilizing a first treatment temperature of no greater than about 1000° C., and in which an interface between the silicon dioxide and the silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. Some embodiments include methods of forming transistors in which a trench is formed to extend into monocrystalline silicon. Silicon dioxide is formed along multiple crystallographic planes along an interior of the trench utilizing a first treatment temperature of no greater than about 1000° C., and an interface between the silicon dioxide and the monocrystalline silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. A transistor gate is formed within the trench, and a pair of source/drain regions is formed within the monocrystalline silicon adjacent the transistor gate. Some embodiments include DRAM cells.Type: ApplicationFiled: April 19, 2012Publication date: October 24, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Shivani Srivastava, Kunal Shrotri, Fawad Ahmed
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Patent number: 8557667Abstract: By reducing a deposition rate and maintaining a low bias power in a plasma atmosphere, a spacer layer, for example a silicon nitride layer, may be deposited that exhibits tensile stress. The amount of tensile stress is controllable within a wide range, thereby providing the potential for forming sidewall spacer elements that modify the charge carrier mobility and thus the conductivity of the channel region of a field effect transistor.Type: GrantFiled: November 12, 2004Date of Patent: October 15, 2013Assignee: Globalfoundries Inc.Inventors: Hartmut Rülke, Katja Huy, Markus Lenski
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Patent number: 8547085Abstract: An arrangement for measuring process parameters within a processing chamber is provided. The arrangement includes a probe arrangement disposed in an opening of an upper electrode. Probe arrangement includes a probe head, which includes a head portion and a flange portion. The arrangement also includes an o-ring disposed between the upper electrode and the flange portion. The arrangement further includes a spacer made of an electrically insulative material positioned between the head portion and the opening of the upper electrode to prevent the probe arrangement from touching the upper electrode. The spacer includes a disk portion configured for supporting an underside of the flange portion. The spacer also includes a hollow cylindrical portion configured to encircle the head portion. The spacer forms a right-angled path between the o-ring and an opening to the processing chamber to prevent direct line-of-sight path between the o-ring and the opening to the processing chamber.Type: GrantFiled: July 7, 2009Date of Patent: October 1, 2013Assignee: Lam Research CorporationInventors: Jean-Paul Booth, Douglas Keil
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Patent number: 8541317Abstract: A substrate is mounted onto an elevated substrate support of a substrate carrier plate. The substrate carrier plate with the substrate is then placed in a plasma reactor. Due to the elevated substrate support, both opposite sides of the substrate are exposed to the plasma and are therefore coated with an electrical passivation layer.Type: GrantFiled: December 28, 2010Date of Patent: September 24, 2013Assignee: ABB Technology AGInventors: Kranthi Akurati, Magnus Kunow, Andreas Zimmermann, Ron Jervis
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Publication number: 20130224889Abstract: A charged particle beam apparatus is provided that enables faster semiconductor film deposition than the conventional deposition that uses silicon hydrides and halides as source gases. The charged particle beam apparatus includes a charged particle source 1, a condenser lens electrode 2, a blanking electrode 3, a scanning electrode 4, a sample stage 10 on which a sample 9 is mounted, a secondary charged particle detector 8 that detects a secondary charged particle 7 generated from the sample 9 in response to the charged particle beam irradiation, a reservoir 14 that accommodates cyclopentasilane as a source gas, and a gas gun 11 that supplies the source gas to the sample 9.Type: ApplicationFiled: September 22, 2011Publication date: August 29, 2013Applicants: HITACHI HIGH-TECH SCIENCE CORPORATION, JSR CORPORATION, JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Yoshihiro Koyama, Anto Yasaka, Tatsuya Shimoda, Yasuo Matsuki, Ryo Kawajiri
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Patent number: 8513809Abstract: A semiconductor device includes an interlayer insulation film, a wiring embedded in the interlayer insulation film and an air gap part formed between a side surface of the wiring and the interlayer insulation film. A first sidewall film is formed in the air gap part so that the first sidewall film contacts with the side surface of the wiring.Type: GrantFiled: May 6, 2011Date of Patent: August 20, 2013Assignee: Elpida Memory, Inc.Inventor: Yasuhiko Ueda
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Patent number: 8501631Abstract: A method for controlling a plasma processing system using wafer bias information derived from RF voltage information is proposed. The RF voltage is processed via an analog or digital methodology to obtain peak voltage information at least for each of the fundamental frequencies and the broadband frequency. The peak voltage information is then employed to derive the wafer bias information to serve as a feedback or control signal to hardware/software of the plasma processing system.Type: GrantFiled: December 7, 2010Date of Patent: August 6, 2013Assignee: Lam Research CorporationInventors: John C. Valcore, Jr., Henry S. Povolny
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Patent number: 8497214Abstract: A semiconductor device manufacturing method, the method including: forming a semiconductor element on a semiconductor substrate; and by using microwaves as a plasma source, forming an insulation film on the semiconductor element by performing a CVD process using microwave plasma having an electron temperature of plasma lower than 1.5 eV and an electron density of plasma higher than 1×1011 cm?3 near a surface of the semiconductor substrate.Type: GrantFiled: August 7, 2008Date of Patent: July 30, 2013Assignees: Tokyo Electron Limited, National University Corporation Tohoku UniversityInventors: Hirokazu Ueda, Toshihisa Nozawa, Takaaki Matsuoka, Akinobu Teramoto, Tadahiro Ohmi
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Publication number: 20130183834Abstract: Methods and apparatus for processing a substrate are provided. In some embodiments, a method of processing a substrate disposed in a process chamber includes performing a process on a substrate disposed in a process chamber having a substrate support ring configured to support the substrate and a reflector plate disposed proximate a back side of the substrate; providing a first gas comprising one of an oxygen containing gas or a nitrogen containing gas to a back side of the substrate via one or more through holes disposed in the reflector plate while performing the process on the substrate; and maintaining the process chamber at a first pressure proximate a top surface of the substrate and at a second pressure proximate the bottom surface of the substrate, wherein the first pressure is greater than the second pressure sufficiently to prevent dislodgement of the substrate from the substrate support ring during processing.Type: ApplicationFiled: January 9, 2013Publication date: July 18, 2013Applicant: APPLIED MATERIALS, INC.Inventor: APPLIED MATERIALS, INC.
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Patent number: 8486845Abstract: A method for depositing a film on a substrate using a plasma enhanced atomic layer deposition (PEALD) process includes disposing the substrate in a process chamber configured to facilitate the PEALD process, introducing a first process material within the process chamber and introducing a second process material within the process chamber. Also included is coupling electromagnetic power to the process chamber during introduction of the second process material in order to generate a plasma that facilitates a reduction reaction between the first and second process materials at a surface of the substrate. A reactive gas is introduced within the process chamber, the reactive gas chemically reacting with contaminants in the process chamber to release the contaminants from at least one of a process chamber component or the substrate.Type: GrantFiled: March 21, 2005Date of Patent: July 16, 2013Assignee: Tokyo Electron LimitedInventor: Tsukasa Matsuda
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Patent number: 8486792Abstract: A silicon compound gas, an oxidizing gas, and a rare gas are supplied into a chamber (2) of a plasma processing apparatus (1). A microwave is supplied into the chamber (2), and a silicon oxide film is formed on a target substrate with plasma generated by the microwave. A partial pressure ratio of the rare gas is 10% or more of a total gas pressure of the silicon compound gas, the oxidizing gas, and the rare gas, and an effective flow ratio of the silicon compound gas and the oxidizing gas (oxidizing gas/silicon compound gas) is not less than 3 but not more than 11.Type: GrantFiled: May 11, 2009Date of Patent: July 16, 2013Assignee: Tokyo Electron LimitedInventors: Hirokazu Ueda, Yoshinobu Tanaka, Yusuke Ohsawa, Toshihisa Nozawa, Takaaki Matsuoka
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Patent number: 8481403Abstract: Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manner gaps on the substrate are filled with a solid dielectric material. According to various embodiments, the methods involve reacting a dielectric precursor with an oxidant to form the dielectric material. In certain embodiments, the dielectric precursor condenses and subsequently reacts with the oxidant to form dielectric material. In certain embodiments, vapor phase reactants react to form a condensed flowable film.Type: GrantFiled: January 4, 2011Date of Patent: July 9, 2013Assignee: Novellus Systems, Inc.Inventors: Vishal Gauri, Raashina Humayun, Chi-I Lang, Judy H. Huang, Michael Barnes, Sunil Shanker
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Patent number: 8476099Abstract: Methods, structures, and design structures for improved adhesion of protective layers of imager microlens structures are disclosed. A method of fabricating a semiconductor structure includes forming an interfacial region between a microlens and a protective oxide layer. The interfacial region has a lower concentration of oxygen than the protective oxide layer.Type: GrantFiled: July 22, 2010Date of Patent: July 2, 2013Assignee: International Business Machines CorporationInventors: Edward C. Cooney, III, Jeffrey P. Gambino, Robert K. Leidy, Charles F. Musante, John G. Twombly
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Patent number: 8461031Abstract: A method for making a thin-film structure includes a thin film stabilized on a substrate. The structure of the thin film is defined by a material which includes at least one first chemical species. The method includes a step of inputting particles of the first chemical species into the thin film so as to compensate for the flow of vacancies from the surface of the film.Type: GrantFiled: October 25, 2006Date of Patent: June 11, 2013Assignee: Commissariat a l'Energie AtomiqueInventors: Joël Eymery, Pascal Pochet
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Patent number: 8453318Abstract: A method of making a planar coil is disclosed in the present invention. First, a substrate having a trench is provided. Then, a barrier and a seed layer are formed on the substrate in sequence. An isolative layer is used for guiding a conductive material to flow into a lower portion of the trench such that accumulation of the conductive material at opening of the trench is prevented before the lower portion of the trench is completely filled up, thereby avoiding gap formation in the trench.Type: GrantFiled: October 15, 2012Date of Patent: June 4, 2013Assignee: Touch Micro-System Technology Corp.Inventors: Hung Yi Lin, Ming Fa Chen
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Publication number: 20130115783Abstract: Provided is a method of depositing a cyclic thin film that can provide excellent film properties and step coverage. The method comprises the steps of forming a silicon thin film by repeating a silicon deposition step for depositing silicon on a substrate by injecting a silicon precursor into a chamber into which the substrate is loaded and a first purge step for removing a non-reacted silicon precursor and a reacted byproduct from the chamber; and forming the insulating film including silicon from the silicon thin film by forming a plasma atmosphere into the chamber.Type: ApplicationFiled: August 1, 2011Publication date: May 9, 2013Applicant: EUGENE TECHNOLOGY CO., LTD.Inventors: Hai Won Kim, Sang Ho Woo
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Patent number: 8435906Abstract: Methods and apparatus for forming an oxide layer on a semiconductor substrate are disclosed. In one or more embodiments, plasma oxidation is used to form a conformal oxide layer by controlling the temperature of the semiconductor substrate at below about 100° C. Methods for controlling the temperature of the semiconductor substrate according to one or more embodiments include utilizing an electrostatic chuck and a coolant and gas convection.Type: GrantFiled: January 22, 2010Date of Patent: May 7, 2013Assignee: Applied Materials, Inc.Inventors: Agus S. Tjandra, Christopher S. Olsen, Johanes F. Swenberg, Yoshitaka Yokota
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Publication number: 20130087783Abstract: Embodiments of the disclosure generally provide methods of forming a silicon containing layers in TFT devices. The silicon can be used to form the active channel in a LTPS TFT or be utilized as an element in a gate dielectric layer, a passivation layer or even an etch stop layer. The silicon containing layer is deposited by a vapor deposition process whereby an inert gas, such as argon, is introduced along with the silicon precursor. The inert gas functions to drive out weak, dangling silicon-hydrogen bonds or silicon-silicon bonds so that strong silicon-silicon or silicon-oxygen bonds remain to form a substantially hydrogen free silicon containing layer.Type: ApplicationFiled: September 28, 2012Publication date: April 11, 2013Applicant: Applied Materials, Inc.Inventors: Qunhua Wang, Weijie Wang, Young Jin Choi, Seon-Mee Cho, Yi Cui, Beom Soo Park, Soo Young Choi
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Patent number: 8410581Abstract: There is provided a silicon device structure, comprising: a P-doped n+ type amorphous silicon film formed on a silicon semiconductor, and a wiring formed on the P doped n+ type amorphous silicon film, wherein the wiring is formed of a silicon oxide film which is formed on a surface of the P doped n+ type amorphous silicon film and is also formed of a copper alloy film, and the copper alloy film is a film obtained by forming a copper alloy containing Mn of 1 atom % or more and 5 atom % or less and P of 0.05 atom % or more and 1.0 atom % or less by sputtering.Type: GrantFiled: July 6, 2011Date of Patent: April 2, 2013Assignee: Hitachi Cable LtdInventors: Noriyuki Tatsumi, Tatsuya Tonogi
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Patent number: 8404602Abstract: A plasma oxidation method includes the steps of: generating oxygen-containing plasma with a process gas containing oxygen; applying a bias voltage to a substrate placed on a stage; and radiating positive ions and negative ions in the oxygen-containing plasma onto the substrate so as to perform plasma oxidation of the substrate while controlling a bias potential of the substrate in such a manner that a maximum value Vmax and a minimum value Vmin of the bias potential and a plasma potential Vp satisfy a following relationship: Vmin<Vp<Vmax.Type: GrantFiled: April 12, 2011Date of Patent: March 26, 2013Assignees: FUJIFILM Corporation, Tokai University Educational SystemInventors: Shuji Takahashi, Haruo Shindo
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Patent number: 8389395Abstract: A method for manufacturing includes the steps of forming a BCB resin region on a semiconductor optical device; processing a surface of the BCB resin region with inductively coupled plasma produced with a high-frequency power supply for supplying ICP power and a high-frequency power supply for supplying bias power, thus forming a silicon oxide film on the surface of the BCB resin region and roughening the surface of the BCB resin region with projections and recesses; and forming an electrode pad on the surface of the BCB resin region in direct contact with the silicon oxide film. The surface roughness of the BCB resin region and the thickness of the silicon oxide film on the surface of the BCB resin region are controlled by adjusting the bias power and the ICP power.Type: GrantFiled: September 2, 2011Date of Patent: March 5, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventor: Yukihiro Tsuji
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Patent number: 8377792Abstract: An interdigitated semiconductor capacitor with a large number of plates and a capacitance in the micro-farad range is formed on a wafer with only a single lithography step by depositing each odd layer of metal through a first shadow mask that lies spaced apart from the wafer, and each even layer of metal through a second shadow mask that lies spaced apart from the wafer.Type: GrantFiled: April 7, 2010Date of Patent: February 19, 2013Assignee: National Semiconductor CorporationInventors: Peter J. Hopper, William French, Peter Smeys, Peter Johnson
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Patent number: 8368184Abstract: There is provided a silicon device structure, comprising: a P-doped n+ type amorphous silicon film formed on a silicon semiconductor, and a wiring formed on the P doped n+ type amorphous silicon film, wherein the wiring is formed of a silicon oxide film which is formed on a surface of the P doped n+ type amorphous silicon film and is also formed of a copper alloy film, and the copper alloy film is a film obtained by forming a copper alloy containing Mn of 1 atom % or more and 5 atom % or less and P of 0.05 atom % or more and 1.0 atom % or less by sputtering.Type: GrantFiled: July 6, 2011Date of Patent: February 5, 2013Assignee: Hitachi Cable LtdInventors: Noriyuki Tatsumi, Tatsuya Tonogi
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Patent number: 8367559Abstract: Characteristics of a low-k insulating film grown on a substrate is modulated in the thickness-wise direction, by varying the ratio of high-frequency input and low-frequency input used for inducing plasma in the course of forming the film, to thereby improve the adhesion strength while keeping the dielectric constant at a low level, wherein the high-frequency input and the low-frequency input for inducing plasma are applied from a single electrode, while elevating the level of low-frequency input at least either at the start of formation or at the end of formation of the insulating film, as compared with the input level in residual time zone.Type: GrantFiled: January 25, 2011Date of Patent: February 5, 2013Assignee: Renesas Electronics CorporationInventors: Hironori Yamamoto, Yoshihiro Hayashi
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Publication number: 20130023124Abstract: Methods of patterning low-k dielectric films are described. For example, a method includes forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Exposed portions of the low-k dielectric layer are modified with a plasma process. The modified portions of the low-k dielectric layer are removed selective to the mask layer and unmodified portions of the low-k dielectric layer.Type: ApplicationFiled: July 20, 2011Publication date: January 24, 2013Inventors: Srinivas D. Nemani, Yifeng Zhou, Dmitry Lubomirsky, Ellie Yieh
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Patent number: 8318584Abstract: The formation of a gap-filling silicon oxide layer with reduced volume fraction of voids is described. The deposition involves the formation of an oxygen-rich less-flowable liner layer before an oxygen-poor more-flowable gapfill layer. However, the liner layer is deposited within the same chamber as the gapfill layer. The liner layer and the gapfill layer may both be formed by combining a radical component with an unexcited silicon-containing precursor (i.e. not directly excited by application of plasma power). The liner layer has more oxygen content than the gapfill layer and deposits more conformally. The deposition rate of the gapfill layer may be increased by the presence of the liner layer. The gapfill layer may contain silicon, oxygen and nitrogen and be converted at elevated temperature to contain more oxygen and less nitrogen. The presence of the gapfill liner provides a source of oxygen underneath the gapfill layer to augment the gas phase oxygen introduced during the conversion.Type: GrantFiled: June 3, 2011Date of Patent: November 27, 2012Assignee: Applied Materials, Inc.Inventors: DongQing Li, Jingmei Liang, Nitin K. Ingle
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Patent number: 8314035Abstract: In a method for the manufacture of an active matrix OLED display, at least two thin-film transistors and one storage capacitor are provided to drive each pixel, with a reduced number of photolithographic patterning steps.Type: GrantFiled: February 3, 2010Date of Patent: November 20, 2012Assignee: Universitaet StuttgartInventors: Norbert Fruehauf, Thomas Buergstein, Patrick Schalberger
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Patent number: 8312840Abstract: Disclosed is a substrate processing apparatus and method. The substrate processing apparatus includes a chamber (10) providing an internal space, in which a process is carried out onto a substrate; a gas supply unit (40) supplying a source gas to the internal space; a coil (16) generating an electric field in the internal space to generate plasma from the source gas; and an adjustment ring (50) disposed on a flow path of the plasma toward a support member to adjust the flow of the plasma. The chamber (10) includes a process chamber (12), in which the support member is provided and the process is carried out by the plasma; and a generation chamber (14), in which the plasma is generated by the coil (16), provided on the upper surface of the process chamber (12), and the adjustment ring (50) is installed at the lower end of the generation chamber (14).Type: GrantFiled: March 23, 2009Date of Patent: November 20, 2012Assignee: Eugene Technology Co., Ltd.Inventor: Il-Kwang Yang
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Patent number: 8304033Abstract: Disclosed are methods of operation to grow, modify, deposit, or dope a layer upon a substrate using a multi-nozzle and skimmer assembly for introducing a process gas mixture, or multiple process gases mixtures, in a gas cluster ion beam (GCIB) system. Also disclosed is a method of forming a shallow trench isolation (STI) structure on a substrate, for example, an SiO2 STI structure, using a multiple nozzle system with two separate gas supplies, for example providing a silicon-containing gas and an oxygen-containing gas.Type: GrantFiled: April 23, 2009Date of Patent: November 6, 2012Assignee: TEL Epion Inc.Inventors: Martin D. Tabat, Matthew C. Gwinn, Robert K. Becker, Avrum Freytsis, Michael Graf
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Patent number: 8304353Abstract: Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing precursors comprising ozone and TEOS to a substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material having an outer surface onto the substrate. The outer surface is treated effective to one of add hydroxyl to or remove hydroxyl from the outer surface in comparison to any hydroxyl presence on the outer surface prior to said treating. After the treating, precursors comprising ozone and TEOS are flowed to the substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material onto the treated outer surface of the substrate. Other embodiments are contemplated.Type: GrantFiled: September 28, 2011Date of Patent: November 6, 2012Assignee: Micron Technology, Inc.Inventors: John Smythe, Gurtej S. Sandhu
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Patent number: 8293659Abstract: A method for fabricating a dielectric layer with improved insulating properties is provided, including: providing a dielectric layer having a first resistivity; performing a hydrogen plasma doping process to the dielectric layer; and annealing the dielectric layer, wherein the dielectric layer has a second resistivity greater than that of the first resistivity after annealing thereof.Type: GrantFiled: January 26, 2011Date of Patent: October 23, 2012Assignee: Nanya Technology CorporationInventor: Shu Qin
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Patent number: 8278195Abstract: In a plasma CVD apparatus, unnecessary discharge such as arc discharge is prevented, the amount of particles due to peeling of films attached to a reaction chamber is reduced, and the percentage of a time contributing to production in hours of operation of the apparatus is increased while enlargement of the apparatus and easy workability are maintained. The plasma CVD apparatus is configured such that in a conductive reaction chamber 104 with a power source 113, a vacuum exhausting means 118, and a reaction gas introduction pipe 114, plasma 115 is generated in a space surrounded by an electrode 111, a substrate holder 112, and an insulator 120.Type: GrantFiled: November 2, 2011Date of Patent: October 2, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Takayama, Mitsunori Sakama, Hisashi Abe, Hiroshi Uehara, Mika Ishiwata
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Patent number: 8272348Abstract: In a film-forming process with a capacitively-coupled plasma (CCP) chemical vapor deposition (CVD) device, pulse control is performed on a low-frequency radio-frequency power source. During the pulse control, an ON time and an OFF time form one period. Furthermore, in the pulse control, a time interval between a time period from the moment that the electric power supply is stopped till the electron density decreases to a residual plasma threshold capable of causing an arc discharge and a time period from the moment that the electric power supply is stopped till the density of high-temperature electrons decreases to a specific plasma state serves as the OFF time; a saturation time during the rising process of the density of the high-temperature electrons in the plasma after the electric power supply is started serves as an upper limit of the ON time; and electric power is intermittently supplied under the above conditions.Type: GrantFiled: February 26, 2008Date of Patent: September 25, 2012Assignee: Shimadzu CorporationInventor: Masayasu Suzuki
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Patent number: 8268411Abstract: A method of forming a porous composite material in which substantially all of the pores within the composite material are small having a diameter of about 5 nm or less and with a narrow PSD is provided. The porous composite material includes a first solid phase having a first characteristic dimension and a second phase comprised of pores having a second characteristic dimension, wherein the characteristic dimensions of at least one of said phases is controlled to a value of about 5 nm or less.Type: GrantFiled: August 8, 2009Date of Patent: September 18, 2012Assignee: International Business Machines CorporationInventors: Stephen M. Gates, Alfred Grill, Deborah A. Neumayer, Son Nguyen, Vishnubhai V. Patel
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Patent number: 8263502Abstract: A substrate structure is produced by forming a first material layer on a substrate having a recess, removing the first material layer from the portion of the substrate except for the recess using a second material that reacts with the first material, and forming a deposition film from the first material layer using a third material that reacts with the first material. A method of manufacturing a device may include the method of forming a substrate structure.Type: GrantFiled: August 11, 2009Date of Patent: September 11, 2012Assignee: Synos Technology, Inc.Inventor: Sang In Lee
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Patent number: 8242031Abstract: A method of depositing a silicon and nitrogen containing film on a substrate. The method includes introducing silicon-containing precursor to a deposition chamber that contains the substrate, wherein the silicon-containing precursor comprises at least two silicon atoms. The method further includes generating at least one radical nitrogen precursor with a remote plasma system located outside the deposition chamber. Moreover, the method includes introducing the radical nitrogen precursor to the deposition chamber, wherein the radical nitrogen and silicon-containing precursors react and deposit the silicon and nitrogen containing film on the substrate. Furthermore, the method includes annealing the silicon and nitrogen containing film in a steam environment to form a silicon oxide film, wherein the steam environment includes water and acidic vapor.Type: GrantFiled: September 27, 2010Date of Patent: August 14, 2012Assignee: Applied Materials, Inc.Inventors: Abhijit Basu Mallick, Srinivas D. Nemani, Ellie Yieh
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Publication number: 20120196450Abstract: Stress of a silicon nitride layer may be enhanced by deposition at higher temperatures. Employing an apparatus that allows heating of a substrate to substantially greater than 400° C. (for example a heater made from ceramic rather than aluminum), the silicon nitride film as-deposited may exhibit enhanced stress allowing for improved performance of the underlying MOS transistor device. In accordance with some embodiments, a deposited silicon nitride film is exposed to curing with plasma and ultraviolet (UV) radiation, thereby helping remove hydrogen from the film and increasing film stress. In accordance with other embodiments, a silicon nitride film is formed utilizing an integrated process employing a number of deposition/curing cycles to preserve integrity of the film at the sharp corner of the underlying raised feature. Adhesion between successive layers may be promoted by inclusion of a post-UV cure plasma treatment in each cycle.Type: ApplicationFiled: February 2, 2012Publication date: August 2, 2012Applicant: Applied Materials, Inc.Inventors: Mihaela Balseanu, Victor Nguyen, Li-Qun Xia, Derek R. Witty, Hichem M'Saad, Mei-Yee Shek, Isabelita Roflox
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Patent number: 8217479Abstract: An embodiment of the invention provides a solid-state image pickup element, including: a semiconductor layer having a photodiode, photoelectric conversion being carried out in the photodiode; a silicon oxide film formed on the semiconductor layer in a region having at least the photodiode by using plasma; and a film formed on the silicon oxide film and having negative fixed charges.Type: GrantFiled: January 21, 2010Date of Patent: July 10, 2012Assignee: Sony CorporationInventors: Itaru Oshiyama, Susumu Hiyama
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Patent number: 8207067Abstract: A surface component film (2) is etched using a resist (3) as a mask, and the surface component film (2) is patterned according to the shape of an aperture (3a). This results in a step portion (4) having the same shape as the aperture (3a), with the sidewall (4a) of the step portion (4) exposed through the aperture (3a). The aperture (3a) is spin-coated with a shrink agent, reacted at a first temperature, and developed to shrink the aperture (3a). To control the shrinkage with high accuracy, in the first round of reaction, the aperture is shrunk by, for example, about half of the desired shrinkage. The aperture (3a) is further spin-coated with a shrink agent, reacted at a second temperature, and developed to shrink the aperture (3a). In this embodiment, the second-round shrink process will result in the desired aperture length. The second temperature is adjusted based on the shrinkage in the first round.Type: GrantFiled: March 26, 2010Date of Patent: June 26, 2012Assignee: Fujitsu LimitedInventors: Kozo Makiyama, Ken Sawada
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Patent number: 8202809Abstract: A semiconductor device manufacturing method includes: forming a layer on a heated substrate by supplying source gas into a process vessel; changing the layer into an oxide layer by supplying gases containing oxygen and hydrogen to the heated substrate in the process vessel under a pressure lower than atmospheric pressure; and forming an oxide film on the heated substrate by alternately repeating the forming of the layer and the changing of the layer while purging an inside of the process vessel therebetween. In the forming of the layer, the source gas is supplied toward the substrate through a nozzle at a side of the substrate, and inert or hydrogen-containing gas is supplied together with the source gas through the nozzle toward the substrate, such that the velocity of the source gas flowing parallel to the substrate is greater than the velocity of the inert gas flowing parallel to the substrate in the purging of the process vessel.Type: GrantFiled: November 19, 2010Date of Patent: June 19, 2012Assignee: Hitachi Kokusai Electric Inc.Inventors: Yosuke Ota, Naonori Akae, Yushin Takasawa, Yoshiro Hirose
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Publication number: 20120135562Abstract: A method of forming a hydrophobic silicon dioxide layer is provided. A substrate is provided. Thereafter, a hydrophobic silicon dioxide layer is formed on the substrate by using a plasma chemical vapour deposition (CVD) system, in which tetraethyl orthosilicate (TEOS) and an oxygen-containing gas are introduced at a reactive temperature between 25° C. and 150° C. A method of forming an organic thin film transistor (OTFT) including the hydrophobic silicon dioxide layer as a gate insulating layer is also provided. In the present invention, the hydrophobic silicon dioxide layer can be directly formed at low temperature without using the conventional surface modification treatment. Accordingly, the process is simplified and the cost is reduced.Type: ApplicationFiled: January 14, 2011Publication date: May 31, 2012Applicant: National Taiwan University of Science and TechnologyInventors: Ching-Lin Fan, Ping-Cheng Chiu, Chang-Chih Lin