Using Electromagnetic Or Wave Energy (e.g., Photo-induced Deposition, Plasma, Etc.) Patents (Class 438/788)
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Publication number: 20120126376Abstract: To produce a silicon dioxide film having concentration of hydrogen atoms below or equal to 9.9×1020 atoms/cm3 in the silicon dioxide film, as measured by using secondary ion mass spectrometry (SIMS), a plasma CVD, which generate plasma by introducing microwaves into a process chamber by using a planar antenna having a plurality of apertures and forms a film, is performed by setting the pressure inside the process chamber within a range from 0.1 Pa to 6.7 Pa and by using a gas of a compound composed of silicon atoms and chlorine atoms and an oxygen containing gas.Type: ApplicationFiled: September 29, 2009Publication date: May 24, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Minoru Honda, Toshio Nakanishi, Masayuki Kohno, Junya Miyahara
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Patent number: 8183136Abstract: Provided are a method of forming an insulating layer and a method of manufacturing a transistor using the method. The method of forming the insulating layer includes forming a preliminary insulating layer including silicon oxide (SiO2) on a silicon (Si)-containing substrate. A reactive gas containing ammonia (NH3) gas is supplied to the preliminary insulating layer. Nitrogen radicals (N*) and hydrogen radicals (H*) are generated from the ammonia gas using plasma. The hydrogen radicals combine with oxygen of the preliminary insulating layer, and the nitrogen radicals combine with the silicon oxide so that an insulating layer including hydroxides (OH) and silicon oxynitride (SiON) can be formed.Type: GrantFiled: November 19, 2010Date of Patent: May 22, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Hoon Jeong, Dong-Chan Kim, Yu-Gyun Shin, Soo-Jin Hong, Deok-Hyung Lee
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Patent number: 8177992Abstract: In one embodiment, a method of removing film materials on an edge area of a substrate in a plasma etching apparatus is disclosed. The apparatus includes a chamber, a substrate support, a shield disposed with a gap on the substrate such that plasma is not generated therein while allowing an edge portion of the substrate to be exposed, and an antenna disposed on an outer wall of the chamber to apply plasma-generating power to an area between the edge portion of the substrate and an inner wall of the chamber. The method includes spraying a curtain gas to a space between the shield and the substrate, using a curtain gas passageway; and spraying a reaction gas to an area between a side surface of the shield and an inner sidewall of the chamber formed within the shield, using a reaction gas supply passageway.Type: GrantFiled: December 13, 2010Date of Patent: May 15, 2012Assignee: Jusung Engineering Co., Ltd.Inventor: Bu-Il Jeon
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Publication number: 20120108079Abstract: Atomic layer deposition methods of forming one or more of a mixed silicon oxide/silicon nitride film or a mixed silicon oxide/silicon film are described in which the substrate is exposed sequentially to a first reactant gas comprising a silicon species and a second reactant gas comprising an oxygen species to form at least a partial layer of silicon oxide on the substrate during a first atomic layer deposition process. The substrate is then exposed sequentially to a third reactant gas comprising a silicon species and a fourth reactant gas comprising a species sufficient to form at least a partial layer of one or more of silicon nitride or silicon on the substrate during a second atomic layer deposition process. The process can be repeated multiple times to deposit one or more of a mixed silicon oxide/silicon nitride film and a mixed silicon oxide/silicon film.Type: ApplicationFiled: July 28, 2011Publication date: May 3, 2012Applicant: Applied Materials, Inc.Inventor: Maitreyee Mahajani
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Patent number: 8168548Abstract: A method of forming a semiconductor device includes providing a substrate in a vacuum processing tool, the substrate having a strained Ge-containing layer on the substrate and a Si-containing layer on the strained Ge-containing layer, maintaining the substrate at a temperature less than 700° C., and exposing the Si-containing layer to oxidation radicals in an UV-assisted oxidation process to form a Si-containing dielectric layer while minimizing oxidation and strain relaxation in the underlying strained Ge-containing layer. A semiconductor device containing a substrate, a strained Ge-containing layer on the substrate, and a Si-containing dielectric layer formed on the strained Ge-containing layer is provided. The semiconductor device can further contain a gate electrode layer on the Si-containing dielectric layer or a high-k layer on the Si-containing dielectric layer and a gate electrode layer on the high-k layer.Type: GrantFiled: September 29, 2006Date of Patent: May 1, 2012Assignee: Tokyo Electron LimitedInventor: Gert Leusink
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Patent number: 8169577Abstract: A thin-film transistor photosensor and a liquid crystal display (LCD) panel respectively utilize a dielectric layer having F—SiOC: H compound and a bump structure having F—SiOC: H compound so as to form a thin-film transistor photosensor having lower resistor-capacitor loading (RC loading) and an LCD panel having low-dielectric F—SiOC: H compound respectively. In addition, a method of forming a dielectric layer having F—SiOC: H compound utilizes gases including trimethyl silane, carbon tetrafluoride, argon, and oxygen for thin-film deposition process so as to form a low-k F—SiOC: H compound dielectric layer.Type: GrantFiled: October 18, 2009Date of Patent: May 1, 2012Assignee: Chunghwa Picture Tubes, Ltd.Inventor: Cho-Yu Li
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Patent number: 8163660Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias.Type: GrantFiled: March 27, 2009Date of Patent: April 24, 2012Assignee: Cypress Semiconductor CorporationInventors: Helmut Puchner, Igor Polishchuk, Sagy Levy
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Patent number: 8158266Abstract: Provided is a technology capable of improving the reliability of a semiconductor device using a SiOC film as an interlayer film. In the invention, by forming an interlayer film from a SiOC film having a Si—CH3 bond/Si—O bond ratio less than 2.50% or having a strength ratio determined by the FT-IR of a Si—OH bond to a SiO—O bond exceeding 0.0007, a strength ratio of a SiH bond to a SiO—O bond at a wavelength of 2230 cm?1 exceeding 0.0050 and a strength ratio of a Si—H bond to a SiO—O bond at a wavelength of 2170 cm?1 exceeding 0.0067, the interlayer film has a relative dielectric constant of to 3 or less, and owing to suppression of lowering in hardness or elastic modulus, has improved mechanical strength.Type: GrantFiled: May 17, 2010Date of Patent: April 17, 2012Assignee: Renesas Electronics CorporationInventors: Masami Takayasu, Katsuhiko Hotta
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Patent number: 8153537Abstract: There is provided a method for fabricating a semiconductor device comprising the formation of a first device in the first device region, the first device comprising first diffusion regions. A stressor layer covering the substrate in the first device region and the first device is subsequently formed, the stressor layer having a first stress value. A laser anneal to memorize at least a portion of the first stress value in the first device is carried out followed by an activation anneal after the laser anneal to activate dopants in the first diffusion regions.Type: GrantFiled: September 19, 2011Date of Patent: April 10, 2012Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Sai Hooi Yeong, Tao Wang, Shesh Mani Pandey, Chia Ching Yeo, Ying Keung Leung, Elgin Kiok Boone Quek
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Patent number: 8148274Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.Type: GrantFiled: January 24, 2008Date of Patent: April 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Wada, Atsuko Sakata, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
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Publication number: 20120071006Abstract: Disclosed is a starting material for use in forming a silicon oxide film on a substrate by the CVD method, comprising a siloxane compound having a carbonyl group, wherein the starting material is decomposed by applying energy, thereby releasing CO and producing a product having no dangling bond in the chemical structure, and the product contributes to the formation of the film. As a result, a silicon oxide film having a favorable step coverage is formed.Type: ApplicationFiled: May 27, 2010Publication date: March 22, 2012Inventor: Song Yun Kang
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Patent number: 8133822Abstract: A method is provided for forming a silicon (Si) nanocrystal embedded Si oxide electroluminescence (EL) device with a mid-bandgap transition layer. The method provides a highly doped Si bottom electrode, and forms a mid-bandgap electrically insulating dielectric film overlying the electrode. A Si nanocrystal embedded SiOx film layer is formed overlying the mid-bandgap electrically insulating dielectric film, where X is less than 2, and a transparent top electrode overlies the Si nanocrystal embedded SiOx film layer. The bandgap of the mid-bandgap dielectric film is about half that of the bandgap of the Si nanocrystal embedded SiOx film. In one aspect, the Si nanocrystal embedded SiOx film has a bandgap (Eg) of about 10 electronvolts (eV) and mid-bandgap electrically insulating dielectric film has a bandgap of about 5 eV. By dividing the high-energy tunneling processes into two lower energy tunneling steps, potential damage due to high power hot electrons is reduced.Type: GrantFiled: August 22, 2008Date of Patent: March 13, 2012Assignee: Sharp Laboratories of America, Inc.Inventors: Jiandong Huang, Pooran Chandra Joshi, Hao Zhang, Apostolos T. Voutsas
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Patent number: 8124484Abstract: To manufacture a MOS memory device having a dielectric film laminate in which adjacent dielectric films have band-gaps of different magnitudes, a plasma processing device which transmits microwaves to a chamber by means of a planar antenna having a plurality of holes is used to perform plasma CVD under pressure conditions that differ from at least pressure conditions used when forming the adjacent dielectric films, and the dielectric films are sequentially formed by altering the band-gaps of the adjacent dielectric films that constitute the dielectric film laminate.Type: GrantFiled: March 30, 2009Date of Patent: February 28, 2012Assignees: Tohoku University, Tokyo Electron LimitedInventors: Tetsuo Endoh, Masayuki Kohno, Syuichiro Otao, Minoru Honda, Toshio Nakanishi
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Publication number: 20120045904Abstract: Embodiments of the disclosure generally provide methods of forming a hydrogen free silicon containing layer in TFT devices. The hydrogen free silicon containing layer may be used as a passivation layer, a gate dielectric layer, an etch stop layer, or other suitable layers in TFT devices, photodiodes, semiconductor diode, light-emitting diode (LED), or organic light-emitting diode (OLED), or other suitable display applications. In one embodiment, a method for forming a hydrogen free silicon containing layer in a thin film transistor includes supplying a gas mixture comprising a hydrogen free silicon containing gas and a reacting gas into a plasma enhanced chemical vapor deposition chamber, wherein the hydrogen free silicon containing gas is selected from a group consisting of SiF4, SiCl4, Si2Cl6, and forming a hydrogen free silicon containing layer on the substrate in the presence of the gas mixture.Type: ApplicationFiled: August 20, 2011Publication date: February 23, 2012Applicant: APPLIED MATERIALS, INC.Inventor: Soo Young Choi
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Patent number: 8119541Abstract: Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.Type: GrantFiled: July 28, 2009Date of Patent: February 21, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Lee Wee Teo, Elgin Quek
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Patent number: 8105958Abstract: A selective oxidation process is performed on a gate electrode in a plasma processing apparatus 100. A wafer W with the gate electrode formed thereon is placed on a susceptor 2 within a chamber 1. Ar gas, H2 gas, and O2 gas are supplied from an Ar gas supply source 17, an H2 gas supply source 18, and an O2 gas supply source 19 in a gas supply system 16 through a gas feed member 15 into the chamber 1. At this time, a flow rate ratio H2/O2 of H2 gas relative to O2 gas is set to be 1.5 or more and 20 or less, preferably to be 4 or more, and more preferably to be 8 or more. Further, the pressure inside the chamber is set to be 3 to 700 Pa, such as 6.7 Pa (50 mTorr).Type: GrantFiled: August 11, 2005Date of Patent: January 31, 2012Assignee: Tokyo Electron LimitedInventors: Yoshiro Kabe, Masaru Sasaki
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Publication number: 20120021613Abstract: The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.Type: ApplicationFiled: March 17, 2010Publication date: January 26, 2012Inventors: Walter Schwarzenbach, Sébastien Kerdiles, Patrick Reynaud, Ludovic Ecarnot, Eric Neyret
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Patent number: 8101531Abstract: Methods and hardware for depositing thin conformal films using plasma-activated conformal film deposition (CFD) processes are described herein. In one example, a method for forming a thin conformal film comprises, in a first phase, generating precursor radicals off of a surface of the substrate and adsorbing the precursor radicals to the surface to form surface active species; in a first purge phase, purging residual precursor from the process station; in a second phase, supplying a reactive plasma to the surface, the reactive plasma configured to react with the surface active species and generate the thin conformal film; and in a second purge phase, purging residual reactant from the process station.Type: GrantFiled: September 23, 2010Date of Patent: January 24, 2012Assignee: Novellus Systems, Inc.Inventors: Ming Li, Hu Kang, Mandyam Sriram, Adrien LaVoie
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Patent number: 8093142Abstract: There is provided a plasma processing device capable of forming a film in a favorable manner irrespective of deflection generated in an anode electrode and a cathode electrode in the case where an area of the electrodes is increased. A plasma processing device 100 includes a chamber 15, a gas introducing portion 28, an exhaust unit 29, and a high-frequency power supply unit 30. In the chamber 15, there are provided an anode electrode (first electrode) 4 having a flat-plate shape, a cathode electrode (second electrode) 12 having a flat-plate shape, and first supporting members 6 and second supporting members 5 for slidably supporting the two electrodes 4 and 12 in parallel with each other. The cathode electrode 12 is provided so as to face the anode electrode 4. The anode electrode 4 and the cathode electrode 12 are not fixed with screws or the like but are merely placed on the first supporting members 6 and the second supporting members 5.Type: GrantFiled: November 16, 2006Date of Patent: January 10, 2012Assignee: Sharp Kabushiki KaishaInventors: Yusuke Fukuoka, Katsushi Kishimoto
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Publication number: 20120003842Abstract: There is provided a silicon oxide film forming method including forming a silicon oxide film on a processing target substrate W by supplying a silicon compound gas, an oxidizing gas and a rare gas into a processing chamber 32 while maintaining a surface temperature of a holding table 34 capable of holding thereon the processing target substrate W at a temperature equal to or lower than about 300° C. and by generating microwave plasma within the processing chamber 32, and performing a plasma process on the silicon oxide film formed on the processing target substrate W by supplying an oxidizing gas and a rare gas into the processing chamber 32 and by generating microwave plasma within the processing chamber 32.Type: ApplicationFiled: December 10, 2009Publication date: January 5, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Hirokazu Ueda, Yusuke Ohsawa, Yoshinobu Tanaka
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Publication number: 20110281442Abstract: Methods and apparatus for forming nitrogen-containing layers are provided herein. In some embodiments, a method of forming a nitrogen-containing layer may include placing a substrate having a first layer disposed thereon on a substrate support of a process chamber; heating the substrate to a temperature of at least about 250 degrees Celsius; and exposing the first layer to a radio frequency (RF) plasma formed from a process gas consisting essentially of ammonia (NH3) and an inert gas while maintaining the process chamber at a pressure of about 10 mTorr to about 40 mTorr to transform at least an upper portion of the first layer into a nitrogen-containing layer.Type: ApplicationFiled: July 27, 2011Publication date: November 17, 2011Inventors: Malcolm J. Bevan, Johanes Swenberg, Son T. Nguyen, Wei Liu, Jose Antonio Marin, Jian Li
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Patent number: 8053338Abstract: In a plasma CVD apparatus, unnecessary discharge such as arc discharge is prevented, the amount of particles due to peeling of films attached to a reaction chamber is reduced, and the percentage of a time contributing to production in hours of operation of the apparatus is increased while enlargement of the apparatus and easy workability are maintained. The plasma CVD apparatus is configured such that in a conductive reaction chamber 104 with a power source 113, a vacuum exhausting means 118, and a reaction gas introduction pipe 114, plasma 115 is generated in a space surrounded by an electrode 111, a substrate holder 112, and an insulator 120.Type: GrantFiled: April 2, 2009Date of Patent: November 8, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Takayama, Mitsunori Sakama, Hisashi Abe, Hiroshi Uehara, Mika Ishiwata
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Patent number: 8043981Abstract: Methods and apparatus for forming an oxide layer on a semiconductor substrate are disclosed. A two frequency plasma source is used to form a plasma in a plasma reactor. In various embodiments, different quantities of power are supplied to a power source operating at the first frequency and a power source operating at the second frequency over time.Type: GrantFiled: April 19, 2010Date of Patent: October 25, 2011Assignee: Applied Materials, Inc.Inventors: Kai Ma, Yoshitaka Yokota, Christopher S. Olsen
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Patent number: 8043975Abstract: Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing precursors comprising ozone and TEOS to a substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material having an outer surface onto the substrate. The outer surface is treated effective to one of add hydroxyl to or remove hydroxyl from the outer surface in comparison to any hydroxyl presence on the outer surface prior to said treating. After the treating, precursors comprising ozone and TEOS are flowed to the substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material onto the treated outer surface of the substrate. Other embodiments are contemplated.Type: GrantFiled: July 1, 2010Date of Patent: October 25, 2011Assignee: Micron Technology, Inc.Inventors: John Smythe, Gurtej S. Sandhu
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Patent number: 8039333Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a SiGe crystal layer on a semiconductor substrate, the SiGe crystal layer having a first plane and a second plane inclined with respect to the first plane; forming an amorphous Si film on the SiGe crystal layer; crystallizing a portion located adjacent to the first and second planes of the amorphous Si film by applying heat treatment using the first and second planes of the SiGe crystal layer as a seed, thereby forming a Si crystal layer; selectively removing or thinning a portion of the amorphous Si film that is not crystallized by the heat treatment; applying oxidation treatment to a surface of the Si crystal layer, thereby forming a gate insulating film on the surface of the Si crystal layer; and forming a gate electrode on the gate insulating film.Type: GrantFiled: January 26, 2009Date of Patent: October 18, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Akio Kaneko, Seiji Inumiya, Tomonori Aoyama, Takuya Kobayashi
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Patent number: 8030206Abstract: A solar cell fabrication process is described that includes etching a cap layer into a front surface of a semiconductor structure, depositing an anti-reflective coating onto the front surface of the semiconductor structure, forming a front electrical contact on the front surface of the semiconductor structure, forming a first back metal contact on a back surface of the semiconductor structure, utilizing a plasma enhanced chemical vapor deposition (PECVD) process to apply a dielectric layer to the first back metal contact, the PECVD process performed at within a temperature environment and for a duration that allows for the annealing of metal associated with the front electrical contact and the first back metal contact, and attaching at least one secondary electrical contact to the dielectric layer.Type: GrantFiled: August 27, 2008Date of Patent: October 4, 2011Assignee: The Boeing CompanyInventors: Xiaobo Zhang, Julie Hoskin
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Patent number: 8030220Abstract: A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of the semiconductor substrate with plasma to neutralize a hydrophobicity associated with the exposed surface, wherein the exposed surface is treated using plasma with a power in a range of 100 watts to 500 watts and for duration in a range of 1 to 60 seconds. The method may further include forming a metal-containing layer on a top surface of the plasma treated surface using an atomic layer deposition process.Type: GrantFiled: October 14, 2009Date of Patent: October 4, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Dina H. Triyoso, Olubunmi O. Adetutu
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Publication number: 20110230061Abstract: A manufacturing method of a semiconductor device includes the steps of carrying a substrate in a processing chamber, bringing the processing chamber into a state at a first pressure by supplying a silicon compound gas which contains carbon and hydrogen into the processing chamber, forming a silicon oxide film on the substrate by irradiating a UV light to the silicon compound gas supplied into the processing chamber in the state kept at the first pressure, and decompression process to bring the processing chamber into a state at a second pressure lower than the first pressure. This makes it possible to form the dense silicon oxide film in the trench with high aspect ratio and small width.Type: ApplicationFiled: June 1, 2011Publication date: September 22, 2011Applicant: Hitachi Koskusai Electric Inc.Inventors: Naofumi Ohashi, Yuichi Wada, Nobuo Owada, Takeshi Taniguchi
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Patent number: 8021992Abstract: A high density plasma chemical vapor deposition process including exciting gas mixture to create a plasma including ions, and directing the plasma into a dense region above the upper surface of the semiconductor wafer, heating the wafer using an additional heat source, and allowing a material from the plasma to deposit onto the semiconductor wafer.Type: GrantFiled: September 1, 2005Date of Patent: September 20, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Joung-Wei Liou, Tsang-Yu Liu, Chien-Feng Lin, Cheng-Liang Chang, Ming-Te Chen, Chia-Hui Lin, Ying-Hsiu Tsai, Szu-An Wu, Yin-Ping Lee
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Patent number: 8003551Abstract: The present invention provides means and methods for producing surface-activated semiconductor nanoparticles suitable for in vitro and in vivo applications that can fluoresce in response to light excitation. Semiconductor nanostructures can be produced by generating a porous layer in semiconductor substrate comprising a network of nanostructures. Prior or subsequent to cleavage from the substrate, the nanostructures can be activated by an activation means such as exposing their surfaces to a plasma, oxidation or ion implantation. In some embodiments, the surface activation renders the nanostructures more hydrophilic, thereby facilitating functionalization of the nanoparticles for either in vitro or in vivo use.Type: GrantFiled: April 27, 2009Date of Patent: August 23, 2011Assignee: Spire CorporationInventors: Nader Montazernezam Kalkhoran, James G. Moe, Kurt J. Linden, Marisa Sambito
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Patent number: 7998884Abstract: A light emitting device using a silicon (Si) nanocrystalline Si insulating film is presented with an associated fabrication method. The method provides a doped semiconductor or metal bottom electrode. Using a high density plasma-enhanced chemical vapor deposition (HDPECVD) process, a Si insulator film is deposited overlying the semiconductor electrode, having a thickness in a range of 30 to 200 nanometers (nm). For example, the film may be SiOx, where X is less than 2, Si3Nx, where X is less than 4, or SiCx, where X is less than 1. The Si insulating film is annealed, and as a result, Si nanocrystals are formed in the film. Then, a transparent metal electrode is formed overlying the Si insulator film. An annealed Si nanocrystalline SiOx film has a turn-on voltage of less than 20 volts, as defined with respect to a surface emission power of greater than 0.03 watt per square meter.Type: GrantFiled: May 23, 2008Date of Patent: August 16, 2011Assignee: Sharp Laboratories of America, Inc.Inventors: Jiandong Huang, Pooran Chandra Joshi, Apostolos T. Voutsas, Hao Zhang
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Patent number: 7994070Abstract: A method for depositing a dielectric film on a substrate includes positioning a plurality of substrates in a process chamber, heating the process chamber to a deposition temperature between 400° C. and less than 650° C., flowing a first process gas comprising water vapor into the process chamber, flowing a second process gas comprising dichlorosilane (DCS) into the process chamber, establishing a gas pressure of less than 2 Torr, and reacting the first and second process gases to thermally deposit a silicon oxide film on the plurality of substrates. One embodiment further includes flowing a third process gas comprising nitric oxide (NO) gas into the process chamber while flowing the first process gas and the second process gas; and reacting the oxide film with the third process gas to form a silicon oxynitride film on the substrate.Type: GrantFiled: September 30, 2010Date of Patent: August 9, 2011Assignee: Tokyo Electron LimitedInventors: Anthony Dip, Kimberly G Reid
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Patent number: 7989365Abstract: Methods of seasoning a remote plasma system are described. The methods include the steps of flowing a silicon-containing precursor into a remote plasma region to deposit a silicon containing film on an interior surface of the remote plasma system. The methods reduce reactions with the seasoned walls during deposition processes, resulting in improved deposition rate, improved deposition uniformity and reduced defectivity during subsequent deposition.Type: GrantFiled: August 18, 2009Date of Patent: August 2, 2011Assignee: Applied Materials, Inc.Inventors: Soonam Park, Soo Jeon, Toan Q. Tran, Jang-Gyoo Yang, Qiwei Liang, Dmitry Lubomirsky
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Patent number: 7989363Abstract: A method for fabricating semiconductor devices, e.g., SONOS cell. The method includes providing a semiconductor substrate (e.g., silicon wafer, silicon on insulator) having a surface region, which has a native oxide layer. The method includes treating the surface region to a wet cleaning process to remove a native oxide layer from the surface region. In a specific embodiment, the method includes subjecting the surface region to an oxygen bearing environment and subjecting the surface region to a high energy electromagnetic radiation having wavelengths ranging from about 300 to about 800 nanometers for a time period of less than 10 milli-seconds to increase a temperature of the surface region to greater than 1000 Degrees Celsius. In a specific embodiment, the method causes formation of an oxide layer having a thickness of less than 10 Angstroms. In a preferred embodiment, the oxide layer is substantially free from pinholes and other imperfections.Type: GrantFiled: October 27, 2008Date of Patent: August 2, 2011Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: David Gao, Mieno Fumitake
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Patent number: 7989364Abstract: A plasma oxidation process is performed to form a silicon oxide film on the surface of a target object by use of plasma with an O(1D2) radical density of 1×1012 [cm?3] or more generated from a process gas containing oxygen inside a process chamber of a plasma processing apparatus. During the plasma oxidation process, the O(1D2) radical density in the plasma is measured by a VUV monochromator 63, and a correction is made to the plasma process conditions.Type: GrantFiled: August 27, 2007Date of Patent: August 2, 2011Assignees: National University Corporation Nagoya University, Tokyo Electron LimitedInventors: Masaru Hori, Toshihiko Shiozawa, Yoshiro Kabe, Junichi Kitagawa
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Patent number: 7985700Abstract: A method for fabricating a semiconductor device utilizing the step of forming a first insulating film of a porous material over a substrate; the step of forming on the first insulating film a second insulating film containing a silicon compound containing Si—CH3 bonds by 30-90%, and the step of irradiating UV radiation with the second insulating film formed on the first insulating film to cure the first insulating film. Thus, UV radiation having the wavelength which eliminates CH3 groups is sufficiently absorbed by the second insulating film, whereby the first insulating film is highly strengthened with priority by the UV cure, and the first insulating film can have the film density increased without having the dielectric constant increased.Type: GrantFiled: December 8, 2008Date of Patent: July 26, 2011Assignee: Fujitsu LimitedInventors: Shirou Ozaki, Yoshihiro Nakata, Ei Yano
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Patent number: 7985188Abstract: Methods for processing a vessel, for example to provide a gas barrier or lubricity, are disclosed. First and second PECVD or other vessel processing stations or devices and a vessel holder comprising a vessel port are provided. An opening of the vessel can be seated on the vessel port. The interior surface of the seated vessel can be processed via the vessel port by the first and second processing stations or devices. Vessel barrier, lubricity and hydrophobic coatings and coated vessels, for example syringes and medical sample collection tubes are disclosed. A vessel processing system and vessel inspection apparatus and methods are also disclosed.Type: GrantFiled: May 12, 2010Date of Patent: July 26, 2011Assignee: CV Holdings LLCInventors: John T. Felts, Thomas E. Fisk, Robert S. Abrams, John Ferguson, Johathan R. Freedman, Robert J. Pangborn, Peter J. Sagona
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Patent number: 7981815Abstract: Disclosed is a producing method or a semiconductor device including: loading at least one substrate into a processing chamber; forming a metal oxide film or a silicon oxide film on a surface of the substrate by repeatedly supplying a metal compound or a silicon compound, each of which is a first material, an oxide material which is a second material including an oxygen atom, and a hydride material which is a third material, into the processing chamber predetermined times; and unloading the substrate from the processing chamber.Type: GrantFiled: July 19, 2007Date of Patent: July 19, 2011Assignees: Hitachi Kokusai Electric Inc., Shin-Etsu Chemical Co., Ltd.Inventors: Hironobu Miya, Kazuhiro Hirahara, Yoshitaka Hamada, Atsuhiko Suda
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Patent number: 7981814Abstract: A method for the duplication of microscopic patterns from a master to a substrate is disclosed, in which a replica of a topographic structure on a master is formed and transferred when needed onto a receiving substrate using one of a variety of printing or imprint techniques, and then dissolved. Additional processing steps can also be carried out using the replica before transfer, including the formation of nanostructures, microdevices, or portions thereof. These structures are then also transferred onto the substrate when the replica is transferred, and remain on the substrate when the replica is dissolved. This is a technique that can be applied as a complementary process or a replacement for various lithographic processing steps in the fabrication of integrated circuits and other microdevices.Type: GrantFiled: August 31, 2007Date of Patent: July 19, 2011Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventor: Charles Daniel Schaper
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Patent number: 7972968Abstract: A high density plasma dep/etch/dep method of depositing a dielectric film into a gap between adjacent raised structures on a substrate disposed in a substrate processing chamber. The method deposits a first portion of the dielectric film within the gap by forming a high density plasma from a first gaseous mixture flown into the process chamber, etches the deposited first portion of the dielectric film by flowing an etchant gas comprising CxFy, where a ratio of x to y is greater than or equal to 1:2 and then deposits a second portion of the dielectric film over the first portion by forming a high density plasma from a second gaseous mixture flown into the process chamber.Type: GrantFiled: August 18, 2008Date of Patent: July 5, 2011Assignee: Applied Materials, Inc.Inventors: Young S. Lee, Ying Rui, Dmitry Lubomirsky, Daniel J. Hoffman, Jang Gyoo Yang, Anchuan Wang
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Patent number: 7972946Abstract: Provided are a plasma treatment method and a plasma treatment device capable of forming a silicon nitride film having high compressive stress. In the plasma treatment method for depositing the silicon nitride film on a process target substrate by use of plasma of raw material gas containing silicon and hydrogen and of nitrogen gas, ion energy for disconnecting nitrogen-hydrogen bonding representing a state of bonding between the hydrogen in the raw material gas and the nitrogen gas is applied to the process target substrate so as to reduce an amount of nitrogen-hydrogen bonding contained in the silicon nitride film.Type: GrantFiled: July 24, 2007Date of Patent: July 5, 2011Assignee: Mitsubishi Heavy Industries, Ltd.Inventors: Tadashi Shimazu, Masahiko Inoue, Toshihiko Nishimori, Yuichi Kawano
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Patent number: 7972885Abstract: This invention relates to imaging device and its related transferring technologies to independent substrate able to attain significant broadband capability covering the wavelengths from ultra-violet (UV) to long-Infrared. More particularly, this invention is related to the broadband image sensor (along with its manufacturing technologies), which can detect the light wavelengths ranges from as low as UV to the wavelengths as high as 20 ?m covering the most of the wavelengths using of the single monolithic image sensor on the single wafer. This invention is also related to the integrated circuit and the bonding technologies of the image sensor to standard integrated circuit for multicolor imaging, sensing, and advanced communication. Our innovative approach utilizes surface structure having more than micro-nano-scaled 3-dimensional (3-D) blocks which can provide broad spectral response.Type: GrantFiled: September 24, 2009Date of Patent: July 5, 2011Assignee: Banpil Photonics, Inc.Inventors: Achyut Kumar Dutta, Robert Allen Olah
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Publication number: 20110151679Abstract: A silicon-containing insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas including di-iso-propylaminosilane gas and a second process gas including an oxidizing gas or nitriding gas. The film is formed by performing a plurality of times a cycle alternately including first and second steps. The first step performs supply of the first process gas, thereby forming an adsorption layer containing silicon on a surface of the target substrate. The second performs supply of the second process gas, thereby oxidizing or nitriding the adsorption layer on the surface of the target substrate. The second step includes an excitation period of supplying the second process gas to the process field while exciting the second process gas by an exciting mechanism.Type: ApplicationFiled: March 4, 2011Publication date: June 23, 2011Applicant: Tokyo Electron LimitedInventors: Kazuhide HASEBE, Shigeru Nakajima, Jun Ogawa
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Publication number: 20110151678Abstract: Novel gap fill schemes involving depositing both flowable oxide films and high density plasma chemical vapor deposition oxide (HDP oxide) films are provided. According to various embodiments, the flowable oxide films may be used as a sacrificial layer and/or as a material for bottom up gap fill. In certain embodiments, the top surface of the filled gap is an HDP oxide film. The resulting filled gap may be filled only with HDP oxide film or a combination of HDP oxide and flowable oxide films. The methods provide improved top hat reduction and avoid clipping of the structures defining the gaps.Type: ApplicationFiled: December 9, 2010Publication date: June 23, 2011Inventors: Kaihan Ashtiani, Michael Wood, John Drewery, Naohiro Shoda, Bart van Schravendijk, Lakshminarayana Nittala, Nerissa Draeger
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Patent number: 7964517Abstract: According to various embodiments, the present teachings include methods for reducing first wafer defects in a high-density plasma chemical vapor deposition process. In an exemplary embodiment, the method can include running a deposition chamber for deposition of film on a first batch of silicon wafers and then cleaning interior surfaces of the deposition chamber. The method can further include inserting a protective electrostatic chuck cover (PEC) wafer on an electrostatic chuck in the deposition chamber and applying power to bias the PEC wafer while simultaneously precoating the deposition chamber with an oxide. The exemplary method can also include re-starting the deposition chamber for deposition of film on a second batch of silicon wafers.Type: GrantFiled: January 29, 2009Date of Patent: June 21, 2011Assignee: Texas Instruments IncorporatedInventor: Rajneesh Jaiswal
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Patent number: 7960294Abstract: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.Type: GrantFiled: July 21, 2009Date of Patent: June 14, 2011Assignee: Applied Materials, Inc.Inventors: Francimar Campana Schmitt, Li-Qun Xia, Son Van Nguyen, Shankar Venkataraman
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Patent number: 7955948Abstract: A manufacturing method of a semiconductor device includes the steps of carrying a substrate in a processing chamber, bringing the processing chamber into a state at a first pressure by supplying a silicon compound gas which contains carbon and hydrogen into the processing chamber, forming a silicon oxide film on the substrate by irradiating a UV light to the silicon compound gas supplied into the processing chamber in the state kept at the first pressure, and decompression process to bring the processing chamber into a state at a second pressure lower than the first pressure. This makes it possible to form the dense silicon oxide film in the trench with high aspect ratio and small width.Type: GrantFiled: September 1, 2009Date of Patent: June 7, 2011Assignee: Hitachi Kokusai Electric Inc.Inventors: Naofumi Ohashi, Yuichi Wada, Nobuo Owada, Takeshi Taniguchi
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Patent number: 7951683Abstract: In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of voids or weak spots is provided. This deposition part of the process may involve the use of any suitable high density plasma chemical vapor deposition (HDP CVD) chemistry. Prior to etch back, the feature gap is plugged with an etch selectivity layer. The etch back part of the process involves multiple steps including a sputter etch to reduce the top hat formations followed by a reactive plasma etch to open the gap. This method improves gapfill, reduces the use of high cost fluorine-based etching and produces interim gaps with better sidewall profiles and aspect ratios.Type: GrantFiled: April 6, 2007Date of Patent: May 31, 2011Assignee: Novellus Systems, IncInventor: Sunil Shanker
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Patent number: 7943531Abstract: A method of depositing a silicon oxide layer over a substrate includes providing a substrate to a deposition chamber. A first silicon-containing precursor, a second silicon-containing precursor and a NH3 plasma are reacted to form a silicon oxide layer. The first silicon-containing precursor includes at least one of Si—H bond and Si—Si bond. The second silicon-containing precursor includes at least one Si—N bond. The deposited silicon oxide layer is annealed.Type: GrantFiled: October 22, 2007Date of Patent: May 17, 2011Assignee: Applied Materials, Inc.Inventors: Srinivas D. Nemani, Abhijit Basu Mallick, Ellie Y. Yieh
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Patent number: 7935592Abstract: In a case of using a silicon nitride film as an offset spacer for forming an extension region of a transistor, an oxide protective surface is formed by oxygen plasma processing on the surface of the silicon nitride film.Type: GrantFiled: October 31, 2007Date of Patent: May 3, 2011Assignee: Renesas Electronics CorporationInventor: Takashi Watanabe