Abstract: A complementary metal-oxide-semiconductor (CMOS) device comprising a substrate, a first type of metal-oxide-semiconductor (MOS) transistor, a second type of MOS transistor, an etching stop layer, a first stress layer and a second stress layer is provided. The substrate has a first and a second active region. The first active region is isolated from the second active region through an isolation structure. The first type of MOS transistor is disposed in the first active region of the substrate and the second type of MOS transistor is disposed in the second active region of the substrate. The etching stop layer covers conformably the first type of MOS transistor, the second type of MOS transistor and the isolation structure. The first stress layer is disposed on the etching stop layer in the first active region and the second stress layer is disposed on the etching stop layer in the second active region.

Abstract: A method and system are described for increasing the tensile stress in thin films formed on a substrate, such as silicon nitride films. The thin film may be a planar film, or a non-planar film, such as a nitride film formed over a NMOS gate. The thin film is exposed to electro-magnetic (EM) radiation, such as EM radiation having a wavelength component less than about 500 nm. The EM source can include a multi-frequency source of radiation. Additionally, the source of radiation is collimated in order to selectively treat regions of a non-planar film.

Abstract: Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.

Abstract: An embodiment of the invention is a HDP CVD FSG layer and an HDP CVD SIN layer with more stability (e.g., less free F and less free H). A feature is that the FSG and SIN are formed using a HDP CVD process with a high plasma density between 1E12 and 1E15 ions/cc and more preferably between 1E14 and 1E15 ions/cc. The high bias has sufficient energy to break the F—Si bonds in the FSG. The high bias has sufficient energy to break the H—Si bonds in the silicon nitride. Whereby the FSG layer has less F and the SiN layer has less H that increases the FSG/SiN interface reliability. The embodiments can be used on smooth surfaces (non-gap fill applications).

Abstract: A method for fabricating a dielectric layer doped with nitrogen is provided according to the present invention. According to the method, a dielectric layer is formed on a semiconductor substrate. Two steps of nitridation processes are then performed on the dielectric layer. Following that, one step or two steps of annealing processes are performed on the dielectric layer. Dielectric layer formed by the method has uniform nitrogen dopant, and thus has fine electric properties.

Abstract: A method and system are described for increasing the tensile stress in thin films formed on a substrate, such as silicon nitride films. The thin film may be a planar film, or a non-planar film, such as a nitride film formed over a NMOS gate. The thin film is exposed to collimated electro-magnetic (EM) radiation to anisotropically expose the film. The EM radiation can have a component having a wavelength less than about 500 nm. The EM source can include a multi-frequency source of radiation.

Abstract: A method of depositing tensile or compressively stressed silicon nitride on a substrate is described. Silicon nitride having a tensile stress with an absolute value of at least about 1200 MPa can be deposited from process gas comprising silicon-containing gas and nitrogen-containing gas, maintained in an electric field having a strength of from about 25 V/mil to about 300 V/mil. The electric field is formed by applying a voltage at a power level of less than about 60 Watts across electrodes that are spaced apart by a separation distance that is at least about 600 mils. Alternatively, silicon nitride having a compressive stress with an absolute value of at least about 2000 MPa can be formed in an electric field having a strength of from about 400 V/mil to about 800 V/mil.

Abstract: A semiconductor device having an etch stop layer and a method of fabricating the same are provided. The semiconductor device may include a substrate and a first gate electrode formed on the substrate. An auxiliary spacer may be formed on the sidewall of the first gate electrode. An etch stop layer may be formed on the substrate having the auxiliary spacer. The etch stop layer and the auxiliary spacer may be formed of a material having a same stress property.

Abstract: The present invention provides a processing system comprising a remote plasma activation region for formation of active gas species, a transparent transfer tube coupled between the remote activation region and a semiconductor processing chamber, and a source of photo-energy for maintaining activation of the active species or providing photo-energy for a non-plasma species during transfer through the transparent tube to the processing chamber. The source of photo-energy preferably includes an array of UV lamps. Additional UV lamps may also be used to further sustain active species and assist processes by providing additional in-situ energy through a transparent window of the processing chamber. The system can be utilized for processes such as layer-by-layer annealing and deposition and also removal of contaminants from deposited layers.

Abstract: The present invention discloses an improved shallow trench isolation process. A semiconductor substrate having a pad oxide disposed thereon and a pad nitride disposed directly on the pad oxide is provided. A trench is etched, through the pad oxide and the pad nitride, into the semiconductor substrate. A thermal oxide liner is then grown in the trench. A silicon nitride liner is deposited into the trench, wherein the silicon nitride liner covering the pad nitride and the thermal oxide liner has a first stress status. A stress alteration process is performed to alter the silicon nitride liner from the first stress status to a second stress status. A trench fill dielectric having the second stress status is deposited into the trench.

Abstract: A substrate processing method forming an oxynitride film by nitriding an oxide film formed on a silicon substrate includes a nitridation processing step that nitrides a surface of the oxide film by radicals or ions formed by exciting a nitrogen gas by microwave-excited plasma, the nitridation processing is conducted at a substrate temperature of 500° C. or less by setting an electron temperature of the microwave-excited plasma to 2 eV or less, and by setting the resident time of oxygen in the processing space in which the substrate to be processed is held, to two seconds or less.

Abstract: A method and apparatus for depositing a material layer onto a substrate is described. The method includes placing the substrate in a process chamber, delivering a mixture of precursors for the material layer into the process chamber, delivering a hydrogen gas into the process chamber to improve water-barrier performance of the material layer, controlling the temperature of the substrate to a temperature of about 100° C. or lower, applying an electric field and generating a plasma inside the process chamber, and depositing the material layer on the substrate. The material layer can be used as an encapsulating layer for various display applications which require low temperature deposition process due to thermal instability of underlying materials used. The encapsulating layer thus deposited provides reduced surface roughness, improved water-barrier performance which can be applied to any substrate type including wafer, glass, and plastic film (e.g., PET, PEN, etc.

Abstract: A method is provided for contact opening definition for active element electrical connections. According to the method, a layer of BPSG is formed on a surface of an integrated circuit, and a transparent layer of nitride UV is formed above the layer of BPSG. Preferably, the transparent layer of nitride UV is formed by deposition using an HDP process and has a thickness of less than about 500 ?. In one embodiment, after forming a transparent layer of nitride UV, two overlapped layers of BARC and resist are formed on the surface of the integrated circuit. Also provided is a machine-readable medium encoded with a program for contact opening definition for active element electrical connections.

Abstract: A process for producing an electronic device material of a high quality MOS-type semiconductor having an insulating layer and a semiconducting layer. The process includes a step of CVD-treating a substrate to be processed having single-crystal silicon as a main component to thereby form an insulating layer, and a step of exposing the substrate to be processed to a plasma which has been generated from a process gas on the basis of microwave irradiation via a plane antenna member having a plurality of slots to thereby modify the insulating film by using the thus generated plasma.

Abstract: A silicon nitride spacer material for use in forming a PFET device and a method for making the spacer includes the use of a dual-frequency plasma enhanced CVD process wherein the temperature is in the range depositing a silicon nitride layer by means of a low-temperature dual-frequency plasma enhanced CVD process, at a temperature in the range 400° C. to 550° C. The process pressure is in the range 2 Torr to 5 Torr. The low frequency power is in the range 0 W to 50 W, and the high frequency power is in the range 90 W to 110 W. The precursor gases of silane, ammonia and nitrogen flow at flow rates in the ratio 240:3200:4000 sccm. The use of the silicon nitride spacer of the invention to form a PFET device having a dual spacer results in a 10%–15% performance improvement compared to a similar PFET device having a silicon nitride spacer formed by a RTCVD process.

Abstract: A method of depositing a non-conductive barrier layer onto a metal surface wherein the resistance of the metal remains substantially unchanged before and after the non-conductive barrier layer deposition. The deposition process provides a low temperature processing environment so as to inhibit the formation of impurities such as silicide in the metal, wherein the silicide can adversely increase the resistance of the underlying metal.

Abstract: A method for forming a nitrided tunnel oxide layer is described. A silicon oxide layer as a tunnel oxide layer is formed on a semiconductor substrate, and a plasma nitridation process is performed to implant nitrogen atoms into the silicon oxide layer. A thermal drive-in process is then performed to diffuse the implanted nitrogen atoms across the silicon oxide layer.

Abstract: The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.

Abstract: The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.

Abstract: A method for plasma processing of semiconductor wafers is provided that reduces plasma-induced damage to the gate dielectric while limiting damage to the wafer from particulates that flake off of the interior surfaces of the reaction chamber. Plasma conditions are maintained in the reaction chamber while the wafer is transferred into the chamber and the plasma process is performed. After the plasma process, while still maintaining plasma conditions, the wafer is cooled to a removal temperature and removed from the reaction chamber.

Abstract: A method for low-temperature plasma-enhanced chemical vapor deposition of a silicon-nitrogen-containing film on a substrate. The method includes providing a substrate in a process chamber, exciting a reactant gas in a remote plasma source, thereafter mixing the excited reactant gas with a silazane precursor gas, and depositing a silicon-nitrogen-containing film on the substrate from the excited gas mixture in a chemical vapor deposition process. In one embodiment of the invention, the reactant gas can contain a nitrogen-containing gas to deposit a SiCNH film. In another embodiment of the invention, the reactant gas can contain an oxygen-containing gas to deposit a SiCNOH film.

Abstract: We have developed a method of PECVD depositing a-SiNx:H films which are useful in a TFT device as gate dielectric and passivation layers, when a series of TFT devices are arrayed over a substrate having a surface area larger than about 1 m2, which may be in the range of about 4.1 m2, and even as large as 9 m2. The a-SiNx:H films provide a uniformity of film thickness and uniformity of film properties, including chemical composition, which are necessary over such large substrate surface areas. The films produced by the method are useful for both liquid crystal active matrix displays and for organic light emitting diode control.

Abstract: CVD is performed without damaging a micro-fabricated semiconductor element. An organic material gas containing amine is used as deposition material gas. The material gas is introduced into a vacuum chamber and ultraviolet light radiated from each of lamps is applied onto an object to be processed that is placed in the chamber, thereby causing chemical vapor deposition to be carried out, whereby a film is grown at a temperature such that no damage is given to a semiconductor element or the like of the object.

Abstract: A fabrication process of a flash memory device includes microwave excitation of high-density plasma in a mixed gas of Kr and an oxidizing gas or a nitriding gas. The resultant atomic state oxygen O* or hydrogen nitride radicals NH* are used for nitridation or oxidation of a polysilicon electrode surface. It is also disclosed the method of forming an oxide film and a nitride film on a polysilicon film according to such a plasma processing.

Abstract: It is an object of the present invention is to provide a technique for forming a dense insulating film of good quality that is applicable to a transistor made on a substrate weak against heat such as a glass and a semiconductor device that can realize high performance and high reliability using the technique. In the present invention a silicon oxide film is formed on a crystalline semiconductor film, which is formed on an insulating surface, by the sputtering method using silicon as a target by applying high-frequency power in an atmosphere containing oxygen or oxygen and a rare gas, a silicon nitride film is formed thereon by applying high-frequency power in an atmosphere containing nitrogen or nitrogen and a rare gas, and then, heat treatment of a stacked body of the crystalline semiconductor film, the silicon oxide film, and the silicon nitride film at a temperature higher than a temperature for forming the films is performed.

Abstract: A method for fabricating a thin film oxide is provided. The method includes: forming a substrate; treating the substrate at temperatures equal to and less than 360° C. using a high density (HD) plasma source; and forming an M oxide layer overlying the substrate where M is an element selected from a group including elements chemically defined as a solid and having an oxidation state in a range of +2 to +5. In some aspects, the method uses an inductively coupled plasma (ICP) source. In some aspects the ICP source is used to plasma oxidize the substrate. In other aspects, HD plasma enhanced chemical vapor deposition is used to deposit the M oxide layer on the substrate. In some aspects of the method, M is silicon and a silicon layer and an oxide layer are incorporated into a TFT.

Abstract: A three-dimensional integrated circuit formed by applying a material to fill a gap between coupled wafers and slicing the coupled wafers into dice. A method for filling a gap between coupled wafers. Various embodiments include at least one of spinning a coupled wafer pair, drilling a hole into one of the coupled wafers, and using a vacuum to aid in the dispersion of the material.

Abstract: A method of forming a multi-layered thin film uses photolysis chemical vapor deposition (PCVD). In the method, a substrate for a process of forming the multi-layered thin film is prepared. At least two source gases are supplied to the substrate. Reaction lights having particular wavelengths are prepared, which are absorbed by each of the source gases, are prepared. The reaction lights having particular wavelengths are alternatingly emitted on the substrate to a form a predetermined multi-layered thin film. A photolysis chemical vapor deposition (PCVD) reactor is disclosed, having a chamber with a substrate support, a gas supply system for supplying a plurality of source gases to the substrate in the chamber, and a light supply system mounted at one side of the chamber. The light supply system selectively emits one of the plurality of reaction lights having different wavelengths on the substrate.

Abstract: The temperature of the sputtering process for forming the Ti film is selected to a temperature within a range of from 200 degree C. to 225 degree C. to provide stable film quality against oxidization (step 11). The irradiation with ultraviolet is conducted before applying the photo resist to reduce positive electric charge (step 12), and nitrogen plasma processing is conducted during the etching of the via hole and after the plasma stripping processing to reduce positive electric charge (steps 13 and 14), and the resistivity of the rinse liquid at the organic stripping is controlled to obtain equal to or lower than 0.3M? cm (step 15). Further, the RF-spattered thickness during the RF sputtering process for the barrier metal film is set to 18 nm to 22 nm to remove TiOn film (step 16).

Abstract: The present invention pertains to forming a transistor in the absence of hydrogen, or in the presence of a significantly reduced amount of hydrogen. In this manner, a high-k material can be utilized to form a gate dielectric layer in the transistor and facilitate device scaling while mitigating defects that can be introduced into the high-k material by the presence of hydrogen and/or hydrogen containing compounds.

Abstract: An integrated circuit is provided comprising a substrate and discrete areas of electrically insulating and electrically conductive material, wherein the electrically insulating material is a hybrid organic-inorganic material that has a density of 1.45 g/cm3 or more and a dielectric constant of 3.0 or less. The integrated circuit can be made by a method comprising: providing a substrate; forming discrete areas of electrically insulating and electrically conductive material on the substrate; wherein the electrically insulating material is deposited on the substrate followed by heating at a temperature of 350° C. or less; and wherein the electrically insulating material is a hybrid organic-inorganic material that has a density of 1.45 g/cm3 or more after densification. Also disclosed is a method for making an integrated circuit comprising performing a dual damascene method with an electrically conductive material and a dielectric, the dielectric being a directly photopatterned hybrid organic-inorganic material.

Abstract: According to the invention, while performing plasma-enhanced chemical vapor deposition on a substrate by exposing the substrate in a vacuum to a flow of particles generated by a plasma, which particles react to form a passivation layer on the substrate, a grid is interposed between the plasma and the substrate, thereby reducing the flow of charged particles towards the substrate while conserving a flow of neutral particles. The grid is formed of metal wires that are crossed at a pitch that is less than two or three times the Debye length (?D) of the plasma used, at least at the beginning of deposition. The aging properties of semiconductor components made by such a method is thereby improved.

Abstract: A semiconductor device producing method using a plasma processing apparatus including a processing chamber, a substrate-supporting body which supports a substrate in the processing chamber, and a cylindrical electrode and a magnetic lines of force-forming member disposed around the processing chamber, comprises forming an oxide film on the substrate, and thereafter, by changing a high frequency impedance of the substrate-supporting body, continuously forming an oxynitride film by nitriding the oxide film by activated species of nitrogen which are activated by plasma.

Abstract: A method for oxidizing a nitride film is disclosed, which includes the steps of: providing a nitride film formed on an electrically conductive substrate; irradiating the nitride film with a light beam and getting close to the nitride film with a electrically conductive probe; and exerting a bias between the electrically conductive substrate and the electrically conductive probe. The method can oxidize the nitrides quickly and reduce the cost building a nano-structure in the nitride film. An apparatus for oxidizing a nitride film is also disclosed herewith.

Abstract: A semiconductor apparatus is provided that is thermally stable in a post process and is suitable for fabricating a gate insulator having a laminated structure with various high permittivity oxides, and a process is provided for producing the same. In order to achieve a high function formation of a gate insulator, a silicon nitride film having a specific inductive capacity approximately twice as much as that of silicon oxide, and which is thermally stable, is not provided with a Si—H bond and is used as at least a portion of the gate insulator. Further, an effective thickness of a gate insulator forming a multilayered structure insulator laminated with a metal oxide having a high dielectric constant, in conversion to silicon oxide, can be thinned to less than 3 nm while restraining leakage current.

Abstract: With keeping an atmosphere including oxygen within a chamber and with a wafer kept at a low temperature, plasma generated within the chamber is biased toward the wafer, and the wafer is subjected to the plasma. A semiconductor layer exposed on the wafer is oxidized into an oxide film. Thus, an oxide film can be formed even at room temperature differently from thermal oxidation. This oxidation is applicable to recovery of an implantation protection insulating film having been etched in cleaning a photoresist film, relaxation of a step formed between polysilicon films, relaxation of a step formed within a trench and the like. Also, before removing a photoresist film used for forming a gate electrode including a metal, a contamination protection film can be formed by this oxidation with the photoresist film kept.

Abstract: A plasma surface treatment system for irradiating a surface of a substrate to be treated with a nitrogen plasma excited by a high-frequency electric field to introduce nitrogen into the surface of the substrate comprises a pulse modulator for pulse modulation of the high-frequency electric field. By applying the high-frequency electric field in a pulsed form, it is possible to realize a nitriding by which the peak of nitrogen concentration is located at a shallower position and a desired nitrogen concentration can be obtained.

Abstract: A fabrication process of a flash memory device includes microwave excitation of high-density plasma in a mixed gas of Kr and an oxidizing gas or a nitriding gas. The resultant atomic state oxygen O* or hydrogen nitride radicals NH* are used for nitridation or oxidation of a polysilicon electrode surface. It is also disclosed the method of forming an oxide film and a nitride film on a polysilicon film according to such a plasma processing.

Abstract: An embodiment of the instant invention is a method of forming a dielectric layer on a silicon-containing structure, the method comprising the steps of: providing a nitrogen-containing gas; heating the silicon-containing structure to an elevated temperature which is greater than 700 C; and striking a plasma above the silicon-containing structure, wherein combination of the nitrogen-containing gas, the elevated temperature, and the plasma resulting in the thermal nitridation of a portion of the silicon-containing structure. Preferably, the elevated temperature is greater than 900 C (more preferably the elevated temperature is greater than 1000 C). The silicon-containing structure is, preferably, a silicon substrate or a bottom electrode of a storage capacitor of a memory device.

Abstract: This invention relates to the fabrication of planar inductive components whereby the design in cross-section describes a conductor surrounded by magnetic material along the length of the conductor; an electrical insulator is placed between the conductor and the magnetic material. Cases also apply where more than one independent conductor is used. The planar form allows integration of inductive components with integrated circuits. These inductive components can be embedded in other materials. They can also be fabricated directly onto parts.

Abstract: A deposition method includes forming a nucleation layer over a substrate, forming a layer of a first substance at least one monolayer thick chemisorbed on the nucleation layer, and forming a layer of a second substance at least one monolayer thick chemisorbed on the first substance. The chemisorption product of the first and second substance may include silicon and nitrogen. The nucleation layer may comprise silicon nitride. Further, a deposition method may include forming a first part of a nucleation layer on a first surface of a substrate and forming a second part of a nucleation layer on a second surface of the substrate. A deposition layer may be formed on the first and second parts of the nucleation layer substantially non-selectively on the first part of the nucleation layer compared to the second part. The first surface may be a surface of a borophosphosilicate glass layer. The second surface may be a surface of a rugged polysilicon layer.

Abstract: A vapor reaction method including the steps of providing a pair of first and second electrodes within a reaction chamber where the pair of electrodes are arranged substantially parallel with each other. The method further includes the steps of placing a substrate in the reaction chamber where the substrate is held by said first electrode so that a first surface of the substrate faces toward the second electrode. A first film forming gas is introduced into the reaction chamber through the second electrode. The first film forming gas is excited to form a first insulating film by vapor deposition. The first insulating film may be silicon nitride. The method may also include the step of introducing a second film forming gas into the reaction chamber through the second electrode to ultimately form a second film. After removing the substrate from the reaction chamber, a cleaning gas may then be introduced through the second electrode to remove unnecessary layers from the inside of the reaction chamber.

Abstract: A method of manufacturing a semiconductor device by which a generation of a void is prevented after depositing an interlayer dielectric material. First, a plurality of conductive patterns are formed on a substrate and then, a capping insulation layer is formed on the conductive patterns. The capping insulation layer is treated with plasma, and an interlayer dielectric material is deposited on the plasma treated capping insulation layer. The dependency of the interlayer dielectric on the type of material and form of an underlying layer is reduced to improve a gap-filling characteristic, especially for a gap having a high aspect ratio. An improved gap-filling characteristic is accomplished and the formation of all or substantially all of the voids from forming in a gap is prevented even though an interlayer dielectric is deposited under a conventional deposition conditions.

Abstract: A method of forming dual gate insulator layers, each with a specific insulator thickness, featuring a HF type pre-clean procedure performed prior to formation of each of the gate insulator layers, has been developed. After a first HF type pre-clean procedure a silicon nitride layer is deposited on the native oxide free, semiconductor substrate followed by selective removal of silicon nitride layer from a second portion of the semiconductor substrate. After a second HF type pre-clean procedure a silicon dioxide gate insulator layer is formed on the second portion of the native oxide free, semiconductor substrate, with the silicon dioxide gate insulator layer comprised with a different thickness than the silicon nitride gate insulator layer, located on a first portion of the semiconductor substrate. The procedure used to form the silicon dioxide gate insulator layer also removes bulk traps in the silicon nitride gate insulator layer.

Abstract: A method for forming a low-k dielectric layer for a semiconductor device using an ALD process including (a) forming predetermined interconnection patterns on a semiconductor substrate, (b) supplying a first and a second reactive material to a chamber having the substrate therein, thereby adsorbing the first and second reactive materials on a surface of the substrate, (c) supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, (d) supplying a third reactive material to the chamber, thereby causing a reaction between the first and second materials and the third reactive material to form a monolayer, (e) supplying a second gas to the chamber to purge the third reactive material that remains unreacted in the chamber and a byproduct; and (f) repeating (b) through (e) a predetermined number of times to form a SiBN ternary layer having a predetermined thickness on the substrate.

Abstract: A reduction of a leakage current as well as a decrease in the thickness of an insulating film is realized in a semiconductor device. To this end, a silicon oxide film and a silicon nitride film are formed on a substrate, which is then heated to a temperature within a range of 20° C.–600° C. so that a plasma nitridation process can be performed on the silicon nitride film. Further, a thermal process is performed in a non-oxide gas atmosphere. By performing these processes, the gate leakage current can be significantly reduced in the formed gate insulator, and the silicon oxide-equivalent thickness of the insulating film can be significantly decreased as well.

Abstract: A capacitor and a capacitor dielectric material are fabricated by adjusting the amount of an ionic conductive species, such as hydrogen, contained in the capacitor dielectric material to obtain predetermined electrical or functional characteristics. Forming the capacitor dielectric material from silicon, nitrogen and hydrogen allows a stoichiometric ratio control of silicon to nitrogen to limit the amount of hydrogen. Forming the capacitor by dielectric material plasma enhanced chemical vapor deposition (PECVD) allows hydrogen bonds to be broken by ionic bombardment, so that stoichiometric control is achieved by controlling the power of the PECVD. Applying a predetermined number of thermal cycles of temperature elevation and temperature reduction also breaks the hydrogen bonds to control the amount of the hydrogen in the formed capacitor dielectric material.

Abstract: A vacuum chamber with a cover with a first section, a second section, and a pocket between the first section and second section is provided. The vacuum chamber has a main cavity to which the first section is adjacent. The vacuum chamber may be used for plasma processing, which may require a critical element to be supported by the first section. The pocket is in fluid communication with the main cavity. When a vacuum is created in the main cavity, the pressure is also reduced in the pocket. As a result, the second section of the cover is deformed by the vacuum in the pocket. However, the vacuum in the pocket helps to prevent the first section from deforming, providing better support for the critical element.

Abstract: A method for the passivation of a semiconductor substrate, wherein a SiNx:H layer is deposited on the surface of the substrate (1) by means of a PECVD process comprising the following steps: the substrate (1) is placed in a processing chamber (5) which has specific internal processing chamber dimensions; the pressure in the processing chamber is maintained at a relatively low value; the substrate (1) is maintained at a specific treatment temperature; a plasma (P) is generated by at least one plasma cascade source (3) mounted on the processing chamber (5) at a specific distance (L) from the substrate surface; at least a part of the plasma (P) generated by each source (3) is brought into contact with the substrate surface; and flows of silane and ammonia are supplied to said part of the plasma (P).

Abstract: In a plasma processing method making use of a plasma processing gas of a reactant gas and an inert gas, it is aimed at enhancing an efficiency of use of high-frequency power and a reactant gas to increase a processing rate. The plasma processing method comprises supplying high frequency power to an electrode 2 opposed to a substrate 6 to thereby generate plasma between the electrode 2 and the substrate 6 on the basis of a plasma processing gas comprising a reactant gas and an inert gas to perform film formation, etching, surface treatment or the like on the substrate 6, pressure P(Torr) of the plasma processing gas being set to satisfy the following relationship 2×10?7(Torr/Hz)×f(Hz)?P(Torr)?500(Torr) where f(Hz) is a frequency of high frequency power.