Abstract: A method of making a bonded intermediate substrate includes forming a weak interface in a GaN source substrate by implanting ions into an N-terminated surface of the GaN source substrate, bonding the N-terminated surface of the GaN source substrate to a handle substrate, and exfoliating a thin GaN single crystal layer from the source substrate such that the thin GaN exfoliated single crystal layer remains bonded to the handle substrate and a Ga-terminated surface of the thin GaN single crystal layer is exposed. The method further includes depositing a capping layer directly onto the exposed surface of the thin GaN single crystal layer, and annealing the thin GaN single crystal layer in a nitrogen containing atmosphere after depositing the capping layer. The in-plane strain present in the thin GaN single crystal layer after the annealing is reduced relative to an in-plane strain present in said layer prior to the annealing.

Abstract: A semiconductor layer contains, as a principal constituent, a Group III-V semiconductor compound, which may be represented by the general formula: AlxGayInzN, wherein x represents a number satisfying the condition 0?x<1, y represents a number satisfying the condition 0<y<1, and z represents a number satisfying the condition 0<z<1, with the proviso that x+y+z=1. The semiconductor layer is formed with a laser assisted metalorganic vapor phase epitaxy technique. A semiconductor light emitting device comprises the semiconductor layer and may be constituted as a semiconductor laser or a light emitting diode.

Abstract: A method of producing a silicon carbide semiconductor device, including: step (A) of forming an impurity-doped region by implanting impurity ions 3 into at least a portion of a silicon carbide layer 2 formed on a first principal face of a silicon carbide substrate 1 having first and second principal faces; step (B) of forming capping layers 6 having thermal resistance on at least an upper face 2a of the silicon carbide layer 2 and on at least a second principal face 12a of the silicon carbide substrate 1; and step (C) of performing an activation annealing treatment by heating the silicon carbide layer 2 at a predetermined temperature.

Abstract: The invention provides a nanowire light emitting device and a manufacturing method thereof. In the light emitting device, first and second conductivity type clad layers are formed and an active layer is interposed therebetween. At least one of the first and second conductivity type clad layers and the active layer is a semiconductor nanowire layer obtained by preparing a layer of a mixture composed of a semiconductor nanowire and an organic binder and removing the organic binder therefrom.

Abstract: There is provided a method of forming a pattern on a group III nitride semiconductor substrate. A method of forming a pattern on a group III nitride semiconductor substrate according to an aspect of the invention may include: irradiating a laser beam onto at least one first region for preventing etching in a group III nitride semiconductor substrate; and etching at least one second region exclusive of the first region using the first region irradiated with the laser beam as a mask.

Abstract: The present invention provides a semiconductor device fabrication method capable of reducing the thermal load on the substrate. The present invention also provides a semiconductor device fabrication method capable of improving the characteristics of a semiconductor element. The semiconductor device fabrication method according to the present invention comprises a step of thermally processing a semiconductor layer that is deposited on a substrate by using, as a heat source, the flame of a gas burner that uses a mixed gas of hydrogen and oxygen as fuel. As a result of thermal processing, the semiconductor layer is re-crystallized and an oxide film is formed on the surface of the semiconductor layer. The oxide film can be used as a gate insulation film and a capacitive insulation film.

Abstract: There is provided a surface treatment method of a group III nitride semiconductor including: providing a group III nitride semiconductor including a first surface having a group III polarity and a second surface opposing the first surface and having a nitrogen polarity; and irradiating a laser beam onto the second surface to change the nitrogen polarity of the second surface to the group III polarity.

Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming a trench for a MOS gate in an SiC substrate by dry etching. Thereafter, the substrate with the trench is heat treated. The heat treatment includes heating the substrate in an Ar gas atmosphere or in a mixed gas atmosphere containing SiH4 and Ar at a temperature between 1600° C. and 1800° C., and thereafter in a hydrogen gas atmosphere at a temperature between 1400° C. and 1500° C. The present manufacturing method smoothens the trench inner surface and rounds the corners in the trench to prevent the electric field from localizing thereto.

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Abstract: A heat treatment method for compound semiconductors includes a step for placing an object to be treated on a stage in a process chamber, and a step for irradiating the surface of the object with an electromagnetic wave having a specific frequency by introducing the electromagnetic wave into the process chamber. A compound semiconductor is heat-treated by the electromagnetic wave irradiated upon the surface of the object to be treated.

Abstract: Method of processing a substrate containing at least one semiconductor of the SiXAY type and comprising at least four separate types of light elements, comprising at least the following steps: carrying out a first anneal of the substrate at a temperature T1 corresponding to a thermal activation temperature for a first one of the four types of light elements, carrying out a second anneal of the substrate at a temperature T2 corresponding to a thermal activation temperature for a second one of the four types of light elements, carrying out a third anneal of the substrate at a temperature T3 corresponding to a thermal activation temperature for a third one of the four types of light elements, carrying out a fourth anneal of the substrate at a temperature T4 corresponding to a thermal activation temperature for a fourth one of the four types of light elements, each anneal comprising a holding at the temperature T1, T2, T3 or T4 and the temperatures T1, T2, T3 and T4 being such that T1>T2>T3>T4.

Abstract: A method of fabrication of laser gain material and utilization of such media includes the steps of introducing a transitional metal, preferably Cr2+ thin film of controllable thickness on the ZnS crystal facets after crystal growth by means of pulse laser deposition or plasma sputtering, thermal annealing of the crystals for effective thermal diffusion of the dopant into the crystal volume with a temperature and exposition time providing the highest concentration of the dopant in the volume without degrading laser performance due to scattering and concentration quenching, and formation of a microchip laser either by means of direct deposition of mirrors on flat and parallel polished facets of a thin Cr:ZnS wafer or by relying on the internal reflectance of such facets.

Abstract: Provided is a semiconductor light emitting diode that uses a silicon nano dot and a method of manufacturing the same. The semiconductor light emitting diode includes a light emitting layer that emits light; a hole injection layer formed on the light emitting layer; an electron injection layer formed on the light emitting layer to face the hole injection layer; a metal layer that includes a metal nano dot and is formed on the electron injection layer; and a transparent conductive electrode formed on the metal layer. Amorphous silicon nitride that includes the silicon nano dot is used as the light emitting layer.

Abstract: A method of manufacturing a nitride semiconductor device includes the steps of: growing a group III nitride semiconductor layer on a substrate; forming a processed region in the substrate with a laser beam; and reducing the thickness of the substrate thereby spontaneously dividing the substrate from the processed region by the internal stress of the substrate. The substrate may be a sapphire substrate or an SiC substrate.

Abstract: According to one embodiment of the invention, a method of modifying a mechanical, physical and/or electrical property of a dielectric layer comprises exposing the dielectric layer to a first dose of electron beam radiation at a first energy level; and thereafter, exposing the dielectric layer to a second dose of electron beam radiation at a second energy level that is different from the first energy level.

Abstract: Provided are mono- and diimide naphthalene compounds for use in the fabrication of various device structures. In some embodiments, the naphthalene core of these compounds are mono-, di-, or tetra-substituted with cyano group(s) or other electron-withdrawing substituents or moieties. Such mono- and diimide naphthalene compounds also can be optionally N-substituted.

Abstract: A substrate heating apparatus having a conductive heater which heats a substrate includes a filament arranged in the conductive heater and connected to a filament power supply to generate thermoelectrons, and an acceleration power supply which accelerates the thermoelectrons between the filament and conductive heater. The filament has inner peripheral portions formed at a predetermined interval along an inner circle concentric with the substrate, outer peripheral portions formed at a predetermined interval on an outer circle concentric with the inner circle and having a diameter larger than that of the inner circle, and a region formed by connecting the end point of each inner peripheral portions and the end point of a corresponding one of the outer peripheral portions.

Abstract: A method for controlling dislocation position in a silicon germanium buffer layer located on a substrate includes irradiating one or more regions of the silicon germanium layer with a dislocation inducing agent and depositing a strained silicon germanium layer on the substrate. The dislocation inducing agent may include ions, electrons, or other radiation source. Dislocations in the silicon germanium layer are located in one or more of the regions. The substrate and strained silicon germanium layer may then be subjected to an annealing process to transform the strained silicon germanium layer into a relaxed state. A top layer of strained silicon or silicon germanium may be deposited on the relaxed silicon germanium layer. Semiconductor-based devices may then be fabricated in the non-damaged regions of the strained silicon or silicon germanium layer. Threading dislocations are confined to damaged areas which may be transformed into SiO2 isolation regions.

Abstract: In a production process for a semiconductor device employing an SiC semiconductor substrate (1), the SiC semiconductor substrate (1) is mounted on a susceptor (23), and a C heating member (3) of carbon is placed on a surface of the SiC semiconductor substrate (1). An annealing process is performed to form an impurity region in the surface of the SiC semiconductor substrate (1) by causing the susceptor (23) and the C heating member (3) to generate heat at high temperatures.

Abstract: Using a helium cryostat, the temperature for a substrate wafer(s) is reduced to 2.2 Kelvin over a period of twenty-four hours. Next, a soak segment will hold the temperature of the substrate wafer at 2.2 Kelvin for a period of ninety-six hours. At these low temperatures, alloys such as GaAs, InP, and GaP will form dipole molecular moments, which will re-align along lines of internal magnetic force as molecular bonds condense. Next the substrate wafer's temperature is ramped up to room temperature over a period of twenty-four hours. Next, the temperature of the substrate wafer is ramped up to assure that the temperature gradients made to occur within the wafer are kept low. Next, the substrate wafer undergoes a temper hold segment, which assures that the entire substrate wafer has had the benefit of the tempering temperature.

Abstract: The present invention is to provide a heat treatment method for effectively eliminating Te deposits in a ZnTe single crystal substrate, and a ZnTe single crystal substrate having an optical characteristic suitable for use of a light modulation element and having a thickness of 1 mm or more. A heat treatment method of a ZnTe single crystal substrate, includes: a first step of increasing a temperature the ZnTe single crystal substrate to a first heat treatment temperature T1, and retaining the temperature of the substrate for a predetermined time; and a second step of gradually reducing the temperature of the substrate from the first heat treatment temperature T1 to a second heat treatment temperature T2 lower than the heat treatment temperature T1 with a predetermined rate, wherein the first heat treatment temperature T1 is set in a range of 700° C.?T1?1250° C. and the second heat treatment temperature T2 is set in a range of T2?T1?50.

Abstract: Objects of the present invention is to reduce a number of scanning a linear laser, to shorten the amount of time for laser annealing, and to reduce a manufacturing process, a manufacturing time, and manufacturing cost of a semiconductor device. In this invention, a gas at high temperature is locally blown so as to overlap at an irradiation surface of linear laser light. The linear laser light can be obtained by injecting laser light radiated from a laser oscillator into a lens. The gas at high temperature can be obtained by heating a gas which is compressed using a gas compressor, by a nozzle type heater. The heated has is sprayed so as to overlap with the irradiation surface of the linear laser light.

Abstract: Provided are a wafer with the characteristics of abrupt metal-insulator transition (MIT), and a heat treatment apparatus and method that make it possible to mass-produce a large-diameter wafer without directly attaching the wafer to a heater or a substrate holder. The heat treatment apparatus includes a heater applying heat to a wafer having the characteristics of abrupt MIT and one surface covered with a thermally opaque film, and a plurality of fixing units formed along an edge portion of a top surface of the heater to fix the wafer to the heater.

Abstract: It is an object of the present invention to provide a porous body containing an oxide semiconductor in which more efficient photocatalytic reactions and photoelectrode reactions occur. The present invention relates to a porous body having a network structure skeleton wherein 1) the aforementioned skeleton is composed of an inner part and a surface part, 2) the aforementioned inner part is substantially made of carbon material, and 3) all or part of the aforementioned surface part is an oxide semiconductor, and to a manufacturing method therefor.

Abstract: An embodiment of a multilayer wafer according to the invention includes a base substrate, a first layer associated with the base substrate, and a second layer on the first layer on side opposite from the base substrate in an axial direction and having a lateral edge. The first layer includes a ridge that protrudes axially and is disposed laterally adjacent the second layer measured in a direction normal to the axial direction for protecting the lateral edge. This ridge can surround portion the lateral edge in an axial cross-section for preventing edge falls. Also, the ridge can have an axial height greater than the axial thickness of the second layer. In one embodiment, the second layer includes an oxydizable semiconductor and the first layer includes an oxidized insulator.

Abstract: In a Group-III-element nitride semiconductor device including a Group-III-element nitride crystal layer stacked on a Group-III-element nitride crystal substrate, the substrate is produced by allowing nitrogen of nitrogen-containing gas and a Group III element to react with each other to crystallize in a melt (a flux) containing at least one of alkali metal and alkaline-earth metal, and a thin film layer is formed on the substrate and the thin film has a lower diffusion coefficient than that of the substrate with respect to impurities contained in the substrate. The present invention provides a semiconductor device in which alkali metal is prevented from diffusing.

Abstract: Disclosed is a method for forming a polycrystalline silicon film of a polycrystalline silicon thin film transistor. The method includes a step of crystallizing an amorphous silicon film deposited on a glass substrate by irradiating a laser beam onto the amorphous silicon film using a mask pattern. The glass substrate is horizontally moved by a predetermined distance unit corresponding to a translation distance of the mask pattern when the laser beam is irradiated onto the amorphous silicon film through a mask having the mask pattern, thereby growing grains in a circular shape.

Abstract: A method of processing a type III–VI semiconductor material on a silicon substrate to improve minority carrier diffusion length and EBIC response is provided. The semiconductor material is heated to a temperature in the range of 300° C.–600° C. for a period in the range of 20 seconds to 60 minutes in an atmosphere having a composition of 0–10% of hydrogen in nitrogen.

Abstract: A device for thermally treating semiconductor wafers having at least one silicon layer to be oxidized and a metal layer, preferably a tungsten layer, which is not to be oxidized. The inventive device comprises the following: at least one radiation source; a treatment chamber receiving the substrate, with at least one wall part located adjacent to the radiation sources and which is substantially transparent for the radiation of said radiation source; and at least one cover plate between the substrate and the wall part of the treatment chamber located adjacent to the radiation sources, the dimensions of said cover plate being selected such that it fully covers the transparent wall part of the treatment chamber in relation to the substrate in order to prevent material, comprising a metal, metal oxide or metal hydroxide such as tungsten, tungsten oxide or tungsten hydroxide, from said substrate from becoming deposited on or evaporating onto the transparent wall part of the treatment chamber.

Abstract: A method of reducing propagation of threading dislocations into active areas of an optoelectronic device having a III–V material system includes growing a metamorphic buffer region in the presence of an isoelectronic surfactant. A first buffer layer may be lattice matched to an adjacent substrate and a second buffer layer may be lattice matched to device layers disposed upon the second buffer layer. Moreover, multiple metamorphic buffer layers fabricated in this manner may be used in a single given device allowing multiple layers to have their band gaps and lattice constants independently selected from those of the rest of the device.

Abstract: An insulating film (2) is formed on a semiconductor substrate (1) formed of silicon carbide. A contact hole (3) is formed in the insulating film (2) to expose a part of the upper surface of the semiconductor substrate (1). Then, nickel (Ni) (4?) is formed above the semiconductor substrate (1). Subsequently, the semiconductor substrate (1) is subjected to a heat treatment, whereby the contact portion of nickel (4?) chemically bonds with the semiconductor substrate (1) to become an alloy layer (4) of silicon carbide and nickel. Nickel (4?) on the insulating film (2) is selectively removed by etching liquid for dissolving the nickel.

Abstract: A method of fabricating a silicon integrated circuit on a glass substrate includes preparing a glass substrate; fabricating a silicon layer on the glass substrate; implanting ions into the active areas of the silicon layer; covering the silicon layer with a heat pad material; activating the ions in the silicon layer by annealing while maintaining the glass substrate at a temperature below that of the thermal stability of the glass substrate; removing the heat pad material; and completing the silicon integrated circuit.

Abstract: A process for producing a substrate is described. The process includes providing an assembly having a first layer weakly bonded to a temporary support at an interface therebetween. At least a portion of the first layer is selectively etched substantially to the interface to create an etched zone. A second layer is then bonded to un-etched portions of the first layer to cover the etched zone and to form a closed cavity. The first layer is detached from the temporary support at the weak bond by providing a raised pressure in the cavity.

Abstract: The present invention relates to an epitaxial structure having one or more structural epitaxial layers, including a gallium nitride (GaN) layer, which is deposited on a substrate, and a method of growing the epitaxial structure, wherein the structural epitaxial layers can be separated from the substrate. In general, a sacrificial epitaxial layer is deposited on the substrate between the substrate and the structural epitaxial layers, and the structural epitaxial layers are deposited on the sacrificial layer. After growth, the structural epitaxial layers are separated from the substrate by oxidizing the sacrificial layer. The structural epitaxial layers include a nucleation layer deposited on the sacrificial layer and a gallium nitride layer deposited on the nucleation layer. Optionally, the oxidation of the sacrificial layer may also oxidize the nucleation layer.

Abstract: The invention concerns a method for making thin-film CIGS which consists in: electrochemically depositing on a substrate a layer of stoichiometry close to CuInSe2; then rapidly annealing said layer from a light source with pulses of sufficient power to recrystallize CIS. Advantageously, the electrodeposited elements are premixed. Thus, after the deposition step, a homogeneous matrix is obtained which can support sudden temperature increases during the rapid annealing.

Abstract: A method of depositing a low dielectric constant film on a substrate and post-treating the low dielectric constant film is provided. The post-treatment includes rapidly heating the low dielectric constant film to a desired high temperature and then rapidly cooling the low dielectric constant film such that the low dielectric constant film is exposed to the desired high temperature for about five seconds or less. In one aspect, the post-treatment also includes exposing the low dielectric constant film to an electron beam treatment and/or UV radiation.

Abstract: Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses a SSOI substrate fabrication process comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is the two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.

Abstract: A method for processing integrated circuit devices. The method includes providing a monitor wafer, which comprising a silicon material. The method introduces a plurality of particles within a depth of the silicon material. The plurality of particles have a reduced activation energy within the silicon material. The method subjects the monitor wafer including the plurality of particles into a rapid thermal anneal process. The method includes applying the rapid thermal anneal process at a first state including a first temperature. The first temperature is within a range defined as a low temperature range, which is less than 650 Degrees Celsius. The method includes removing the monitor wafer and measuring a sheet resistivity of the monitor wafer. The method also determines the first temperature within a tolerance of less than 2 percent across the monitor wafer.

Abstract: A method of fabrication of laser gain material and utilization of such media includes the steps of introducing a transitional metal, preferably Cr2+ thin film of controllable thickness on the ZnS crystal facets after crystal growth by means of pulse laser deposition or plasma sputtering, thermal annealing of the crystals for effective thermal diffusion of the dopant into the crystal volume with a temperature and exposition time providing the highest concentration of the dopant in the volume without degrading laser performance due to scattering and concentration quenching, and formation of a microchip laser either by means of direct deposition of mirrors on flat and parallel polished facets of a thin Cr:ZnS wafer or by relying on the internal reflectance of such facets.

Abstract: A germanium substrate is positioned in a process chamber. A plasma is generated from a treatment gas that includes a flow of a hydrogen-containing gas. The plasma is provided to the process chamber to react with GeO2 in the germanium substrate.

Abstract: An apparatus of manufacturing a semiconductor device is disclosed which comprises at least one heat/light source opposing at least one major surface of a to-be-processed substrate, the heat/light source emitting light rays with a heating function onto the major surface of the to-be-processed substrate, and at least one light intensity adjusting member interposed between the heat/light source and the to-be-processed substrate, the light intensity adjusting member being made of a material which can pass therethrough the light rays, the light intensity adjusting member adjusting, to a substantially predetermined value, an intensity of the light rays at the major surface of the to-be-processed substrate.

Abstract: A method for preparing a semiconductor wafer wherein rapid thermal annealing is conducted to smooth a free surface of a superficial zone that is supported by the wafer. The improvement includes treating the superficial zone before conducting the rapid thermal annealing to prevent pitting in the superficial zone during the rapid thermal annealing.

Abstract: A method of manufacturing a compound semiconductor includes the steps of forming a layered structure of dielectric layers including oxygen or sulfur, and an inter layer formed between the dielectric layers, including rare earth transition metal that is highly reactive to oxygen and sulfur, and heating the layered structure. As a result of the chemical reaction and diffusion of elements, one can change a heated portion of the layered structure to a semiconductor or an insulator, depending on the temperature to which the portion is heated.

Abstract: A process of heat-treating II-VI compound semiconductors reduces the electrical resistivity without the decrease in crystallinity resulting from the increase in dislocation density. The process comprises the following steps:(a) placing at least one II-VI compound semiconductor in contact with aluminum in a heat-treating chamber having the inside surface formed by at least one material selected from the group consisting of pyrolytic born nitride, hexagonal-system boron nitride, sapphire, alumina, aluminum nitride, and polycrystalline diamond; and (b) heat-treating the II-VI compound semiconductor or semiconductors in a gaseous atmosphere containing the group II element constituting part of the II-VI compound semiconductor or semiconductors. A II-VI compound semiconductor is heat-treated by the foregoing process. An apparatus for heat-treating II-VI compound semiconductors comprises components for performing the foregoing process.

Abstract: Method and structure for optimizing dual damascene patterning with polymeric dielectric materials are disclosed. Certain embodiments of the invention comprise polymeric sacrificial light absorbing materials (“polymer SLAM”) functionalized to have a controllable solubility switch wherein such polymeric materials have substantially the same etch rate as conventionally utilized polymeric dielectric materials, and subsequent to chemical modification of solubility-modifying protecting groups comprising the SLAM materials by thermal treatment or in-situ generation of an acid, such SLAM materials become soluble in weak bases, such as those conventionally utilized to remove materials in lithography treatments.

Abstract: A method of heat-treating a nitride compound semiconductor layer, comprising heating a nitride compound semiconductor layer doped with a p-type impurity at a temperature that is at least 200° C. but less than 400° C. for at least 100 minutes.

Abstract: A spacer layer is formed on a single-crystal substrate and an epitaxially grown layer composed of a group III-V compound semiconductor layer containing a nitride or the like is further formed on the spacer layer. The epitaxially grown layer is adhered to a recipient substrate. The back surface of the single-crystal substrate is irradiated with a light beam such as a laser beam or a bright line spectrum from a mercury vapor lamp such that the epitaxially grown layer and the single-crystal substrate are separated from each other. Since the forbidden band of the spacer layer is smaller than that of the single-crystal substrate, it is possible to separate the thin semiconductor layer from the substrate by decomposing or fusing the spacer layer, while suppressing the occurrence of a crystal defect or a crack in the epitaxially grown layer.

Abstract: A method of fabricating relaxed SiGe buffer layers with low threading dislocation densities on silicon-on-insulator (SOI) substrates is provided. The relaxed SiGe buffer layers are fabricated by the epitaxial deposition of a defect-free Stranski-Krastanov Ge or SiGe islands on a surface of the SOI substrate; the capping and planarizing of the islands with a Si or Si-rich SiGe layer, and the annealing of the structure at elevated temperatures until intermixing and thereby formation of a relaxed SiGe layer on the insulating layer (i.e., buried oxide layer) of the initial SOI wafer is achieved. The present invention is also directed to semiconductor structures, devices and integrated circuits which include at least the relaxed SiGe buffer layer mentioned above.

Abstract: A method of forming a programmable conductor memory cell array is disclosed wherein metal and chalcogenide glass are co-sputtered to fill an array of cell vias in a prepared substrate. The prepared substrate is heated above room temperature before the metal and chalcogenide glass film is deposited, and the heating is maintained throughout the deposition. The resulting metal/chalcogenide glass film has good homogeneity, a desired ratio of components, and has a regular surface.

Abstract: A method of fabricating an annealed wafer of high quality by forming a defect-free active region of a device and controlling an irregular resistivity characteristic. The method includes a first annealing step of pre-heating a silicon wafer at a temperature of about 500° C. in a furnace in an ambience of a gas selected from the group consisting of Ar, N2 and an inert gas including Ar and N2; a second annealing step of changing the ambience of the gas into a 100% H2 gas ambience, increasing the temperature to 850° C.-1,150° C., and carrying out annealing for about an hour by maintaining the increased temperature; a third annealing step of changing the ambience of the gas into a 100% Ar gas ambience, increasing the temperature to about 1,200° C., and carrying out annealing for about an hour while the temperature of about 1,200° C. is maintained; and a temperature dropping step of decreasing the temperature in the furnace below about 500° C.