Abstract: A process for producing a semiconductor emitting device of group III nitride semiconductor having a crystal layer (Al.sub.x Ga.sub.1-x).sub.1-y In.sub.y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1) includes; a step of forming at least one pn-junction or pin-junction and a crystal layer (Al.sub.x Ga.sub.1-x).sub.1-y In.sub.y N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1) to which a group II element is added; and a step of forming electrodes on the crystal layer. The process further includes an electric-field-assisted annealing treatment in which the pn-junction or pin-junction is heated to the predetermined temperature range while forming and maintaining an electric field across the pn-junction or pin-junction for at least partial time period of the predetermined temperature range via the electrodes.

Abstract: A process for synthesizing wide band gap materials, specifically, GaN, employs plasma-assisted and thermal nitridation with NH.sub.3 to convert GaAs to GaN. Thermal assisted nitridation with NH.sub.3 can be employed for forming layers of substantial thickness (on the order of 1 micron) of cubic and hexagonal GaN on a GaAs substrate. Plasma-assisted nitridation of NH.sub.3 results in formation of predominantly cubic GaN, a form particularly useful in optoelectronic devices. Preferably, very thin GaAs membranes are employed to permit formation thereon of GaN layers of any desired thickness without concern for critical thickness constraints. The thin membranes are preferably formed either with an epitaxial bonding technique, or by undercut etching.

Abstract: An improved gallium arsenide anneal boat and method for annealing comprises a slot structure for holding a wafer-stack of first and second GaAs wafers and a silicon wafer in the slot structure prior to annealing. The silicon wafer is tightly held in a central slot to maintain a vertical position and the GaAs wafers are loosely held in outside slots to avoid the formation of slip lines. The GaAs wafers slightly adhere to the silicon wafer to maintain a vertical position to avoid bending. Additionally, the wafer-stacks are separated by more than about 1.25 inches and processed in arsine gas at about 1 atm. pressure to avoid hazing.

Abstract: Known MBE methods of heat-treating semiconductor crystal of a group II-group VI compound for crystal growth are accompanied by a problem of releasing the component elements during the heat-treatment to produce a coarse crystal surface that adversely affects the subsequent crystal growth steps. According to the invention, this problem is eliminated by irradiating a substrate of a group II-group VI compound, specifically ZnSe, with Zn beams and Se beams depending on the vapor pressures of the elements between the respective starting points and the respective terminating points to compensate the released Zn and Se so that consequently no oxide film is formed on the ZnSe substrate when the heat-treatment is completed to produce a plane crystal surface that is free from coarseness.