Compound Semiconductor Patents (Class 438/796)
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Patent number: 6812039Abstract: Disclosed is a method for producing a magnetic tunnel contact. A metal layer is disposed on a first ferromagnetic layer (1) and is oxidised for producing an insulation layer (3). A second ferromagnetic layer (2) is produced on the insulation layer (3), whereby oxidation of the metal layer is supported by UV-light.Type: GrantFiled: February 5, 2002Date of Patent: November 2, 2004Assignee: Forschungszentrum Julich GmbHInventors: Hermann Kohlstedt, Peter Rottländer
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Patent number: 6797595Abstract: A method of heat-treating a nitride compound semiconductor layer, comprising heating a nitride compound semiconductor layer doped with a p-type impurity at a temperature that is at least 200° C. but less than 400° C. for at least 100 minutes.Type: GrantFiled: January 24, 2003Date of Patent: September 28, 2004Assignee: Sony CorporationInventor: Motonobu Takeya
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Patent number: 6797532Abstract: A light emitting layer made of a group III-V nitride semiconductor is formed between a first semiconductor layer made of an n-type group III-V nitride semiconductor and a second semiconductor layer made of a p-type group III-V nitride semiconductor. In side portions of the second semiconductor layer, oxidized regions are formed through the oxidization of the second semiconductor layer itself so as to be spaced apart from each other in the direction parallel to the plane of the light emitting layer. A p-side electrode is formed across the entire upper surface of the second semiconductor layer including the oxidized regions, and an n-side electrode is formed on one surface of the first semiconductor layer that is away from the second semiconductor layer.Type: GrantFiled: March 7, 2003Date of Patent: September 28, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Tetsuzo Ueda
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Patent number: 6780796Abstract: A method of forming a SiGe layer having a relatively high Ge content includes preparing a silicon substrate; depositing a layer of strained SiGe to a thickness of between about 100 nm to 500 nm, wherein the Ge content of the SiGe layer is equal to or greater than 20%, by molecular weight; implanting H2+ ions into the SiGe layer; irradiating the substrate and SiGe layer, to relax the SiGe layer; and depositing a layer of tensile-strained silicon on the relaxed SiGe layer to a thickness of between about 5 nm to 30 nm.Type: GrantFiled: July 22, 2003Date of Patent: August 24, 2004Assignee: Sharp Laboratories of America, Inc.Inventors: Jer-Shen Maa, Jong-Jan Lee, Douglas J. Tweet, Sheng Teng Hsu
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Publication number: 20040137761Abstract: In a method for fabricating a semiconductor device, a first semiconductor layer of aluminum gallium nitride is first formed on a substrate, and a protection film containing silicon is then formed on the first semiconductor layer in such a manner that a device-isolation region is uncovered. Thereafter, the method further includes the step of heat-treating the first semiconductor layer in an oxidizing atmosphere whose temperature is adjusted to be within a range of 950° C. or more and 1050 ° C. or less.Type: ApplicationFiled: July 17, 2003Publication date: July 15, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kaoru Inoue, Yoshito Ikeda, Katsunori Nishii, Yutaka Hirose
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Patent number: 6750158Abstract: A first semiconductor layer is formed on a mother substrate, and the mother substrate is irradiated with irradiation light from a surface opposite to the first semiconductor layer, so that a thermally decomposed layer formed by thermally decomposing the first semiconductor layer between the first semiconductor layer and the mother substrate. Then, a second semiconductor layer including an active layer is formed on the first semiconductor layer in which the thermally decomposed layer is formed.Type: GrantFiled: May 15, 2002Date of Patent: June 15, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masahiro Ogawa, Daisuke Ueda, Masahiro Ishida, Masaaki Yuri, Hirokazu Shimizu
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Patent number: 6737367Abstract: A method of formally treating at least one layer for activating foreign atoms passivated in the layer by hydrogen is provided. The at least one layer is heated, in a first time interval of less than 120 seconds, above a first temperature at which a specific sheet resistance of the at least one layer decreases. The at least one layer is heated, in a second time interval which is within the first time interval and is less than 60 seconds, to above a decomposition temperature of the layer. Charge carriers are produced in the at least one layer during at least one third time interval, by electromagnetic radiation, wherein the energy of such electromagnetic radiation is greater than an energy gap of the at least one layer.Type: GrantFiled: April 11, 2002Date of Patent: May 18, 2004Assignee: Steag RTP Systems GmbHInventors: Martin Drechsler, Arthur Pelzmann
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Patent number: 6737288Abstract: A heterojunction structure has an AlxGa1−xAs layer (0<x≦1), on which an AlyGa1−yAs layer (0≦y≦1 and y<x) is provided and having a band gap energy smaller than that of the AlxGa1−xAs layer and a valence band energy edge higher than that of the AlxGa1−xAs layer. When the AlyGa1−yAs layer is selectively etched, an Au electrode film is formed on a surface of the AlyGa1−yAs layer outside an etching region, a resist pattern is formed covering the Au electrode film and leaving exposed the etching region, and the AlyGa1−yAs layer is selectively removed by etching while irradiating with light, using an etching solution having a Fermi level higher than that of the AlyGa1−yAs layer.Type: GrantFiled: January 31, 2002Date of Patent: May 18, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Zempei Kawazu, Tetsuya Yagi
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Patent number: 6683198Abstract: A compound of formula (I) wherein X is aluminium, gallium or indium; each Y, which may be the same or different, is nitrogen or phosphorus; R1 and R2, which may be the same or different, are hydrogen, halogen or alkyl; and R3 to R7, which may be the same or different, are hydrogen or a saturated group, or R3 and R4, or R5 and R6 together represent a saturated divalent link thus completing a ring.Type: GrantFiled: February 21, 2002Date of Patent: January 27, 2004Assignee: Isis Innovation LimitedInventors: Anthony John Downs, Hans-Jörg Himmel
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Patent number: 6667252Abstract: A compound semiconductor substrate is manufactured by forming a higher-quality compound semiconductor layer having a smaller number of crystalline defects on a single-crystal substrate, and removing the single-crystal substrate without causing damage to the compound semiconductor layer. The method comprises the steps of forming the compound semiconductor layer (first, second and third compound semiconductor layers) on the single-crystal substrate (sapphire substrate) through crystal growth so as to partially have a space between the compound semiconductor layer and the single-crystal substrate; and removing the compound semiconductor layer from the sapphire substrate by irradiating the compound semiconductor layer from a side of the sapphire substrate with a laser beam passing through the single-crystal substrate and being absorbed in the compound semiconductor layer to melt an interface between the single-crystal substrate and the compound semiconductor.Type: GrantFiled: April 3, 2002Date of Patent: December 23, 2003Assignees: Sony Corporation, NEC CorporationInventors: Takao Miyajima, Shigetaka Tomiya, Akira Usui
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Patent number: 6620643Abstract: A group III nitride compound semiconductor light-emitting device provides a multiple quantum well (MQW) active layer formed on an intermediate layer. The MQW active layer may include, for example, five semiconductor layers having a thickness of approximately 500 Å. The five layers of the MQW active layer may comprise two gallium nitride (GaN) barrier layers each having a thickness of approximately 100 Å and three well layers having different emission wavelengths. The barrier layers and the well layers are stacked alternately. The three well layers may include, for example, an Al0.1In0.9N red-light-emitting well layer having a thickness of approximately 20 Å and doped with impurities (zinc (Zn) and silicon (Si)), a non-doped In0.2Ga0.8N green-light-emitting well layer having a thickness of approximately 50 Å and a non-doped In0.05Ga0.95N blue-light-emitting well layer having a thickness of approximately 30 Å, wherein the three well layers are stacked in the order given.Type: GrantFiled: August 3, 2000Date of Patent: September 16, 2003Assignee: Toyoda Gosei Co., Ltd.Inventor: Masayoshi Koike
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Publication number: 20030124877Abstract: A method of heat-treating a nitride compound semiconductor layer, comprising heating a nitride compound semiconductor layer doped with a p-type impurity at a temperature that is at least 200° C. but less than 400° C. for at least 100 minutes.Type: ApplicationFiled: December 23, 2002Publication date: July 3, 2003Inventor: Motonobu Takeya
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Patent number: 6586328Abstract: The metallization method of the invention uses an oxide-forming metal layer to improve adhesion and getter surface contamination or oxides. A high work function metal is then formed on the oxide-forming layer. An anneal is conducted to diffuse the high work function on metal through the oxide-forming layer. One or more metal cap layers may top the high work function metal to protect the high work function metal.Type: GrantFiled: June 5, 2000Date of Patent: July 1, 2003Assignee: The Board of Trustees of the University of IllinoisInventors: Ilesanmi Adesida, Ling Zhou
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Patent number: 6579779Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies in the wafer. During the heat-treatment, the front and back surfaces of the wafer are each exposed to either a nitriding gas or a non-nitriding gas. The front surface of the heat-treated wafer is then oxidized by heating in the presence of an oxygen-containing atmosphere in order to further effect the vacancy concentration profile within the wafer.Type: GrantFiled: November 2, 2000Date of Patent: June 17, 2003Assignee: MEMC Electronic Materials, Inc.Inventor: Robert J. Falster
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Patent number: 6573117Abstract: A layer comprising cobalt (Co) is formed on a p+ layer by vapor deposition, and a layer comprising gold (Au) is formed thereon. The two layers are alloyed by a heat treatment to form a light-transmitting electrode. The light-transmitting electrode therefore has reduced contact resistance and improved light transmission properties, and gives a light-emitting pattern which is stable over a long time. Furthermore, since cobalt (Co) is an element having a large work function, satisfactory ohmic properties are obtained.Type: GrantFiled: January 24, 2002Date of Patent: June 3, 2003Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiya Uemura, Naoki Shibata, Shizuyo Noiri, Masanori Murakami, Yasuo Koide, Jun Ito
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Patent number: 6573114Abstract: A LED has a thin highly resistive or insulative layer formed below an electrode pad in order to divert current flow from the region below an electrode pad, which region does not contribute to light emission, to another region which does. Consequently, better current efficiency is obtained. Further, diverting current flow from the region below the electrode pad where mechanical damages are expected deters deterioration of the region. Consequently, the LED lasts longer and is a better quality product.Type: GrantFiled: October 6, 2000Date of Patent: June 3, 2003Assignee: Toyoda Gosei Co., Ltd.Inventors: Naoki Shibata, Makoto Asai
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Publication number: 20030096509Abstract: To shift the bandgap of a quantum well microstructure, the surface of the microstructure is selectively irradiated in a pattern with ultra violet radiation to induce alteration of a near-surface region of said microstructure. Subsequently the microstructure is annealed to induce quantum well intermixing and thereby cause a bandgap shift dependent on said ultra violet radiation.Type: ApplicationFiled: November 20, 2002Publication date: May 22, 2003Inventor: Jan J. Dubowski
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Patent number: 6562701Abstract: A mask film of a material on which substantially no nitride semiconductor grows and having a plurality of openings in a stripe shape is formed on a main surface of a base substrate. Then, on the base substrate, a semiconductor layer of nitride is selectively grown through the mask film. Then, a laser beam is irradiated upon the interface between the semiconductor layer and the base substrate to separate the semiconductor layer from the base substrate, so that a nitride semiconductor substrate is formed from the semiconductor layer.Type: GrantFiled: February 5, 2002Date of Patent: May 13, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masahiro Ishida, Daisuke Ueda, Masaaki Yuri
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Patent number: 6563145Abstract: A compound collector double heterojunction bipolar transistor (CCHBT) incorporates a collector comprising two layers: a wide bandgap collector region (e.g., GaAs), and a narrow bandgap collector region (e.g., InGaP). The higher electric field is supported in the wide bandgap region, thereby increasing breakdown voltage and reducing offset voltage. At the same time, the use of wide bandgap material in the depleted portion of the collector, and a higher mobility material toward the end and outside of the depletion region, reduces series resistance as well as knee voltage.Type: GrantFiled: December 29, 1999Date of Patent: May 13, 2003Inventors: Charles E. Chang, Richard L. Pierson, Peter J. Zampardi, Peter M. Asbeck
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Patent number: 6534421Abstract: The invention grows SiO2 films over silicon at temperatures as low as room temperature and at pressures as high as 1 atmosphere. The lower temperature oxidation is made possible by creation of oxygen atoms and radicals by adding noble gas(es) along with oxidizing gas(es) and applying RF power to create plasma. The invention also fabricates silicon nitride films by flowing nitrogen containing gas(es) with noble gas(es) and applying RF power to create plasma at pressures as high as one atmosphere. In addition, the above processes can also be performed using microwave power instead of RF power to create plasma.Type: GrantFiled: August 27, 2001Date of Patent: March 18, 2003Assignee: Seiko Epson CorporationInventor: Ramesh H. Kakkad
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Patent number: 6524976Abstract: A method of heat-treating a nitride compound semiconductor layer, comprising heating a nitride compound semiconductor layer doped with a p-type impurity at a temperature that is at least 200° C. but less than 400° C. for at least 100 minutes.Type: GrantFiled: August 9, 2001Date of Patent: February 25, 2003Assignee: Sony CorporationInventor: Motonobu Takeya
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Patent number: 6506692Abstract: A method of converting a hydrophobic surface of a silicon carbide layer to a hydrophilic surface is described. That method comprises forming a silicon carbide containing layer on a substrate, then operating a PECVD reactor to generate a plasma that converts the surface of that layer from a hydrophobic surface to a hydrophilic surface. Also described is a method for making a semiconductor device that employs this technique.Type: GrantFiled: May 30, 2001Date of Patent: January 14, 2003Assignee: Intel CorporationInventor: Ebrahim Andideh
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Publication number: 20020182894Abstract: A method of converting a hydrophobic surface of a silicon carbide layer to a hydrophilic surface is described. That method comprises forming a silicon carbide containing layer on a substrate, then operating a PECVD reactor to generate a plasma that converts the surface of that layer from a hydrophobic surface to a hydrophilic surface. Also described is a method for making a semiconductor device that employs this technique.Type: ApplicationFiled: May 30, 2001Publication date: December 5, 2002Inventor: Ebrahim Andideh
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Patent number: 6465374Abstract: A semiconductor substrate is heated via exposure to ultraviolet radiation substantially in the absence of a halogen containing chemical and subsequently exposed to a halogen-containing gas in the absence of ultraviolet radiation to remove contaminants therefrom.Type: GrantFiled: January 13, 2000Date of Patent: October 15, 2002Assignee: FSI International, Inc.Inventors: Jeffery W. Butterbaugh, Brent Schwab
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Patent number: 6432847Abstract: A novel method of using lasers for generating driving energy for activating P-type compound semiconductor films and reducing the resistivity thereof. The P-type compound semiconductor films are made from III-V nitrides or II-VI group compounds doped with P-type impurity. The present invention can be carried out in the ambience of atmosphere rather than in the ambience of nitrogen gas. In addition, adjusting the power and focusing distance of a laser source, and the power density can change the time required by the activating process.Type: GrantFiled: June 1, 2000Date of Patent: August 13, 2002Assignee: Advanced Epitaxy Technology Inc.Inventors: Jian-Shihn Tsang, Wen-Chung Tsai, Tsung-Yu Chen, Chia-Hung Hsu, Wei-Chih Lai
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Publication number: 20020102761Abstract: After a Group III-V compound semiconductor layer, to which a p-type dopant has been introduced, has been formed over a substrate, the compound semiconductor layer is annealed. In the stage of heating the compound semiconductor layer, atoms, deactivating the p-type dopant, are eliminated from the compound semiconductor layer by creating a temperature gradient in the compound semiconductor layer.Type: ApplicationFiled: April 19, 2001Publication date: August 1, 2002Inventors: Yoshiaki Hasegawa, Ayumu Tsujimura, Isao Kidoguchi, Yuzaburo Ban
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Patent number: 6420283Abstract: Methods are provided for producing a compound semiconductor substrate including: a mica substrate; and a III-V group compound semiconductor layer containing nitrogen as its main component grown on the mica substrate.Type: GrantFiled: October 26, 1998Date of Patent: July 16, 2002Assignee: Sharp Kabushiki KaishaInventors: Atsushi Ogawa, Takayuki Yuasa
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Publication number: 20020084523Abstract: There is disclosed a resin sealed semiconductor device in which a heat radiation member formed integrally with a sealing resin is constituted of a clad material comprising a first material having a coefficient of linear expansion approximate to that of the sealing resin, and a second metal laminated on a surface of the first metal and having good adhesive properties to the sealing resin. There can be obtained the metallic heat radiation member which can satisfy all three conditions required for the heat radiation member at a satisfactory level, i.e., (1) heat conductivity being excellent, (2) a difference of a coefficient of linear expansion between the heat radiation member and a sealing resin being small, and (3) adhesive properties to the sealing resin being good.Type: ApplicationFiled: November 2, 2001Publication date: July 4, 2002Applicant: CITIZEN WATCH CO., LTDInventors: Kazuaki Sorimachi, Masayoshi Kikuchi
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Publication number: 20020068468Abstract: The present invention provides a method of manufacturing a low resistivity p-type compound semiconductor material over a substrate. The method of the present invention comprises the steps of forming a p-type impurity doped compound semiconductor layer on the substrate by either HVPE, OMVPE or MBE and applying a microwave treatment over the p-type impurity doped compound semiconductor layer for a period of time. The high resistivity p-type impurity doped compound semiconductor layer is converted into a low resistivity p-type compound semiconductor material according to the present invention.Type: ApplicationFiled: February 3, 2000Publication date: June 6, 2002Inventors: Tzong-Liang Tsai, Chung-Ying Chang
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Publication number: 20020055274Abstract: A method of heat-treating a nitride compound semiconductor layer, comprising heating a nitride compound semiconductor layer doped with a p-type impurity at a temperature that is at least 200° C. but less than 400° C. for at least 100 minutes.Type: ApplicationFiled: August 9, 2001Publication date: May 9, 2002Inventor: Motonobu Takeya
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Patent number: 6313016Abstract: A method for producing relaxed epitaxy layers on a semiconductor substrate by an epitaxy process, particularly molecular beam epitaxy, with a hydrogen source, wherein the following steps occur during an in situ process sequence: a hydrogen-containing intermediate layer is deposited on the substrate surface or diffused into the substrate near the surface; a strained epitaxy layer is grown on this intermediate layer; and the epitaxial layer subsequently is relaxed by a temperature treatment. A preferred layer sequence formed according to the above method includes a substrate of silicon with a hydrogen-containing intermediate layer that is deposited thereon or diffused into the substrate surface; a relaxed Si1−xGex epitaxial layer with a germanium concentration of x=0.1 to 0.3 as a first buffer layer; a hydrogen-containing intermediate layer deposited on or diffused into an outer surface of the first buffer layer; a Si1−xGex relaxed epitaxy layer with a germanium concentration of x=0.Type: GrantFiled: December 22, 1999Date of Patent: November 6, 2001Assignee: DaimlerChrysler AGInventors: Horst Kibbel, Jessica Kuchenbecker
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Patent number: 6303404Abstract: Disclosed is a method for fabricating a white LED which comprises, as a single active layer, an InGaN thin film which enables emission of white light. The InGaN thin film is constructed by taking advantage of the spinodal decomposition of the ternary compound and rapid thermal annealing. When growing the InGaN thin film on an n-type GaN formed on a sappier substrate under a growth condition, the thin film undergoes spinodal decomposition into two phases which show photoluminescence of a wavelength range from violet to blue and from green to blue, respectively, after which the surface of the thin film is thermally stabilized by rapid thermal annealing and the photoluminescence of the In-deficient phase is improved, so as to give intensive white photoluminescence to the InGaN single active layer. The LED which recruits such a single active InGaN thin film is superb in light emission efficiency and can be fabricated in a significantly reduced process steps.Type: GrantFiled: May 28, 1999Date of Patent: October 16, 2001Inventors: Yong Tae Moon, Dong Joon Kim, Keun Man Song, Seong Ju Park
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Patent number: 6258614Abstract: A device with a low resistance zone having confinement, superior reproducibility, and a very high yield comprises a plurality of semiconductor layers, wherein layer resistivity is changed by annealing. The semiconductor layers include a resistance zone having a high activation coefficient of acceptor impurities and a resistance region having a low activation coefficient of acceptor impurities. The activation coefficient is controlled by irradiation with laser light. In addition, laser light is irradiated and absorbed into the semiconductor layers in one part of, or the entire, semiconductor layers, such that layer resistivity in the irradiated regions is changed by annealing resulting from such irradiation.Type: GrantFiled: November 26, 1997Date of Patent: July 10, 2001Assignee: LumiLeds Lighting, U.S., LLCInventor: Yawara Kaneko
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Patent number: 6255185Abstract: A method of controlling the resistance and improving the low temperature tolerance of a polysilicon resistor is provided. The method of the present invention employs a second annealing step after one of the high temperature (about 800° C. or above) device activation anneals. That is, the second annealing step can be used after source/drain activation, emitter activation or silicide formation. In accordance with the present invention, if a low temperature second annealing step below about 800° C. is performed after the high temperature device activation anneal, the resistance of the resistor increases, whereas when the second annealing temperature is higher than about 800° C., the resistance of the resistor decreases.Type: GrantFiled: May 19, 1999Date of Patent: July 3, 2001Assignee: International Business Machines CorporationInventors: Douglas Duane Coolbaugh, Glenn Robert Miller, Sophia Maumovna Ratenberg
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Patent number: 6159873Abstract: In a RTP (rapid Thermal Processing) of a large-diameter semiconductor wafer using a hot-wall type heating furnace, the temperature distribution of the wafer surface is made uniform by means of preliminarily heating a thermal storage plate(s) to a heat-treating temperature, and, then positioning the wafer between a pair of the thermal storage plates or in the direct proximity of a thermal storage plate. The wafer may be brought into contact with the thermal storage plate. The wafer is thus heated rapidly heated to the heat treating temperature.Type: GrantFiled: March 29, 1996Date of Patent: December 12, 2000Assignee: F.T.L. Co., Ltd.Inventor: Mikio Takagi
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Patent number: 6117700Abstract: First, n-type contact layer of GaN, n-type cladding layer of AlGaN, active layer of InGaN, first Mg-doped layer of AlGaN and second Mg-doped layer of GaN are grown in this order over a sapphire substrate. Thereafter, the substrate, including the second Mg-doped layer, is exposed to nitrogen plasma for about 40 minutes. As a result, Mg, which has been introduced into the first and second Mg-doped layers, is activated as an acceptor. Thus, p-type cladding layer and p-type contact layer with low resistance and excellent crystallinity can be formed out of the first and second Mg-doped layers, respectively.Type: GrantFiled: September 2, 1999Date of Patent: September 12, 2000Assignee: Matsushita Electronics CorporationInventors: Kenji Orita, Masahiro Ishida, Shinji Nakamura, Masaaki Yuri
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Patent number: 6106148Abstract: This invention presents an automatic calibration system and method for calibration of a substrate temperature sensor in a thermal processing equipment, such as a rapid thermal processing system. The calibration system includes a temperature-sensitive probe associated with the substrate temperature sensor to calibrate the substrate temperature sensor and an actuator to position the temperature-sensitive probe relative to the substrate during a calibration cycle. The actuator and temperature-sensitive probe of the automatic calibration system can be incorporated into the thermal processing equipment in order to maintain the thermal processing equipment cleanliness and integrity during a calibration cycle, and to allow rapid automated calibration. In the preferred embodiment of this invention, the temperature-sensitive probe and its actuator are implemented in the gas showerhead assembly of a rapid thermal processing system.Type: GrantFiled: June 25, 1999Date of Patent: August 22, 2000Assignee: CVC, Inc.Inventors: Mehrdad M. Moslehi, Yong Jin Lee
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Patent number: 6107168Abstract: In the manufacture of semiconductor components, a SiC single crystal is exposed, during storage or transport between two process steps, to an oxygen-containing gas atmosphere, for example air. In order to prevent an oxide coating from forming on the SiC surface of the SiC single crystal, a carbon coating which does not react chemically with oxygen, preferably a graphite coating, is produced on said SiC surface.Type: GrantFiled: December 18, 1997Date of Patent: August 22, 2000Assignee: Siemens AktiengesellschaftInventor: Roland Rupp
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Patent number: 6083801Abstract: The nickel element is provided selectively, i.e., adjacent to part of the surface of an amorphous silicon film in a long and narrow opening. The amorphous silicon film is irradiated with linear infrared light beams emitted from respective linear infrared lamps while scanned with the linear beams perpendicularly to the longitudinal direction of the opening. The longitudinal direction of the linear beams are set coincident with that of the opening. The infrared light beams are absorbed by the silicon film mainly as thermal energy, whereby a negative temperature gradient is formed in the silicon film. The temperature gradient moves as the lamps are moved for the scanning. The direction of the negative temperature gradient is set coincident with the lamp movement direction and an intended crystal growth direction, which enables crystal growth to proceed parallel with a substrate uniformly over a long distance.Type: GrantFiled: February 10, 1998Date of Patent: July 4, 2000Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Hisashi Ohtani
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Patent number: 6071795Abstract: A method of separating a thin film of GaN epitaxially grown on a sapphire substrate. The thin film is bonded to an acceptor substrate, and the sapphire substrate is laser irradiated with a scanned beam at a wavelength at which sapphire is transparent but the GaN is strongly absorbing, e.g., 248 nm. After the laser irradiation, the sample is heated above the melting point of gallium, i.e., above 30.degree. C., and the acceptor substrate and attached GaN thin film are removed from the sapphire growth substrate. If the acceptor substrate is flexible, the GaN thin film can be scribed along cleavage planes of the GaN, and, when the flexible substrate is bent, the GaN film cleaves on those planes. Thereby, GaN lasers and other electronic and opto-electronic devices can be formed.Type: GrantFiled: January 23, 1998Date of Patent: June 6, 2000Assignee: The Regents of the University of CaliforniaInventors: Nathan W. Cheung, Timothy D. Sands, William S. Wong
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Patent number: 6036772Abstract: A method for making a semiconductor device comprises: depositing at least one Group II-VI compound semiconductor layer comprising at least one Group II element selected from the group consisting of zinc, magnesium, manganese, beryllium, cadmium and mercury and at least one Group VI element selected from the group consisting of oxygen, sulfur, selenium and tellurium onto a Group III-V compound semiconductor layer comprising at least one Group III element selected from the group consisting of gallium, aluminum, boron and indium and at least one Group V element selected from the group consisting of nitrogen, phosphorus, arsenic, antimony and bismuth; whereinbefore depositing the Group II-VI compound semiconductor layer, a particle beam composed of at least one Group II element selected from the group consisting of zinc, magnesium, beryllium, cadmium and mercury is radiated onto the Group III-V compound semiconductor layer in a dose of 8.times.10.sup.-4 Torr.multidot.sec or more.Type: GrantFiled: December 29, 1997Date of Patent: March 14, 2000Assignee: Sony CorporationInventors: Tomonori Hino, Satoshi Taniguchi, Satoshi Ito
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Patent number: 6030848Abstract: A manufacturing method for high quality GaN-based light emitting devices. The method enable effective growth of an Al.sub.y Ga.sub.1-y N (0.ltoreq.y.ltoreq.1) layer on an In.sub.x Ga.sub.1- N (0.ltoreq.x.ltoreq.1) layer by CVD. While holding or increasing the temperature after growing the InGaN layer at the temperature of T0 before growing the AlGaN at the temperature of T1 (T0.ltoreq.T1) in an atmosphere including a source of group V of elements, the present invention applies an inert gas as the carrier gas which includes a source of the group V elements. Therefore, the concentration of group V elements near the surface of the InGaN layer increases and the sublimation of the InGaN layer is prevented by increasing the steam pressure of the group V elements near the surface of the InGaN layer.Type: GrantFiled: April 16, 1997Date of Patent: February 29, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Shozo Yuge, Hideto Sugawara
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Patent number: 6030894Abstract: On a main surface of a silicon substrate of one conductivity type, a diffusion layer of the opposite conductivity type is formed, and the main surface of the silicon substrate is covered by an insulator film. The insulator film is formed with a contact hole which extends to reach the diffusion layer of the opposite conductivity type. A contact plug is provided in the contact hole. The contact plug fills the contact hole and comprises a first silicon layer of the opposite conductivity type directly connected to the diffusion layer of the opposite conductivity type, a silicon-germanium alloy layer of the opposite conductivity type directly contact to the first silicon layer, and a second silicon layer of the opposite conductivity type directly contact to the silicon-germanium alloy layer. Wiring is provided on the surface of the insulator film in direct contact to the contact plug.Type: GrantFiled: July 20, 1998Date of Patent: February 29, 2000Assignee: NEC CorporationInventors: Hiromitsu Hada, Toru Tatsumi, Naoki Kasai, Hidemitsu Mori
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Patent number: 6025281Abstract: A method of passivating interface states of oxide-compound semiconductor interfaces using molecular, atomic, or isotopic species wherein said species are applied before oxide deposition in ultra-high vacuum, or during interruption of oxide deposition in ultra-high vacuum (preferentially after oxide surface coverage of a submonolayer, a monolayer, or a few monolayers), or during oxide deposition in ultra-high vacuum, or after completion of oxide deposition, or before or after any processing steps of the as deposited interface structure. In a preferred embodiment, hydrogen or deuterium atoms are applied to a Ga.sub.2 O.sub.3 --GaAs interface at some point before, during, or after oxide deposition in ultra-high vacuum, or before or after any processing steps of the as deposited interface structure, at any given and useful substrate temperature wherein the atomic species can be provided by any one of RF discharge, microwave plasma discharge, or thermal dissociation.Type: GrantFiled: December 18, 1997Date of Patent: February 15, 2000Assignee: Motorola, Inc.Inventors: Matthias Passlack, Jonathan K. Abrokwah, Sandeep Pendharkar, Stephen B. Clemens, Jimmy Z. Yu, Brian Bowers
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Patent number: 6004029Abstract: This invention presents an automatic calibration system and method for calibration of a substrate temperature sensor in a thermal processing equipment, such as a rapid thermal processing system. The calibration system includes a temperature-sensitive probe associated with the substrate temperature sensor to calibrate the substrate temperature sensor and an actuator to position the temperature-sensitive probe relative to the substrate during a calibration cycle. The actuator and temperature-sensitive probe of the automatic calibration system can be incorporated into the thermal processing equipment in order to maintain the thermal processing equipment cleanliness and integrity during a calibration cycle, and to allow rapid automated calibration. In the preferred embodiment of this invention, the temperature-sensitive probe and its actuator are implemented in the gas showerhead assembly of a rapid thermal processing system.Type: GrantFiled: July 10, 1996Date of Patent: December 21, 1999Assignee: CVC Products, Inc.Inventors: Mehrdad M. Moslehi, Yong Jin Lee
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Patent number: 5937318Abstract: A monocrystalline monolith contains a 3-D array of interconnected lattice-matched devices (which may be of one kind exclusively, or that kind in combination with one or more other kinds) performing digital, analog, image-processing, or neural-network functions, singly or in combination. Localized inclusions of lattice-matched metal and (or) insulator can exist in the monolith, but monolith-wide layers of insulator are avoided. The devices may be self-isolated, junction-isolated, or insulator-isolated, and may include but not be limited to MOSFETs, BJTs, JFETs, MFETs, CCDs, resistors, and capacitors. The monolith is fabricated in a single apparatus using a process such as MBE or sputter epitaxy executed in a continuous or quasicontinuous manner under automatic control, and supplanting hundreds of discrete steps with handling and storage steps interpolated.Type: GrantFiled: May 24, 1991Date of Patent: August 10, 1999Inventors: Raymond M. Warner, Jr., Ronald D. Schrimpf, Alfons Tuszynski
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Patent number: 5937273Abstract: A fabricating method of compound semiconductor device is proposed which has a step of varying selective growth ratio of crystal by changing either a mean free path of material gas in gas atmosphere for use in crystal growth or a thickness of a stagnant layer of the material gas, using selective growth mask having opening portion consisting of first region having a narrow width and second region having a wide width.Type: GrantFiled: December 22, 1995Date of Patent: August 10, 1999Assignee: Fujitsu LimitedInventors: Takuya Fujii, Mitsuru Ekawa, Tsuyoshi Yamamoto, Hirohiko Kobayashi
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Patent number: 5893760Abstract: A susceptor in a semiconductor wafer heat treatment apparatus holds a wafer such that the wafer is made flat at a heat treatment temperature. In particular, the susceptor is constituted by an elastic platy member which is convex upward with respect to the direction of the gravity. Therefore, when the wafer is subjected to a high-temperature heat treatment, a crystal defect in the wafer can be suppressed.Type: GrantFiled: March 26, 1997Date of Patent: April 13, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Yuichi Mikata, Akihito Yamamoto
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Patent number: 5874320Abstract: A method for forming P-type gallium nitride is disclosed in the invention. In this method, Mg--H can be completly discomposed by use of an annealing process, thereby entirely dissociating the hydrogen atoms from the gallium nitride, while the nitrogen atoms are not dissociated from the gallium nitride. Therefore, the P-type gallium nitride having high conductivity is obtained and V.sub.N gap defects created in the gallium nitride do not occur. During the annealing process, nitrogen flux is added around the gallium nitride to prevent decomposition of the gallium nitride. The above-mentioned nitrogen flux can be generated by use of RF plasma, electron cyclotron resonance (ECR) or ion beam. Furthermore, since a forward current is provided across the P--N junction of the gallium nitride, the Mg--H inside the magnesium-doped gallium nitride can be decomposed by just increasing the temperature to 175.degree. C.Type: GrantFiled: July 11, 1997Date of Patent: February 23, 1999Assignee: Industrial Technology Research InstituteInventors: Kwang-Kuo Shih, Chao-Nien Huang, Chin-Yuan Chen, Biing-Jye Lee, Ming-Huang Hong
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Patent number: 5834325Abstract: A light emitting device having higher blue luminance is obtained. A gallium nitride compound layer is formed on a GaAs substrate, and thereafter the GaAs substrate is at least partially removed for forming the light emitting device. Due to the removal of the GaAs substrate, the quantity of light absorption is reduced as compared with the case of leaving the overall GaAs substrate. Thus, a light emitting device having high blue luminance is obtained.Type: GrantFiled: May 28, 1997Date of Patent: November 10, 1998Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Mitsuru Shimazu, Yoshiki Miura