Compound Semiconductor Patents (Class 438/796)
  • Patent number: 8231848
    Abstract: Ternary and quaternary Chalcopyrite CuInxGa1-xSySe2-y (CIGS, where 0?x and y?1) nanoparticles were synthesized from molecular single source precursors (SSPs) by a one-pot reaction in a high boiling solvent using salt(s) (i.e. NaCl as by-product) as heat transfer agent via conventional convective heating method. The nanoparticles sizes were 1.8 nm to 5.2 nm as reaction temperatures were varied from 150° C. to 190° C. with very high-yield. Tunable nanoparticle size is achieved through manipulation of reaction temperature, reaction time, and precursor concentrations. In addition, the method developed in this study was scalable to achieve ultra-large quantities production of tetragonal and quaternary Chalcopyrite CIGS nanoparticles.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: July 31, 2012
    Assignee: Sun Harmonics Ltd
    Inventors: Yuhang Ren, Chivin Sun, Kai Shum
  • Patent number: 8232552
    Abstract: This invention provides an amorphous oxide semiconductor thin film, which is insoluble in a phosphoric acid-based etching solution and is soluble in an oxalic acid-based etching solution by optimizing the amounts of indium, tin, and zinc, a method of producing the amorphous oxide semiconductor thin film, etc. An image display device (1) comprises a glass substrate (10), a liquid crystal (40) as a light control element, a bottom gate-type thin film transistor (1) for driving the liquid crystal (40), a pixel electrode (30), and an opposing electrode (50). The amorphous oxide semiconductor thin film (2) in the bottom gate-type thin film transistor (1) has a carrier density of less than 10+18 cm?3, is insoluble in a phosphoric acid-based etching liquid, and is soluble in an oxalic acid-based etching liquid.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: July 31, 2012
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Koki Yano, Kazuyoshi Inoue
  • Patent number: 8192648
    Abstract: A method of forming a material from a source material including the following steps of grinding the source material to get powders if the source material is not already in the form of powders; sintering the powders with at least one compression step and one thermal processing step; and purifying the material with a gas flow, the gas flow passing through the porosity channels of the material.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: June 5, 2012
    Assignee: S'Tile
    Inventor: Alain Straboni
  • Patent number: 8183131
    Abstract: A method of cutting an object which can accurately cut the object is provided. An object to be processed 1 such as a silicon wafer is irradiated with laser light L while a light-converging point P is positioned therewithin, so as to form a modified region 7 due to multiphoton absorption within the object 1, and cause the modified region 7 to form a starting point region for cutting 8 shifted from the center line CL of the thickness of the object 1 toward the front face 3 of the object 1 along a line along which the object should be cut. Subsequently, the object 1 is pressed from the rear face 21 side thereof. This can generate a fracture from the starting point region for cutting 8 acting as a start point, thereby accurately cutting the object 1 along the line along which the object should be cut.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: May 22, 2012
    Assignee: Hamamatsu Photonics K. K.
    Inventors: Fumitsugu Fukuyo, Kenshi Fukumitsu
  • Publication number: 20120122321
    Abstract: thermal management for large scale processing of CIS and/or CIGS based thin film is described. The method includes providing a plurality of substrates, each of the substrates having a copper and indium composite structure. The method also includes transferring the plurality of substrates into a furnace, each of the plurality of substrates provided in a vertical orientation with respect to a direction of gravity, the plurality of substrates being defined by a number N, where N is greater than 5. The method further includes introducing a gaseous species including a selenide species and a carrier gas into the furnace and transferring thermal energy into the furnace to increase a temperature from a first temperature to a second temperature, to at least initiate formation of a copper indium diselenide film.
    Type: Application
    Filed: November 9, 2011
    Publication date: May 17, 2012
    Applicant: Stion Corporation
    Inventor: Robert D. Wieting
  • Patent number: 8173537
    Abstract: Stability of an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric layer is critical for successful integration. UV-resistant diffusion barrier layers are formed by depositing the layer in a hydrogen-starved environment. Diffusion barrier layers can be made more resistant to UV radiation by thermal, plasma, or UV treatment during or after deposition. Lowering the modulus of the diffusion barrier layer can also improve the resistance to UV radiation.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: May 8, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Kaushik Chattopadhyay, Keith Fox, Tom Mountsier, Hui-Jung Wu, Bart van Schravendijk, Kimberly Branshaw
  • Publication number: 20120100691
    Abstract: The invention relates to a process for fabricating a heterostructure. This process comprises heating an intermediate heterostructure. The intermediate heterostructure comprises a crystalline strain relaxation layer interposed directly between a first substrate and a strained layer of crystalline semiconductor material. The process further comprises causing plastic deformation of the crystalline strain relaxation layer and elastic deformation of the strained layer of crystalline semiconductor material to at least partially relax the strained layer of crystalline semiconductor material.
    Type: Application
    Filed: December 30, 2011
    Publication date: April 26, 2012
    Applicant: Soitec
    Inventor: Bruce Faure
  • Patent number: 8148192
    Abstract: The present invention provides improved devices such as transparent solar cells. This patent teaches a particularly efficient method of device manufacture based on incorporating the solar cell fabrication into the widely used, high temperature, Float Glass manufacture process.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: April 3, 2012
    Inventors: James P Campbell, Harry R Campbell, Ann B Campbell, Joel F Farber
  • Publication number: 20120068188
    Abstract: A GaN sample in a sealed enclosure is heated very fast to a high temperature above the point where GaN is thermodynamically stable and is then cooled down very fast to a temperature where it is thermodynamically stable. The time of the GaN exposure to a high temperature range above its thermodynamic stability is sufficiently short, in a range of few seconds, to prevent the GaN from decomposing. This heating and cooling cycle is repeated multiple times without removing the sample from the enclosure. As a result, by accumulating the exposure time in each cycle, the GaN sample can be exposed to a high temperature above its point of thermodynamic stability for a long time but the GaN sample integrity is maintained (i.e., the GaN doesn't decompose) due to the extremely short heating duration of each single cycle.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 22, 2012
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Boris N. Feigelson, Travis Anderson, Francis J. Kub
  • Publication number: 20120070936
    Abstract: In an annealing process, a Kesterite film is provided on a substrate. The Kesterite film and the substrate are generally planar, have an interface, and have a substrate exterior side and a Kesterite exterior side. An additional step includes locating the cap adjacent the Kesterite exterior side. A further step includes applying sufficient heat to the Kesterite film and the substrate for a sufficient time to anneal the Kesterite film. The annealing is carried out with the cap adjacent the Kesterite exterior side. In another aspect, the film is not limited to Kesterite, and the cap is employed without any precursor layer thereon. Solar cell manufacturing techniques employing the annealing techniques are also disclosed.
    Type: Application
    Filed: June 3, 2011
    Publication date: March 22, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Supratik Guha, David B. Mitzi, Teodor K. Todorov, Kejia Wang
  • Publication number: 20120070968
    Abstract: The present invention provides a method of processing a substrate and a method of manufacturing a silicon carbide (SiC) substrate in which, when annealing processing is performed on a crystalline silicon carbide (SiC) substrate, the occurrence of surface roughness is suppressed. A substrate processing method according to an embodiment of the present invention includes a step of performing plasma irradiation on a single crystal silicon carbide (SiC) substrate (1) and a step of performing high temperature heating processing on the single crystal silicon carbide (SiC) substrate (1) in which the plasma irradiation is performed.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 22, 2012
    Applicant: CANON ANELVA CORPORATION
    Inventors: Masami Shibagaki, Masataka Satoh, Takahiro Sugimoto, Akemi Satoh
  • Patent number: 8133821
    Abstract: A method includes forming an insulating film over a substrate by introducing a cyclic siloxane compound having a cyclic siloxane as a skeleton and having at least one volatile hydrocarbon group bonded to a side chain, and a silicon-containing compound into a plasma, and converting the insulating film to a porous insulating film by adding energy to the insulating film. The silicon-containing compound is decomposed using less energy as compared with the skeleton of the cyclic siloxane compound, the volatile hydrocarbon group, and the bond between the cyclic siloxane compound and the volatile hydrocarbon group.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: March 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Fuminori Ito, Yoshihiro Hayashi
  • Patent number: 8124510
    Abstract: A method of manufacturing a silicon carbide semiconductor device is disclosed in which a trench and a hole are controlled to have a predetermined configuration even if the silicon carbide semiconductor device is subjected to a heat treatment at a temperature of not lower than 1,500° C. A heat treatment step(s) of a method of the invention includes a step of heat treatment in an argon atmosphere at a temperature in a range of 1,600° C. to 1,800° C. under a pressure of at most 10 Torr for a time duration in a range of 0.1 min to 10 min to evaporate silicon atoms from a surface of the silicon carbide semiconductor substrate or the silicon carbide epitaxial layer and to obtain a silicon carbide surface with a carbon atom concentration of at least 95%.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: February 28, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yasuyuki Kawada, Takeshi Tawara
  • Patent number: 8124522
    Abstract: Provided are methods of stabilizing an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric layer. Methods include modulating the optical properties reduces the effects of UV radiation on the dielectric diffusion barrier layer. The dielectric diffusion barrier can be made to absorb less UV radiation. A dielectric layer with UV absorbing properties may also be added on top of the diffusion barrier layer so less UV is transmitted. Both methods result in reduced interaction between UV radiation and the dielectric diffusion barrier.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: February 28, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Hui-Jung Wu, Kimberly Shafi, Kaushik Chattopadhyay, Keith Fox, Tom Mountsier, Girish Dixit, Bart van Schravendijk, Elizabeth Apen
  • Patent number: 8119532
    Abstract: A dual zone plasma processing chamber is provided. The plasma processing chamber includes a first substrate support having a first support surface adapted to support a first substrate within the processing chamber and a second substrate support having a second support surface adapted to support a second substrate within the processing chamber. One or more gas sources in fluid communication with one or more gas distribution members supply process gas to a first zone adjacent to the first substrate support and a second zone adjacent to the second substrate support. A radio-frequency (RF) antenna adapted to inductively couple RF energy into the interior of the processing chamber and energize the process gas into a plasma state in the first and second zones. The antenna is located between the first substrate support and the second substrate support.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: February 21, 2012
    Assignee: Lam Research Corporation
    Inventor: Sanket P. Sant
  • Patent number: 8114693
    Abstract: A solid state energy conversion device and method of making is disclosed for converting energy between electromagnetic and electrical energy. The solid state energy conversion device comprises a wide bandgap semiconductor material having a first doped region. A thermal energy beam is directed onto the first doped region of the wide bandgap semiconductor material in the presence of a doping gas for converting a portion of the first doped region into a second doped region in the wide bandgap semiconductor material. A first and a second Ohmic contact are applied to the first and the second doped regions of the wide bandgap semiconductor material. In one embodiment, the solid state energy conversion device operates as a light emitting device to produce electromagnetic radiation upon the application of electrical power to the first and second Ohmic contacts.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: February 14, 2012
    Assignee: Partial Assignment University of Central Florida
    Inventors: Nathaniel R. Quick, Aravinda Kar
  • Patent number: 8105925
    Abstract: An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the semiconductor layer (22). A dielectric layer (24) is formed on the semiconductor layer (22). A sealing layer (28) is formed on the dielectric layer (24) and exposed to an oxygen plasma (36). A gate electrode (482) is formed on the dielectric layer (24) between the source-drain electrodes (421, 422). The dielectric layer (24) preferably comprises gallium-oxide (25) and/or gadolinium-gallium oxide (26, 27), and the oxygen plasma (36) is preferably an inductively coupled plasma. A further sealing layer (44) of, for example, silicon nitride is desirably provided above the sealing layer (28).
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: January 31, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Publication number: 20110294306
    Abstract: A method for forming a multi-material thin film includes providing a multi-material donor substrate comprising single crystal silicon and an overlying film comprising GaN or SiC. Energetic particles are introduced through a surface of the multi-material donor substrate to a selected depth within the single crystal silicon. The method includes providing energy to a selected region of the donor substrate to initiate a controlled cleaving action in the donor substrate. Then, a cleaving action is made using a propagating cleave front to free a multi-material film from a remaining portion of the donor substrate, the multi-material film comprising single crystal silicon and the overlying film.
    Type: Application
    Filed: August 10, 2011
    Publication date: December 1, 2011
    Applicant: Silicon Genesis Corporation
    Inventors: Francois J. Henley, Nathan W. Cheung
  • Patent number: 8058147
    Abstract: The invention relates to a method for producing semiconductor components, wherein a layer composite (6) containing a semiconductor material is formed on a growth substrate (1), a flexible carrier layer is applied to the layer composite (6), the flexible carrier layer is cured to form a self-supporting carrier layer (2), and the growth substrate (1) is stripped away. As an alternative, the carrier layer (2) may have a base layer (2b) and an adhesion layer (2a) adhering on the layer composite.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: November 15, 2011
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Siegfried Herrmann, Berthold Hahn
  • Publication number: 20110248386
    Abstract: The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps.
    Type: Application
    Filed: June 20, 2011
    Publication date: October 13, 2011
    Applicant: Wostec, Inc.
    Inventors: Valery K. Smirnov, Dmitry S. Kibalov
  • Publication number: 20110227042
    Abstract: There is provided a method of producing a semiconductor wafer by thermally processing a base water having a portion to be thermally processed that is to be thermally processed. The method comprises a step of providing, on the base wafer, a portion to be heated that generates heat through absorption of an electromagnetic wave and selectively heats the portion to be thermally processed, a step of applying an electromagnetic wave to the base wafer, and a step of lowering the lattice defect density of the portion to he thermally processed, by means of the heat generated by the portion to be heated through the absorption of the electromagnetic wave.
    Type: Application
    Filed: November 26, 2009
    Publication date: September 22, 2011
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Tomoyuki Takada, Masahiko Hata, Hisashi Yamada
  • Patent number: 8022444
    Abstract: Provided are a biosensor with a silicon nanowire and a method of manufacturing the same, and more particularly, a biosensor with a silicon nanowire including a defect region formed by irradiation of an electron beam, and a method of manufacturing the same. The biosensor includes: a silicon substrate; a source region disposed on the silicon substrate; a drain region disposed on the silicon substrate; and a silicon nanowire disposed on the source region and the drain region, and having a defect region formed by irradiation of an electron beam. Therefore, by irradiating a certain region of a high-concentration doped silicon nanowire with an electron beam to lower electron mobility in the certain region, it is possible to maintain a low contact resistance between the silicon nanowire and a metal electrode and to lower operation current of a biomaterial detection part, thereby improving sensitivity of the biosensor.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: September 20, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Tae Youb Kim, Nae Man Park, Han Young Yu, Moon Gyu Jang, Jong Heon Yang
  • Patent number: 8017528
    Abstract: A thermal cycle includes: increasing a temperature from an initial temperature to a temperature T1 at an arbitrary rate R1 (° C./sec); holding the temperature at the temperature T1 for an arbitrary period t1 (sec); increasing the temperature from the temperature T1 to a temperature T2 at a rate R2 (° C./sec) of 1.0×107 (° C./sec) or less; and holding the temperature at the temperature T2 for a period t2 (sec) of 50 msec or less. The thermal cycle thereafter includes: decreasing the temperature from the temperature T2 to the temperature T1 at a rate R1? (° C./sec) of 1.0×107 (° C./sec) or less; holding the temperature T1 for an arbitrary period t3 (sec); and decreasing the temperature from the temperature T1 to a final temperature at an arbitrary rate R2? (° C./sec). Such a thermal cycle is successively repeated in a plurality of iterations.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: September 13, 2011
    Assignee: Panasonic Corporation
    Inventors: Kenji Yoneda, Kazuma Takahashi
  • Publication number: 20110201191
    Abstract: A method for nondestructive laser lift-off of GaN from sapphire substrates utilizing a solid-state laser is disclosed in the present invention, wherein, a solid-state laser is used as the laser source, and a small laser-spot with a circumference of 3 to 1000 micrometers and a distance of two farthest corners or a longest diameter of no more than 400 micrometers is used for laser scanning point-by-point and line-by-line, wherein the energy in the small laser-spot is distributed such that the energy in the center of the laser-spot is the strongest and is gradually reduced toward the periphery. According to the present invention, a nondestructive laser lift-off with a small laser-spot is achieved, and a scanning mode of the laser lift-off is improved, thereby a lift-off method without the need of aiming is achieved.
    Type: Application
    Filed: April 21, 2009
    Publication date: August 18, 2011
    Inventors: Guoyi Zhang, Yongjian Sun, Xiangning Kang, Zhizhong Chen, Zhijian Yang, Xinrong Yang
  • Publication number: 20110195583
    Abstract: A layer of wavelength converting material is formed by supplying energy to a particle of wavelength converting material and causing the particle to contact a surface such that the energy causes the particle to adhere to the surface. In some embodiments, the wavelength converting material is a phosphor and the surface is a surface of a semiconductor light emitting device.
    Type: Application
    Filed: February 11, 2010
    Publication date: August 11, 2011
    Applicants: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventor: Jeffrey D. KMETEC
  • Patent number: 7981816
    Abstract: An impurity-activating thermal process is performed after a target is subjected to an impurity introduction step. In this thermal process, while a spike RTA process including a holding period for holding a temperature at a predetermined temperature is performed, at least one iteration of millisecond annealing at a temperature higher than the predetermined temperature is performed during the holding period of the spike RTA process.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: July 19, 2011
    Assignee: Panasonic Corporation
    Inventors: Kazuma Takahashi, Kenji Yoneda
  • Patent number: 7964430
    Abstract: Methods and apparatus for reducing defects on transparent conducting oxide (TCO) layer are provided. In one embodiment, a method for depositing a silicon layer on a transparent conducting oxide (TCO) layer may include providing a substrate having a TCO layer disposed thereon, wherein the TCO layer has a peripheral region and a cell integrated region, the cell integrated region having laser scribing patterns disposed thereon, positioning the substrate on a substrate support assembly disposed in a processing chamber, wherein the substrate support assembly has a roughened surface in contact with the substrate, contacting a shadow frame to the peripheral region of the TCO layer and to the substrate support assembly thereby creating an electrical ground path between the TCO layer and substrate support through the shadow frame, and depositing a silicon containing layer on the TCO layer through an aperture of the shadow frame.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: June 21, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Tae Kyung Won, Soo Young Choi, Yong Kee Chae, Liwei Li, Shuran Sheng
  • Patent number: 7964424
    Abstract: A method for manufacturing a nitride semiconductor light-emitting element comprises: forming a semiconductor laminated structure wherein an n-type nitride semiconductor epitaxial layer, an active layer, and a p-type nitride semiconductor epitaxial layer are laminated on a substrate; forming a p-type electrode having a first electrode layer containing Pd and a second electrode layer containing Ta on the p-type nitride semiconductor epitaxial layer; heat treating at a temperature between 400° C. and 600° C. in ambient containing oxygen after forming the p-type electrode; and forming a pad electrode containing Au on the p-type electrode after the heat treating.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: June 21, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kyozo Kanamoto, Katsuomi Shiozawa, Kazushige Kawasaki, Shinji Abe, Hitoshi Sakuma
  • Patent number: 7951632
    Abstract: An optical device and method is disclosed for forming the optical device within the wide-bandgap semiconductor substrate. The optical device is formed by directing a thermal energy beam onto a selected portion of the wide-bandgap semiconductor substrate for changing an optical property of the selected portion to form the optical device in the wide-bandgap semiconductor substrate. The thermal energy beam defines the optical and physical properties of the optical device. The optical device may take the form of an electro-optical device with the addition of electrodes located on the wide-bandgap semiconductor substrate in proximity to the optical device for changing the optical property of the optical device upon a change of a voltage applied to the optional electrodes. The invention is also incorporated into a method of using the optical device for remotely sensing temperature, pressure and/or chemical composition.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: May 31, 2011
    Assignee: University of Central Florida
    Inventors: Nathaniel R. Quick, Aravinda Kar, Islam A. Salama
  • Patent number: 7935550
    Abstract: The object of this invention is to provide a high-output type nitride light emitting device. The nitride light emitting device comprises an n-type nitride semiconductor layer or layers, a p-type nitride semiconductor layer or layers and an active layer therebetween, wherein a gallium-containing nitride substrate is obtained from a gallium-containing nitride bulk single crystal, provided with an epitaxial growth face with dislocation density of 105/cm2 or less, and A-plane or M-plane which is parallel to C-axis of hexagonal structure for an epitaxial face, wherein the n-type semiconductor layer or layers are formed directly on the A-plane or M-plane. In case that the active layer comprises a nitride semiconductor containing In, an end face film of single crystal AlxGa1-xN (0?x?1) can be formed at a low temperature not causing damage to the active layer.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: May 3, 2011
    Assignees: AMMONO Sp. z o.o., Nichia Corporation
    Inventors: Robert Dwilinski, Roman Doradzinski, Jerzy Garczynski, Leszek Sierzputowski, Yasuo Kanbara
  • Publication number: 20110092016
    Abstract: In a method of treating a semiconductor element which at least includes a semiconductor, a threshold voltage of the semiconductor element is changed by irradiating the semiconductor with light with a wavelength longer than an absorption edge wavelength of the semiconductor. The areal density of in-gap states in the semiconductor is 1013 cm?2eV?1 or less. The band gap may be 2 eV or greater. The semiconductor may include at least one selected from the group consisting of In, Ga, Zn and Sn. The semiconductor may be one selected from the group consisting of amorphous In—Ga—Zn—O (IGZO), amorphous In—Zn—O (IZO) and amorphous Zn—Sn—O (ZTO). The light irradiation may induce the threshold voltage shift in the semiconductor element, the shift being of the opposite sign to the threshold voltage shift caused by manufacturing process history, time-dependent change, electrical stress or thermal stress.
    Type: Application
    Filed: March 2, 2009
    Publication date: April 21, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Masato Ofuji, Katsumi Abe, Hisae Shimizu, Ryo Hayashi, Masafumi Sano, Hideya Kumomi, Yasuyoshi Takai, Takehiko Kawasaki, Norio Kaneko
  • Patent number: 7888251
    Abstract: Apparatus and method are provided for hydrogenating semiconductor or other materials by ultraviolet (UV) radiation in the presence of hydrogen. Hydrogen uptake may be optimized by selection of temperature and wavelength of the UV radiation. Patterned areas may be selectively hydrogenated, such as mesas in Avalanche Photodiode Arrays.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: February 15, 2011
    Assignee: Amethyst Research, Inc.
    Inventors: Terry D. Golding, Ronald Paul Hellmer
  • Publication number: 20110018005
    Abstract: A semiconductor device of the present invention includes a semiconductor layer composed of SiC, a metal layer directly bonded to one face of the semiconductor layer, and a high carbon concentration layer formed on a surface layer portion at one side of the semiconductor layer and containing more highly concentrated carbon than a surface layer portion of the other side. Further, a manufacturing method of a semiconductor device of the present invention includes the steps of forming, on a surface layer portion at one face side of a semiconductor layer composed of SiC, a high carbon concentration layer containing more highly concentrated carbon than a surface layer portion at the other face side by heat treatment and directly bonding metal to the high carbon concentration layer.
    Type: Application
    Filed: July 20, 2010
    Publication date: January 27, 2011
    Applicant: ROHM CO., LTD.
    Inventor: Yuki NAKANO
  • Patent number: 7867925
    Abstract: The main object of the present invention is to provide a method for manufacturing efficiently a pattern formed structure which has a surface having a property-varied pattern and can be used to manufacture a color filter or the like. In order to achieve the object, the present invention provides a method for manufacturing a pattern formed structure, comprising: a patterning substrate preparing process of preparing a patterning substrate having a base material and a property variable layer which is formed on the base material and has a property variable by action of a photocatalyst based on irradiation with energy; and an energy radiating process of arranging a photocatalyst containing layer side substrate having a base body and a photocatalyst containing layer comprising at least the photocatalyst, and the patterning substrate so as to keep a given interval between the photocatalyst containing layer and the property variable layer, and then radiating energy onto the resultant at an intensity of 0.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: January 11, 2011
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Hironori Kobayashi, Yusuke Uno
  • Publication number: 20100320458
    Abstract: The invention provides an IGZO-based oxide material and a method of producing the same, the IGZO-based oxide material being represented by a composition formula of In2-xGaxZnO4-?, where 0.75<x<1.10 and 0<??1.29161×exp(?x/0.11802)+0.00153, and being formed from a single phase of IGZO having a crystal structure of YbFe2O4.
    Type: Application
    Filed: June 15, 2010
    Publication date: December 23, 2010
    Applicant: FUJIFILM CORPORATION
    Inventors: Kenichi Umeda, Masayuki Suzuki, Atsushi Tanaka
  • Publication number: 20100304576
    Abstract: A chamber for annealing a semi-conductor material of II-VI type having a first area for storing an element of group II of the periodic table and a second area designed to receive the semi-conductor material of II-VI type. The chamber s equipped with a separating partition at the level of an intermediate area. This separating partition is provided with a passage aperture equipped with gas anti-reverse flow means to ensure one-way passage of the element of group II of the periodic table, in vapor phase, from the first area to the second area. This chamber is heated by heating means enabling the two areas to be heated independently.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 2, 2010
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Laurent Mollard, Guillaume Bourgeois, Franck Henry, Bernard Pelliciari
  • Publication number: 20100304575
    Abstract: The invention relates to a method and an arrangement for tempering SiC wafers. The invention is to provide a method and an arrangement for tempering SiC wafers for generating a sufficient silicon partial pressure in the processing chamber and while reducing the operating costs. This is achieved in that a source for at least vaporized or gaseous silicon to increase the silicon partial pressure is connected to the processing chamber (2) for receiving at least one wafer (3), wherein said source is a vaporizer (4) having liquefied silicon fragments (11), to which a carrier gas can be supplied, which generates a gas flow via a silicone melt, and the vaporizer (4) is connected via a pipeline (5) to the processing chamber (2) or is disposed therein.
    Type: Application
    Filed: December 10, 2008
    Publication date: December 2, 2010
    Inventors: Uwe Keim, Robert Michael Hartung
  • Patent number: 7842534
    Abstract: A method is provided for fabricating a thin film semiconductor device. The method includes providing a plurality of raw semiconductor materials. The raw semiconductor materials undergo a pre-reacting process to form a homogeneous compound semiconductor target material. The compound semiconductor target material is deposited onto a substrate to form a thin film having a composition substantially the same as a composition of the compound semiconductor target material.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: November 30, 2010
    Assignee: Sunlight Photonics Inc.
    Inventors: Allan James Bruce, Sergey Frolov, Michael Cyrus
  • Publication number: 20100291772
    Abstract: The present invention discloses a semiconductor manufacturing method. The method for activating a p-type impurity doped in a semiconductor element in a chamber comprises that a vacuum pressure is exerted to the chamber first, and the semiconductor element is heated to a preset temperature and the heating is persisted for a preset period to activate the p-type impurity doped in the semiconductor element.
    Type: Application
    Filed: May 15, 2009
    Publication date: November 18, 2010
    Inventors: Cheng-Chung YANG, Ming-Sen Hsu
  • Patent number: 7824995
    Abstract: A SiC semiconductor device includes: a SiC substrate having a main surface; a channel region on the substrate; first and second impurity regions on upstream and downstream sides of the channel region, respectively; a gate on the channel region through a gate insulating film. The channel region for flowing current between the first and second impurity regions is controlled by a voltage applied to the gate. An interface between the channel region and the gate insulating film has a hydrogen concentration equal to or greater than 2.6×1020 cm?3. The interface provides a channel surface perpendicular to a (0001)-orientation plane.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: November 2, 2010
    Assignee: Denso Corporation
    Inventors: Takeshi Endo, Tsuyoshi Yamamoto, Eiichi Okuno
  • Patent number: 7816284
    Abstract: There is provided a method of forming a pattern on a group III nitride semiconductor substrate. A method of forming a pattern on a group III nitride semiconductor substrate according to an aspect of the invention may include: irradiating a laser beam onto at least one first region for preventing etching in a group III nitride semiconductor substrate; and etching at least one second region exclusive of the first region using the first region irradiated with the laser beam as a mask.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: October 19, 2010
    Assignee: Samsung LED Co., Ltd.
    Inventors: Jong In Yang, Yu Seung Kim, Sang Yeob Song, Si Hyuk Lee, Tae Hyung Kim
  • Publication number: 20100248499
    Abstract: Rapid thermal processing of freestanding gallium nitride wafers is used to form semiconductor devices. This high speed process is enabled by the low thermal inertia of the growth substrate and the use of a low thermal inertia susceptor. The use of a low thermal inertia susceptor consisting of, but not limited to, silicon carbide, silicon carbide coated graphite, and/or other platen materials. Infrared (IR) heating is a preferred approach for increasing the temperature of the freestanding gallium nitride films via the susceptor but Radio Frequency (RF) and other methods are also approaches.
    Type: Application
    Filed: January 15, 2010
    Publication date: September 30, 2010
    Inventors: Scott M. Zimmerman, Karl W. Beeson, William R. Livesay
  • Patent number: 7799658
    Abstract: An SOI substrate having a single crystal semiconductor layer with high surface planarity is manufactured. A semiconductor substrate is doped with hydrogen, whereby a damaged region which contains large quantity of hydrogen is formed. After a single crystal semiconductor substrate and a supporting substrate are bonded together, the semiconductor substrate is heated, whereby the single crystal semiconductor substrate is separated in the damaged region. While a heated high-purity nitrogen gas is sprayed on a separation plane of the single crystal semiconductor layer separated from the single crystal semiconductor substrate, laser beam irradiation is performed. By irradiation with a laser beam, the single crystal semiconductor layer is melted, whereby planarity of the surface of the single crystal semiconductor layer is improved and re-single-crystallization is performed.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: September 21, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7786024
    Abstract: Methods, systems, and apparatuses for annealing semiconductor nanowires and for fabricating electrical devices are provided. Nanowires are deposited on a substrate. A plurality of electrodes is formed. The nanowires are in electrical contact with the plurality of electrodes. The nanowires are doped. A polarized laser beam is applied to the nanowires to anneal at least a portion of the nanowires. The nanowires may be aligned substantially parallel to an axis. The laser beam may be polarized in various ways to modify absorption of radiation of the applied laser beam by the nanowires. For example, the laser beam may be polarized in a direction substantially parallel to the axis or substantially perpendicular to the axis to enable different nanowire absorption profiles.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: August 31, 2010
    Assignees: Nanosys, Inc., Regents of the University of California
    Inventors: David P. Stumbo, Yaoling Pan, Costas P. Grigoropoulos, Nipun Misra
  • Publication number: 20100182813
    Abstract: In a SiC pn diode, the lifetime is controlled by electron beam irradiation of about 3×1013 cm?2 or more. As a result of the life time control, as shown by a current-voltage characteristic (K10) in FIG. 1, the current started to flow at about 32 V and the on-voltage at an applied current of 100 A was 50 V in the SiC pn diode. In this case, the SiC pn diode has a resistance of 0.5? when the SiC pn diode is turned on. The conducting region of the SiC pn diode is 0.4 cm2, and is reduced to 0.2 ?cm2 by increasing the on-resistance by the lifetime control. Therefore, for instance, in an electric circuit device using a diode and a resistor connected in series in prior arts, the resistor can be eliminated.
    Type: Application
    Filed: June 17, 2008
    Publication date: July 22, 2010
    Inventors: Katsunori Asano, Yoshitaka Sugawara, Atsushi Tanaka
  • Patent number: 7759228
    Abstract: A method of manufacturing a semiconductor device. In the method, a substrate is prepared, which includes a buried oxide film and a SiGe layer formed on the buried oxide film. Then, heat treatment is performed on the substrate at a temperature equal to or lower than a first temperature, to form a protective oxide film on a surface of the SiGe layer. Next, the substrate having the protective oxide film is heated in a non-oxidizing atmosphere to a second temperature higher than the first temperature. Further, heat treatment is performed on the substrate thus heated, in an oxidizing atmosphere at a temperature equal to or higher than the second temperature, to form oxide the SiGe layer, make the SiGe layer thinner and increasing Ge concentration in the SiGe layer, thus forming a SiGe layer having the increased Ge concentration.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: July 20, 2010
    Assignees: Kabushiki Kaisha Toshiba, Oki Electric Industry Co., Ltd.
    Inventors: Naoharu Sugiyama, Norio Hirashita, Tsutomu Tezuka
  • Patent number: 7759219
    Abstract: A method of manufacturing a nitride semiconductor device includes the steps of; forming a stripping layer including In on a substrate; forming a nitride semiconductor layer on the stripping layer; causing a decomposition of the stripping layer by increasing a temperature of the stripping layer; irradiating the stripping layer with laser light; and separating the nitride semiconductor layer from the substrate.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: July 20, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasumitsu Kunoh, Kunio Takeuchi
  • Patent number: 7749867
    Abstract: A method of cutting an object which can accurately cut the object is provided. An object to be processed 1 such as a silicon wafer is irradiated with laser light L while a light-converging point P is positioned therewithin, so as to form a modified region 7 due to multiphoton absorption within the object 1, and cause the modified region 7 to form a starting point region for cutting 8 shifted from the center line CL of the thickness of the object 1 toward the front face 3 of the object 1 along a line along which the object should be cut. Subsequently, the object 1 is pressed from the rear face 21 side thereof. This can generate a fracture from the starting point region for cutting 8 acting as a start point, thereby accurately cutting the object 1 along the line along which the object should be cut.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: July 6, 2010
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Fumitsugu Fukuyo, Kenshi Fukumitsu
  • Publication number: 20100155717
    Abstract: This invention provides an amorphous oxide semiconductor thin film, which is insoluble in a phosphoric acid-based etching solution and is soluble in an oxalic acid-based etching solution by optimizing the amounts of indium, tin, and zinc, a method of producing the amorphous oxide semiconductor thin film, etc. An image display device (1) comprises a glass substrate (10), a liquid crystal (40) as a light control element, a bottom gate-type thin film transistor (1) for driving the liquid crystal (40), a pixel electrode (30), and an opposing electrode (50). The amorphous oxide semiconductor thin film (2) in the bottom gate-type thin film transistor (1) has a carrier density of less than 10+18 cm?3, is insoluble in a phosphoric acid-based etching liquid, and is soluble in an oxalic acid-based etching liquid.
    Type: Application
    Filed: March 26, 2008
    Publication date: June 24, 2010
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Koki Yano, Kazuyoshi Inoue
  • Publication number: 20100140756
    Abstract: An object of the present invention is to provide a semiconductor thin film device which employs a silicon oxide thin film having an equivalent level of high insulating performance to those currently used in electronic devices, through a low-temperature printing process on a plastic substrate having plasticity or other types of substrates at a temperature equal to or lower than the heat resistant temperature of the substrate, and to provide a method for forming the device. The semiconductor thin film device is formed as follows: a coating film of a silicon compound including a silazane structure or a siloxane structure is formed on a plastic substrate having plasticity; the coating film is converted into a silicon oxide thin film; and the thin film is utilized as part of an insulating layer or a sealing layer.
    Type: Application
    Filed: December 4, 2007
    Publication date: June 10, 2010
    Applicant: National Institute of Advanced Industrial Science and Technology
    Inventors: Kenji Kozasa, Toshihide Kamata