Optical Characteristic Sensed Patents (Class 438/7)
  • Publication number: 20120231559
    Abstract: A method of forming a semiconductor thin film includes the steps of: forming an amorphous semiconductor thin film on a substrate; forming a crystalline semiconductor thin film partially in each element region by applying laser light to the amorphous semiconductor thin film to selectively perform a heating process on the amorphous semiconductor thin film, thereby crystallizing the amorphous semiconductor thin film in a region irradiated with the laser light; and inspecting the crystallinity degree of the crystalline semiconductor thin film. The step of inspecting includes the steps of determining a contrast between the luminance of a crystallized region and the luminance of a non-crystallized region by applying light to the crystalline semiconductor thin film and the amorphous semiconductor thin film, and performing screening of the crystalline semiconductor thin film on the basis of the determined contrast.
    Type: Application
    Filed: May 22, 2012
    Publication date: September 13, 2012
    Applicant: SONY CORPORATION
    Inventors: Nobuhiko UMEZU, Koichi TSUKIHARA, Hirohisa AMAGO, Go MATSUNOBU, Katsuya SHIRAI
  • Publication number: 20120231557
    Abstract: The present invention aims to provides a method of manufacturing a film for a semiconductor device in which a dicing film, a die bond film, and a protecting film are laminated in this order, including the steps of: irradiating the die bond film with a light ray having a wavelength of 400 to 800 nm to detect the position of the die bond film based on the obtained light transmittance and punching the dicing film out based on the detected position of the die bond film, and in which T2/T1 is 0.04 or more, wherein T1 is the light transmittance of the portion where the dicing film and the protecting film are laminated and T2 is the light transmittance of the portion where the dicing film, the die bond film, and the protecting film are laminated.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 13, 2012
    Inventors: Koichi INOUE, Miki MORITA, Yuichiro SHISHIDO
  • Patent number: 8244482
    Abstract: A process system adapted for processing of or with a material therein. The process system includes: a sampling region for the material; an infrared photometric monitor constructed and arranged to transmit infrared radiation through the sampling region and to responsively generate an output signal correlative of the material in the sampling region, based on its interaction with the infrared radiation; and process control means arranged to receive the output of the infrared photometric monitor and to responsively control one or more process conditions in and/or affecting the process system.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: August 14, 2012
    Assignee: Advanced Technology Materials, Inc.
    Inventor: Jose I. Arno
  • Patent number: 8236580
    Abstract: A method of monitoring copper contamination. The method includes method, comprising: (a) ion-implanting an N-type dopant into a region of single-crystal silicon substrate, the region abutting a top surface of the substrate; (c) activating the N-type dopant by annealing the substrate at a temperature of 500° C. or higher in an inert atmosphere; (c) submerging, for a present duration of time, the substrate into an aqueous solution, the aqueous solution to be monitored for copper contamination; and (d) determining an amount of copper adsorbed from the aqueous solution by the region of the substrate.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jay Sanford Burnham, Joseph Kerry Vaughn Comeau, Leslie Peter Crane, James Randall Elliott, Scott Alan Estes, James Spiros Nakos, Eric Jeffrey White
  • Patent number: 8236579
    Abstract: Methods and systems for lithographically exposing a substrate based on a curvature profile of the substrate.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: August 7, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tzu Lu, Hung Chang Hsieh, Kuei Shun Chen, Hsueh-Hung Fu, Ching-Hua Hsieh, Shau-Lin Shue
  • Publication number: 20120187428
    Abstract: For the production of a white LED having a predetermined color temperature, a blue LED (2a-2d) or a UV LED is coated with a conversion layer (5) which absorbs the blue light or UV light and emits light of greater wavelength. In accordance with the invention, the exact wavelength of the LED (2a-2d) is determined and the color conversion agent (5) is applied over this LED (2a-2d) in a quantity dependent upon the determined wavelength. Through this, the tolerance of the color temperature can be significantly reduced. The color conversion agent may be applied by means of dispenser or stamp, and the quantity and/or concentration selected in dependence upon the determined wavelength. Inkjet printing, deposition from the gas phase or selective removal by means of a laser is, however, also possible. The invention also relates to light sources produced in accordance with this method.
    Type: Application
    Filed: March 28, 2012
    Publication date: July 26, 2012
    Applicant: TRIDONIC OPTOELECTRONICS GMBH
    Inventor: Günther Leising
  • Publication number: 20120190136
    Abstract: An apparatus and method of manufacturing a light emitting diode (LED) device, and more particularly, an apparatus and method of manufacturing an LED device by dispensing a fluorescent solution prepared by mixing a fluorescent material with a liquid synthetic resin, onto an LED chip. An apparatus and method of manufacturing an LED device, whereby an appropriate amount of fluorescent solution simultaneously in consideration of several factors, such as characteristics of an LED chip and viscosity of the fluorescent solution may be dispensed onto the LED chip, is provided. An apparatus and method of manufacturing an LED device, whereby an appropriate amount of fluorescent solution may be calculated actively in consideration of viscosity of the fluorescent solution, a change in characteristics of an LED chip, or the like, and the appropriate amount of fluorescent solution may be dispensed onto the LED chip, is provided.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 26, 2012
    Applicant: Protec Co., Ltd.
    Inventor: Seung Min Hong
  • Publication number: 20120190135
    Abstract: According to the embodiment, a manufacturing method for a semiconductor device includes detecting a sectional shape of an ion beam irradiated onto a semiconductor substrate and a beam current of the ion beam, calculating a beam current density which is the beam current per unit area based on the beam shape and the beam current detected in the detecting, and adjusting the ion beam based on the beam current density calculated in the calculating.
    Type: Application
    Filed: September 13, 2011
    Publication date: July 26, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takayuki Ito, Koji Kugino
  • Patent number: 8229175
    Abstract: An exemplary system for calculating the number of conductive particles dispersed in an anisotropic conductive film includes an image capturing device and an image processing device. The image capturing device captures a color image of the anisotropic conductive film. The image processing device processes the color image to generate a first binary image. The second binary image includes a plurality of first objects. The first objects occupy a first area in the first binary image. The image processing device processes the first binary image to generate a second binary image having different size with respect to the first binary image by a predetermined value. The second binary image includes a plurality of second objects. The second objects occupy a second area in the second binary image. The image processing device calculates a number of the conductive particles according to the first area, the second area, and the predetermined value.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: July 24, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Pei-Chong Tang
  • Patent number: 8227265
    Abstract: A method of measuring a pattern shape of performing a shape measurement of a semiconductor pattern at a high accuracy even when a process margin is narrow with respect to miniaturization of a semiconductor device is provided. In the method of measuring a pattern shape, when a best-match calculated waveform cannot be selected, at least one parameter among shape parameters is set as a fixed value based on information obtained by another measurement apparatus that uses a measurement method independent to the pattern shape measurement, a matching of a library and a detected waveform is performed again, a best-match calculated waveform is selected, and shape information of an object pattern is obtained from the best-match calculated waveform.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: July 24, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kana Nemoto, Shunichi Matsumoto, Yasuhiro Yoshitake
  • Patent number: 8222051
    Abstract: There is disclosed a manufacturing method for exposure mask, which comprises acquiring a first information showing surface shape of surface of each of a plurality of mask substrates, and a second information showing the flatness of the surface of each of mask substrates before and after chucked on a mask stage of an exposure apparatus, forming a corresponding relation of each mask substrate, the first information and the second information, selecting the second information showing a desired flatness among the second information of the corresponding relation, and preparing another mask substrate having the same surface shape as the surface shape indicated by the first information in the corresponding relation with the selected second information, and forming a desired pattern on the above-mentioned another mask substrate.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: July 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masamitsu Itoh
  • Publication number: 20120178188
    Abstract: A method and apparatus for depositing a phosphor via a compression molding process, the method involving forming a plurality of light-emitting devices on a wafer, evaluating emission characteristics of the plurality of light-emitting devices, and re-arraying and aligning the plurality of light-emitting devices on a carrier substrate according to the emission characteristics; depositing the phosphor on the plurality of re-arrayed light-emitting devices via a compression molding process; and dicing the plurality of re-arrayed light-emitting devices on the carrier substrate.
    Type: Application
    Filed: January 9, 2012
    Publication date: July 12, 2012
    Inventors: Cheol-jun Yoo, Seong-jae Hong
  • Patent number: 8216382
    Abstract: A foreign matter removal method that removes foreign matter attached to a surface of a substrate having been subjected to predetermined processing. An edge of a rotating substrate mounted on a mounting stage is irradiated with misalignment measurement laser light. The misalignment measurement laser light other than the laser light blocked by the edge of the substrate is received, and power thereof is detected. The amount of misalignment of the substrate is calculated based on the detected power of the misalignment measurement laser light and a detected rotation angle of the rotating substrate. The misalignment of the substrate is corrected for based on the calculated amount of misalignment. After that, foreign matter removal laser light is irradiated, and a process gas that is to react with the foreign matter is jetted to the edge of the substrate. Consequently, the foreign matter attached to the substrate is decomposed and removed.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: July 10, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Takehiro Shindo
  • Patent number: 8216384
    Abstract: Embodiments of the current invention describe a cleaning solution for the removal of high dose implanted photoresist, along with methods of applying the cleaning solution to remove the high dose implanted photoresist and combinatorially developing the cleaning solution.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: July 10, 2012
    Assignee: Intermolecular, Inc.
    Inventors: Nitin Kumar, Guizhen Zhang
  • Publication number: 20120164759
    Abstract: A method and apparatus for depositing a phosphor using transfer molding. The method includes: forming a plurality of light-emitting devices on a wafer and rearranging the light-emitting devices on a carrier substrate according to luminance characteristics of the plurality of light-emitting devices by examining the luminance characteristics of the plurality of light-emitting devices; depositing the phosphor on the rearranged light-emitting devices using transfer molding; and separating the light-emitting devices on the carrier substrate.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 28, 2012
    Inventors: Cheol-jun YOO, Seong-jae Hong
  • Publication number: 20120161305
    Abstract: A method includes depositing a thin film on a first surface of a first substrate and moving a second surface of a second substrate into contact with the thin film such that the thin film is located between the first and second surfaces. The method further includes generating electromagnetic (EM) radiation of a first wavelength, the first wavelength selected such that the thin film absorbs EM radiation at the first wavelength. Additionally, the method includes directing the EM radiation through one of the first and second substrates and onto a region of the thin film until the first and second substrates are fused in the region.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 28, 2012
    Applicant: MEDTRONIC, INC.
    Inventors: David A. Ruben, Michael S. Sandlin
  • Patent number: 8207609
    Abstract: A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: June 26, 2012
    Assignee: International Business Machines Corporation
    Inventors: Stephen Peter Ayotte, Jeffrey Peter Gambino, Timothy Dooling Sullivan, Kimball M. Watson
  • Publication number: 20120156809
    Abstract: An exposure apparatus includes a light emission part 10 generating EUV light by plasma excitation of a predetermined atom, a condenser part 20 condensing the EUV light emitted from the light emission part, an exposure part 30 irradiating a substrate via a mask with the EUV light condensed by the condenser part, a first plasma position monitor 11a detecting the position of an emission point of the EUV light within the light emission part, and a light emission part drive unit 13 adjusting the position of the light emission part. The exposure apparatus determines a first shift amount between the emission point detected by the plasma position monitor and a reference light emission position, and drives the light emission part drive unit according to the first shift amount.
    Type: Application
    Filed: November 29, 2011
    Publication date: June 21, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Seiichiro SHIRAI
  • Patent number: 8202738
    Abstract: A method of optically monitoring a substrate during polishing includes receiving an identification of a selected spectral feature and a characteristic of the selected spectral feature to monitor during polishing, measuring a first spectrum from the substrate during polishing, the first spectrum measured within an initial time following initiation of polishing, measuring a sequence of second spectra from the substrate during polishing, the sequence of second spectra measured after the initial time, for each second spectrum in the sequence of second spectra, removing the first spectrum from the second spectrum to generate a sequence of modified third spectra, determining a value of a characteristic of the selected spectral feature for each third spectrum in the sequence of third spectra to generate a sequence of values for the characteristic, and determining a polishing endpoint or an adjustment for a polishing rate based on the sequence of values.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: June 19, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey Drue David, Garrett Ho Yee Sin, Harry Q. Lee, Dominic J. Benvegnu
  • Patent number: 8198605
    Abstract: An apparatus for performing non-contact material characterization includes a wafer carrier adapted to hold a plurality of substrates and a material characterization device, such as a device for performing photoluminescence spectroscopy. The apparatus is adapted to perform non-contact material characterization on at least a portion of the wafer carrier, including the substrates disposed thereon.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: June 12, 2012
    Assignee: Veeco Instruments Inc.
    Inventors: Dong Seung Lee, Mikhail Belousov, Eric A. Armour, William E. Quinn
  • Patent number: 8193005
    Abstract: Methods for the controlled manufacture of high aspect ratio features. The method may include forming a layer stack on a top surface of a substrate and forming features in the layers of the layer stack. The high aspect ratio features may be defined using a resist layer that is patterned with a photolithographic condition. After removing at least one of the layers removed from the top of the layer stack, a feature dimension may be measured for features at different locations on the substrate. The method may further include changing the photolithographic condition based on the measured dimension and processing another substrate using the changed photolithographic condition.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Parrish, Steven M. Shank
  • Publication number: 20120135546
    Abstract: The present disclosure relates to the field of microelectronic substrate fabrication and, more particularly, to alignment inspection for vias formed in the microelectronic substrates. The alignment inspection may be achieved by determining the relative positions of fluorescing and non-fluorescing elements in a microelectronic substrate.
    Type: Application
    Filed: November 30, 2010
    Publication date: May 31, 2012
    Inventors: Zhihua Zou, Liang William Zhang, Sheng Li, Tamil Selvy Selvamuniandy
  • Patent number: 8187905
    Abstract: A microlens, an image sensor including the microlens, a method of forming the microlens and a method of manufacturing the image sensor are provided. The microlens includes a polysilicon pattern, having a cylindrical shape, formed on a substrate, and a round-type shell portion enclosing the polysilicon pattern. The microlens may further include a filler material filling an interior of the shell portion, or a second shell portion covering the first shell portion. The method of forming a microlens includes forming a silicon pattern on a semiconductor substrate having a lower structure, forming a capping film on the semiconductor substrate over the silicon pattern, annealing the silicon pattern and the capping film altering the silicon pattern to a polysilicon pattern having a cylindrical shape and the capping film to a shell portion for a round-type microlens, and filling an interior of the shell portion with a lens material through an opening between the semiconductor substrate and an edge of the shell portion.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: May 29, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Huaxiang Yin, Hyuck Lim, Young-soo Park, Wenxu Xianyu, Hans S. Cho
  • Publication number: 20120129276
    Abstract: A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tongue and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling, and is further diced at the fixed clock-cycle distance, and flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device.
    Type: Application
    Filed: January 18, 2012
    Publication date: May 24, 2012
    Applicant: International Business Machines Corporation
    Inventors: Wilfried Haensch, Roy R. Yu
  • Publication number: 20120104389
    Abstract: Sacrificial optical test structures are constructed upon a wafer (100) of pre-cleaved optical chips (10) for testing the optical functions of the pre-cleaved optical chips (10). The sacrificial optical structures are disabled upon the cleaving the optical chips (10) from the wafer (100) and the cleaved optical chips (10) can be used for their desired end functions. The test structures may remain on the cleaved optical chips (10) or they may be discarded.
    Type: Application
    Filed: March 30, 2010
    Publication date: May 3, 2012
    Inventors: Neil David Whitbread, Lloyd Nicholas Langley, Andrew Cannon Carter
  • Publication number: 20120104526
    Abstract: An imager apparatus and methods are described. An embodiment of an imager module includes a plurality of groups of optical lenses, a lens frame, and at least one associated lens barrel configured to position and hold the plurality of groups of optical lenses. At least one of the groups of optical lenses is movable with respect to at least one other group of optical lenses for achieving optical focus. The imager module includes an integrated circuit (IC) imager die in proximity to the plurality of lenses, the imager die containing at least one image capture microelectronic device.
    Type: Application
    Filed: January 6, 2012
    Publication date: May 3, 2012
    Inventors: Richard Ian Olsen, Darryl L. Sato, Feng-Qing Sun, James Gates
  • Publication number: 20120100640
    Abstract: Systems and methods for forming a time-average line image are disclosed. The method includes forming a line image with a first amount of intensity non-uniformity. The method also includes forming and scanning a secondary image over at least a portion of the line image to form a time-averaged modified line image having a second amount of intensity non-uniformity that is less than the first amount. Wafer emissivity is measured in real time to control the intensity of the secondary image. Temperature is also measured in real time based on the wafer emissivity and reflectivity of the secondary image, and can be used to control the intensity of the secondary image.
    Type: Application
    Filed: August 10, 2011
    Publication date: April 26, 2012
    Inventors: Serguei Anikitchev, James T. McWhirter, Joseph E. Gortych
  • Publication number: 20120094401
    Abstract: A method of inspecting a semiconductor substrate having a back surface and including at least one piece of metal embedded in the substrate comprises directing measuring light towards the back surface of the substrate and detecting a portion of the measuring light received back from the substrate. The method also includes determining a distance between the piece of metal and the back surface based upon the detected measuring light received back from the substrate.
    Type: Application
    Filed: April 18, 2011
    Publication date: April 19, 2012
    Applicants: IMEC, Nanda Technologies GmbH
    Inventors: Lars Markwort, Pierre-Yves Guittet, Sandip Halder, Anne Jourdain
  • Publication number: 20120096006
    Abstract: A method of controlling polishing includes storing a library having a plurality of reference spectra, polishing a substrate, measuring a sequence of spectra of light from the substrate during polishing, for each measured spectrum of the sequence of spectra, finding a best matching reference spectrum using a matching technique other than sum of squared differences to generate a sequence of best matching reference spectra, and determining at least one of a polishing endpoint or an adjustment for a polishing rate based on the sequence of best matching reference spectra. Finding a best matching reference spectrum may include performing a cross-correlation of the measured spectrum with each of two or more of the plurality of reference spectra from the library and selecting a reference spectrum with the greatest correlation to the measured spectrum as a best matching reference spectrum.
    Type: Application
    Filed: October 10, 2011
    Publication date: April 19, 2012
    Inventors: Jeffrey Drue David, Dominic J. Benvegnu, Xiaoyuan Hu
  • Publication number: 20120094400
    Abstract: A method and apparatus for process control in a lithographic process are described. Metrology may be performed on a substrate either before or after performing a patterning process on the substrate. One or more correctables to the lithographic patterning process may be generated based on the metrology. The patterning process performed on the substrate (or a subsequent substrate) may be adjusted with the correctables.
    Type: Application
    Filed: December 23, 2011
    Publication date: April 19, 2012
    Applicant: KLA-Tencor Corporation
    Inventors: Michael Adel, John Fielden, Amir Widmann, John Robinson, Dongsub Choi
  • Patent number: 8158017
    Abstract: A method of detecting substrate arcing in a semiconductor plasma processing apparatus is provided. A substrate is placed on a substrate support in a reaction chamber of a plasma processing apparatus. Process gas is introduced into the reaction chamber. A plasma is generated from the process gas and the substrate is processed with the plasma. Intensities of real-time spectrometry signals of selected gas species produced in the reaction chamber during plasma processing are monitored. The selected gas species are generated by a substrate arcing event. The arcing event is detected when the intensities are above a threshold value.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: April 17, 2012
    Assignee: Lam Research Corporation
    Inventor: Eric Hudson
  • Patent number: 8158446
    Abstract: A method of manufacturing a semiconductor device includes: forming a groove portion in a dicing region of an insulating layer and forming a via hole in an internal circuit formation region; providing a first resist film on the insulating layer; providing a second resist film to cover the first resist film; forming an interconnect opening in a region covering an internal circuit formation region of the second resist film and forming a position aligning opening in a region covering the dicing region of the second resist film; and detecting a positional relationship between the groove portion and the position aligning opening so as to detect whether the interconnect opening of the second resist film exists at a predetermined position with respect to the via hole of the insulating layer. In selective removing of the second resist film, the position aligning opening is formed such that a region of the position aligning opening covers the groove portion of the insulating layer.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: April 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Manabu Iguchi, Mami Miyasaka
  • Patent number: 8148176
    Abstract: A method of distinguishing a set of highly doped regions from a set of lightly doped regions on a silicon substrate is disclosed. The method includes providing the silicon substrate, the silicon substrate configured with the set of lightly doped regions and the set of highly doped regions. The method further includes illuminating the silicon substrate with an electromagnetic radiation source, the electromagnetic radiation source transmitting a wavelength of light above about 1100 nm. The method also includes measuring a wavelength absorption of the set of lightly doped regions and the set of heavily doped regions with a sensor, wherein for any wavelength above about 1100 nm, the percentage absorption of the wavelength in the lightly doped regions is substantially less than the percentage absorption of the wavelength in the heavily doped regions.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: April 3, 2012
    Assignee: Innovalight, Inc.
    Inventors: Maxim Kelman, Giuseppe Scardera
  • Publication number: 20120075368
    Abstract: According to one embodiment, a droplet dispensing control method includes detecting an amount of positional deviation between a stage on which a substrate is mounted and a template as a template positional deviation amount and detecting an amount of positional deviation between a movement direction of the stage and a nozzle array direction as a nozzle positional deviation amount. The method further includes calculating a stage movement direction correction value and an ejection timing correction value of the imprint material as correction values for eliminating the positional deviation of the landing position of the imprint material. The method further includes controlling the movement direction of the stage using the stage movement direction correction value and controlling the ejection timing of the imprint material using the ejection timing correction value.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 29, 2012
    Inventors: Shinji MIKAMI, IKuo Yoneda
  • Patent number: 8143075
    Abstract: A semiconductor device manufacture method has the steps of: (a) forming a semiconductor device structure in a chip and alignment marks, respectively in a semiconductor wafer; (b) forming a workpiece layer above the semiconductor wafer; (c) exposing the alignment marks; (d) coating an electron beam resist film on the workpiece layer; (e) scanning the alignment marks with an electron beam to obtain plural position information on the alignment marks and obtaining differences between the plural position information; (f) removing abnormal values of position information in accordance with the difference between the plural position information; and (g) performing an electron beam exposure in accordance with plural position information of the alignment marks with the abnormal value being removed. An alignment mark detection precision can be improved in electron beam exposure.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: March 27, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takashi Maruyama
  • Publication number: 20120061828
    Abstract: A semiconductor device that is resin-sealed in a wafer level after a rewiring layer forming process and a metal post forming process forming a metal post are performed on a semiconductor substrate of the semiconductor device includes devices formed on the semiconductor substrate. Further all of the devices are disposed in respective positions other than positions overlapping a peripheral border of the metal post when viewed from a top of the semiconductor substrate.
    Type: Application
    Filed: September 9, 2011
    Publication date: March 15, 2012
    Applicant: RICOH COMPANY, LTD.
    Inventors: Junichi KONISHI, Naohiro Ueda
  • Patent number: 8127713
    Abstract: An apparatus for dispensing fluid during semiconductor substrate processing operations comprises an enclosure having a first side and a second side. The enclosure comprises a first processing station and a second processing station. The second processing station is positioned adjacent to the first processing station. In addition, the substrate processing apparatus includes a first dispense arm configured to deliver a fluid to the first processing station wherein the first dispense arm is positioned between the first side and the first processing station and a second dispense arm configured to deliver the fluid to the second processing station wherein the second dispense arm is positioned between the second side and the second processing station. The substrate processing apparatus also comprises a first rinse arm configured to deliver a rinsing fluid to the first processing station and a second rinse arm configured to deliver the rinsing fluid to the second processing station.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: March 6, 2012
    Assignee: Sokudo Co., Ltd.
    Inventors: Eric B. Britcher, Yevgeniy Rabinovich, Svetlana Sherman, Masami Ohtani
  • Patent number: 8115137
    Abstract: In laser annealing using a solid state laser, a focus position of a minor axial direction of a rectangular beam is easily corrected depending on positional variation of a laser irradiated portion of a semiconductor film. By using a minor-axis condenser lens 29 condensing incident light in a minor axial direction and a projection lens 30 projecting light, which comes from the minor-axis condenser lens 29, onto a surface of a semiconductor film 3, laser beam 1 is condensed on the surface of the semiconductor film 3 in the minor axial direction of a rectangular beam. The positional variation of a vertical direction of the semiconductor film 3 in a laser irradiated portion of the semiconductor film 3 is detected by a positional variation detector 31, and the minor-axis condenser lens 29 is moved in an optical axis direction based on a value of the detection.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: February 14, 2012
    Assignee: IHI Corporation
    Inventors: Norihito Kawaguchi, Ryusuke Kawakami, Kenichiro Nishida, Miyuki Masaki, Masaru Morita, Atsushi Yoshinouchi
  • Patent number: 8110413
    Abstract: In one embodiment, a mask pattern verification apparatus is disclosed.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: February 7, 2012
    Inventors: Chikaaki Kodama, Takanori Urakami, Nozomu Furuta, Shunsuke Kagaya
  • Publication number: 20120021539
    Abstract: A metrology system for gauging and spatially mapping a semiconductor material on a substrate can be used in controlling deposition and thermal activation processes.
    Type: Application
    Filed: July 25, 2011
    Publication date: January 26, 2012
    Inventors: Arnold Allenic, Stephan Paul George, II, Sreenivas Jayaraman, Oleh Karpenko, Chong Lim
  • Publication number: 20120015455
    Abstract: Methods for matching semiconductor processing chambers using a calibrated spectrometer are disclosed. In one embodiment, plasma attributes are measured for a process in a reference chamber and a process in an aged chamber. Using a calibrated light source, an optical path equivalent to an optical path in a reference chamber and an optical path in an aged chamber can be compared by determining a correction factor. The correction factor is applied to adjust a measured intensity of plasma radiation through the optical path in the aged chamber. Comparing a measured intensity of plasma radiation in the reference chamber and the adjusted measured intensity in the aged chamber provide an indication of changed chamber conditions. A magnitude of change between the two intensities can be used to adjust the process parameters to yield a processed substrate from the aged chamber which matches that of the reference chamber.
    Type: Application
    Filed: July 22, 2011
    Publication date: January 19, 2012
    Applicant: Applied Materials, Inc.
    Inventors: Sairaju Tallavarjula, Kailash Pradhan, Huy Q. Nguyen, Jian Li
  • Patent number: 8097900
    Abstract: A monolithically integrated light-activated thyristor in an n-p-n-p-n-p sequence consists of a four-layered thyristor structure and an embedded back-biased PN junction structure as a turn-off switching diode. The turn-off switching diode is formed through structured doping processes and/or depositions on a single semiconductor wafer so that it is integrated monolithically without any external device or semiconductor materials. The thyristor can be switching on and off optically by two discrete light beams illuminated on separated openings of electrodes on the top surface of a semiconductor body. The carrier injection of the turning on process is achieved by illuminating the bulk of the thyristor with a high level light through the first aperture over the cathode to create high density charge carriers serving as the gate current injection and to electrically short the emitter and drift layer.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: January 17, 2012
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Yeuan-Ming Sheu
  • Publication number: 20120007188
    Abstract: An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a reduced-stress dual stress liner NMOS device having a stress reduction layer that extends between the tensile stress layer and the NMOS gate film stack, and a reduced-stress dual stress liner PMOS device having a stress reduction layer that extends between the compressive stress layer and the PMOS gate film stack. In embodiments of the invention additional reduced-stress dual stress liner NMOS devices and reduced-stress PMOS devices are formed by altering the thickness and/or the material properties of the stress reduction layer.
    Type: Application
    Filed: September 9, 2011
    Publication date: January 12, 2012
    Applicant: XILINX, INC.
    Inventor: Sharmin Sadoughi
  • Patent number: 8093079
    Abstract: Methods of fabricating of a light-emitting device are provided, the methods include forming a plurality of light-emitting units on a substrate, measuring light characteristics of the plurality of light-emitting units, respectively, depositing a phosphor layer on the plurality of light-emitting units using a printing method, and cutting the substrate to separate the plurality of light-emitting units into unit by unit. The phosphor layer is adjustably deposited according to the measured light characteristics of the plurality of light-emitting units.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: January 10, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yu-Sik Kim
  • Publication number: 20120003758
    Abstract: A method of fabricating light emitting diode chips having a phosphor coating layer comprises providing a substrate having a plurality of light emitting diodes formed thereon; forming a conductive bump on at least one of the plurality of light emitting diodes; forming a phosphor coating layer over the substrate and the light emitting diodes; cutting the phosphor coating layer by a point cutter to remove an upper portion of the phosphor coating layer, so as to reduce a thickness of the phosphor coating layer and expose the conductive bump; and forming a plurality of individual light emitting diode chips having the phosphor coating layer by separating the plurality of light emitting diodes.
    Type: Application
    Filed: September 12, 2011
    Publication date: January 5, 2012
    Inventor: Chung-Chuan HSIEH
  • Patent number: 8088633
    Abstract: A method of aligning a wafer when lithographically fabricating a light-emitting diode (LED). The method includes forming on the wafer at least one roughened alignment mark having a root-mean-square (RMS) surface roughness ?S. The roughened alignment mark is formed as a consequence of forming a plasma etch to roughen a LED surface on which the wafer alignment mark resides. The method also includes imaging the at least one roughened wafer alignment mark with alignment light having a wavelength ?A that is in the range from about 2?S to about 8?S. The method also includes comparing the detected image to an alignment reference to establish wafer alignment. Once wafer alignment is established, p-contacts and n-contacts can be formed on the LED upper surface in their proper locations.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: January 3, 2012
    Assignee: Ultratech, Inc.
    Inventors: Robert L. Hsieh, Khiem Nguyen, Warren W. Flack, Andrew M. Hawryluk
  • Patent number: 8088632
    Abstract: Protons are entered into a substrate to be analyzed at a proton incident angle larger than 0° and smaller 90°. Excited by the entered protons and emitted from the substrate to be analyzed, the characteristic X-ray is measured by an energy dispersive X-ray detector and the like. Impurity elements present in the substrate to be analyzed are identified based on the measured characteristic X-ray. The in-plane distribution in the substrate can be obtained by scanning the proton beam. The in-depth distribution can be obtained by entering protons at different proton incident angles. The elemental analysis method can be applied to semiconductor device manufacturing processes to analyze metal contamination or quantify a conductivity determining impurity element on an inline basis and with a high degree of accuracy.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: January 3, 2012
    Assignee: Panasonic Corporation
    Inventors: Satoshi Shibata, Hisako Kamiyanagi, Fumitoshi Kawase, Tetsuyuki Okano
  • Patent number: 8080434
    Abstract: A nondestructive testing method for an oxide semiconductor layer includes the steps of applying excitation light to an amorphous or polycrystalline target oxide semiconductor layer to be tested and measuring an intensity of photoluminescence in a wavelength region longer than a wavelength corresponding to a bandgap energy among light emitted from the target oxide semiconductor layer; and estimating a film property of the target oxide semiconductor layer on the basis of measurement results.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: December 20, 2011
    Assignee: Sony Corporation
    Inventors: Norihiko Yamaguchi, Satoshi Taniguchi, Masao Ikeda
  • Publication number: 20110300644
    Abstract: According to one embodiment, a method for manufacturing a semiconductor light emitting device is disclosed. The method can include forming a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar, a second insulating layer, a transparent material and a phosphor layer. The transparent material is formed on the first major surface of a semiconductor layer selected from the plurality of semiconductor layers on the basis of an emission spectrum of a light obtained from the first major surface side. The transparent material transmits the light. The phosphor layer is formed on the transparent material and the first major surface of the plurality of the semiconductor layers.
    Type: Application
    Filed: June 6, 2011
    Publication date: December 8, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke Akimoto, Akihiro Kojima, Miyuki Izuka, Yoshiaki Sugizaki, Hiroshi Koizumi, Tomomichi Naka, Yasuhide Okada
  • Publication number: 20110300645
    Abstract: An apparatus for performing non-contact material characterization includes a wafer carrier adapted to hold a plurality of substrates and a material characterization device, such as a device for performing photoluminescence spectroscopy. The apparatus is adapted to perform non-contact material characterization on at least a portion of the wafer carrier, including the substrates disposed thereon.
    Type: Application
    Filed: August 12, 2011
    Publication date: December 8, 2011
    Applicant: VEECO INSTRUMENTS INC.
    Inventors: Dong Seung Lee, Mikhail Belousov, Eric A. Armour, William E. Quinn