Stereolithography Patents (Class 700/120)
  • Patent number: 10372871
    Abstract: An IC design layout is decomposed into multiple masks to produce an initial output. A post-decomposition optimization is performed. The post-decomposition optimization includes identifying hotspots in the multiple masks, clustering features that contribute to the hotspots into clusters, identifying ones of the clusters that can be relocated to a different mask to eliminate the hotspot, without violating design rules, as reversible clusters, ranking movement of the reversible clusters by comparing the reversible clusters, as potentially moved, to known manufacturability metrics, and moving the reversible clusters to different masks according to the priority established by the ranking, to produce a post-decomposition optimized tape-out. The IC devices are manufactured by applying the post-decomposition optimized tape-out to manufacturing equipment.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: August 6, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lynn Tao-Ning Wang, Sriram Madhavan
  • Patent number: 9975322
    Abstract: A three-dimensional object printer enables production of cylindrically shaped objects. The printer includes a controller operatively connected to at least two printheads, at least one object treating device, and actuator that is operatively connected to a cylindrical member being supported by at least two supports. The controller is configured to operate the actuator to rotate the cylindrical member within the at least two supports, to operate the plurality of ejectors in each of the at least two printheads to form portions of layers on the rotating cylindrical member with the different materials supplied to the at least two printheads, and to operate the at least one object treating device to modify the layers formed on the rotating cylindrical member while the cylindrical member is rotating within the at least two supports.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: May 22, 2018
    Assignee: Xerox Corporation
    Inventors: Erwin Ruiz, Steven M. Russel, Paul M. Fromm, Jeffrey N. Swing
  • Patent number: 9796138
    Abstract: A method and a device for processing a light-polymerizable material (5, 55) for building up an object (27) in layers, using a lithography based generative manufacture having a construction platform (12) for building up the object (27), a projecting exposure unit (10, 60) that can be controlled for locally selected exposing of a surface on the construction platform (12, 62) to an intensity pattern having a prescribed shape, and a control unit (11, 61) prepared for polymerizing overlapping layers (28) on the construction platform (12, 62) in successive exposure steps, each having a prescribed geometry, by controlling the projecting exposure unit (10, 60), in order to thus successively build up the object (27) in the desired shape, said shape resulting from the sequence of layer geometries.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: October 24, 2017
    Assignees: Ivoclar Vivadent AG, Technische Universitat Wien
    Inventors: Robert Liska, Johannes Patzer, Jurgen Stampfl, Wolfgang Wachter, Christoph Appert
  • Patent number: 9530983
    Abstract: A sintering method includes defining a closed pattern having at least one arcuate section. A substance is applied on a substrate along the closed pattern and is sintered along the closed pattern in a first rectilinear direction. The sintering is finished in a second rectilinear direction along the closed pattern. A display device packaging method includes defining a closed pattern having at least one arcuate section. Frit is applied on a substrate of a display device along the closed pattern. A cover plate is provided on the substrate. The frit is sintered along the closed pattern. The sintering is finished in a second rectilinear direction. Then, the cover plate and the substrate of the display device are packaged.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: December 27, 2016
    Assignee: EverDisplay Optronics (Shanghai) Ltd.
    Inventors: Yanhu Li, Chih-Wei Wen
  • Patent number: 9355204
    Abstract: A method of decomposing a design layout for a double patterning process is provided. The method includes changing, by a computing system, a design layout of a first polygon type to a design layout of a curved polygon type; coloring the design layout of the curved polygon type; generating stitching shapes for preventing acute corners in stitching areas of the colored design layout of the curved polygon type; separating the design layout including the stitching shapes for preventing the acute corners into separated design layouts of curved polygon type according to colors; and changing the separated design layouts of the curved polygon type to design layouts of a second polygon type.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: May 31, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wook Seo, Jeong-Hoon Lee, Hye-Soo Shin
  • Patent number: 9031685
    Abstract: A method and apparatus for atomic layer deposition (ALD) is described. In one embodiment, an apparatus comprises a vacuum chamber body having a contiguous internal volume comprised of a first deposition region spaced-apart from a second deposition region, the chamber body having a feature operable to minimize intermixing of gases between the first and the second deposition regions, a first gas port formed in the chamber body and positioned to pulse gas preferentially to the first deposition region to enable a first deposition process to be performed in the first deposition region, and a second gas port formed in the chamber body and positioned to pulse gas preferentially to the second deposition region to enable a second deposition process to be performed in the second deposition region is provided.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 12, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Barry L. Chin, Alfred W. Mak, Lawrence C. Lei, Ming Xi, Hua Chung, Ken Kaung Lai, Jeong Soo Byun
  • Publication number: 20150123319
    Abstract: The invention is a method for producing a three-dimensional object in layers through stereolithography, comprising the following operations: moving a supporting surface (6a, 7a) near the bottom (2a) of a container (2) containing a liquid substance (3), so as to arrange it in a predefined operating position (17); selectively irradiating a layer (6) of liquid substance (3) with pre-defined radiation (4), in such a way as to solidify it against the supporting surface (6a, 7a). The approaching movement (11) comprises a plurality of approaching moves (12, 12a, 12b, 12c) having corresponding predefined lengths (13, 13a, 13b, 13c), spaced by corresponding intermediate stops (14, 14a, 14b) for corresponding predefined time intervals (15, 15a, 15b), the intermediate stops (14, 14a, 14b) being carried out when the supporting surface (6a, 7a) is at least partially immersed in the liquid substance (3).
    Type: Application
    Filed: July 15, 2013
    Publication date: May 7, 2015
    Inventors: Roberto Fortunato, Sergio Zenere
  • Publication number: 20150100149
    Abstract: A system and method for calibrating a laser scanning system is provided. Various embodiments involve the use of a calibration plate with reference markings which is positioned to receive a directed beam in a set of known laser scanner positions. The directed beam forms a laser spot on the calibration plate, and the laser spot is captured using an image acquisition assembly such as a digital camera along with a motorized mount. The movement of the image acquisition assembly may be coordinated with the movement of the laser scanner to track the laser spot across the plate. After photographing various positions, actual laser spot coordinates are deduced from their position relative to the known positions of the reference markings.
    Type: Application
    Filed: September 19, 2014
    Publication date: April 9, 2015
    Inventors: Sam COECK, Kurt RENAP
  • Patent number: 9003338
    Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Lee, Chung-Sheng Yuan, Chao-Yang Yeh, Wei-Cheng Wu, Ching-Fang Chen
  • Patent number: 9002496
    Abstract: Disclosed herein is a device adapted to make a solid object. The device has a surface rotatable around an axis of rotation, and an applicator adapted to apply over at least one portion of the surface a material used to make the solid object. The applicator and the surface are displaceable relative to each other in a direction transverse to the axis. Disclosed herein are also methods of determining instructions for the device.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: April 7, 2015
    Assignee: Zydex Pty Ltd
    Inventor: Justin Elsey
  • Patent number: 8977378
    Abstract: Disclosed are methods and systems for using hieroglyphs for communication in a rapid fabrication environment. The method includes receiving, by a control system for an articulated robotic arm, one or more images of a fabrication machine build space. The method includes identifying, by the control system, a hieroglyph present in the one or more images and translating the identified hieroglyph into one or more instructions for manipulation of the articulated robotic arm. The method includes causing the articulated robotic arm to carry out the instructions translated from the identified hieroglyph. Accordingly foreign objects are inserted into fabricated objects during an automated rapid fabrication process without extensive redesign of the rapid fabrication machine. In some implementations, an unmodified third-party stereolithographic rapid fabrication machine can be used.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: March 10, 2015
    Assignee: Northeastern University
    Inventors: Brian Weinberg, Constantinos Mavroidis
  • Patent number: 8972909
    Abstract: The present disclosure relates to a method of performing an optical proximity correction (OPC) procedure that provides for a high degree of freedom by using an approximation design layer. In some embodiments, the method is performed by forming an integrated chip (IC) design having an original design layer with one or more original design shapes. An approximation design layer, which is different from the original design layer, is generated from the original design layer. The approximation design layer is a design layer that has been adjusted to remove features that may cause optical proximity correction (OPC) problems. An optical proximity correction (OPC) procedure is then performed on the approximation design layer. By performing the OPC procedure on the approximation design layer rather than on the original design layer, characteristics of the OPC procedure can be improved.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Chang, Jau-Shian Liang, Wen-Chen Lu, Chin-Min Huang, Ming-Hui Chih, Cherng-Shyan Tsay, Chien-Wen Lai, Hua-Tai Lin
  • Patent number: 8966410
    Abstract: A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: February 24, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Wei Huang, Ming-Jui Chen, Chun-Hsien Huang
  • Publication number: 20150045934
    Abstract: Three-dimensional object bridge between virtual and physical worlds. A method, system, apparatus and/or computer-usable medium includes steps of selecting a three-dimensional item in a first state for subsequent rendering into a second state and rendering the three-dimensional item in the second state via the three-dimensional rendering apparatus. An additional step of locating a three-dimensional rendering apparatus for rendering the three-dimensional item in a second state can be included. The three-dimensional rendering apparatus can be configured as a kiosk (manned or unmanned), Internet-enabled vending machine, and the like. The first state can comprise a virtual state and the second state can comprise a physical state. Likewise, the first state can comprise a physical state and the second state can comprise a virtual state. Additionally, the three-dimensional item/object can be mapped in the first state for rendering in the second state.
    Type: Application
    Filed: August 7, 2013
    Publication date: February 12, 2015
    Inventors: Christopher Kallenbach, Luke Nihlen, Luis M. Ortiz
  • Publication number: 20150045935
    Abstract: Systems and methods for tuning photolithographic processes are described. A model of a target scanner is maintained defining sensitivity of the target scanner with reference to a set of tunable parameters. A differential model represents deviations of the target scanner from the reference. The target scanner may be tuned based on the settings of the reference scanner and the differential model. Performance of a family of related scanners may be characterized relative to the performance of a reference scanner. Differential models may include information such as parametric offsets and other differences that may be used to simulate the difference in imaging behavior.
    Type: Application
    Filed: October 28, 2014
    Publication date: February 12, 2015
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Yu CAO, Wenjin SHAO, Ronaldus Johannes Gijsbertus GOOSSENS, Jun YE, James Patrick KOONMEN
  • Publication number: 20150019000
    Abstract: An image projection system projects a single image on an image projection region from a plurality of image projection sections and includes section that detects checker intersection coordinates in a corrected checkered sheet image, a section that calculates a first projective transformation matrix from the checker intersection coordinates, a section that generates first and second spatial code images, a section that acquires boundary lines in the first and second spatial code images, and acquires first intersection coordinates of the boundary lines, a section that calculates a second projective transformation matrix for projective transformation of the first intersection coordinates, transformed using the first projective transformation matrix, into second intersection coordinates distributed over an entire sub-region of the image projection region, and a section that transforms image data by using the second projective transformation matrix.
    Type: Application
    Filed: July 8, 2014
    Publication date: January 15, 2015
    Inventor: Yasutoshi NAKAMURA
  • Patent number: 8930859
    Abstract: Embodiments relate to a method of decomposing a layout of a semiconductor device. The method may include generating a pattern layout including first patterns and second patterns, generating an interference map for the pattern layout, the interference map including optical interference information regarding the first and second patterns, and decomposing the pattern layout into a first decomposition pattern layout including the first patterns, and a second decomposition pattern layout including the second patterns, based on the interference map. In the interference map, an influence of constructive interference on the first patterns may be greater than an influence of constructive interference on the second patterns.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sung-Gon Jung
  • Publication number: 20140379114
    Abstract: A projection image correction system includes a section that detects intersection coordinates in a corrected sheet image, a section that calculates a first projective transformation matrix for transformation of the detected intersection coordinates into intersection coordinates stored in advance, a section that generates two spatial code images from the corrected positive and negative images of Gray code patterns, a section that acquires intersections of brightness profiles in the positive and negative images, a section that acquires coordinates of an intersection of boundary lines in the two spatial code images, a section that calculates a second projective transformation matrix by which transformation is performed so that the acquired intersection coordinates, transformed by the first projective transformation matrix, are distributed over the entire region, and a section that transforms, using the second projective transformation matrix, image data to be outputted to a projector.
    Type: Application
    Filed: June 24, 2014
    Publication date: December 25, 2014
    Inventor: Yasutoshi NAKAMURA
  • Patent number: 8918746
    Abstract: Methodologies and an apparatus enabling a selection of design rules to improve a density of features of an IC design are disclosed. Embodiments include: determining a feature overlapping a grating pattern of an IC design, the grating pattern including a plurality of grating structures; determining a shape of a cut pattern overlapping the grating pattern; and selecting one of a plurality of rules for the feature based on the determined shape.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: December 23, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lei Yuan, Jongwook Kye, Harry J. Levinson
  • Patent number: 8893067
    Abstract: In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: November 18, 2014
    Assignee: ASML Netherlands B.V.
    Inventors: Jun Ye, Yen-Wen Lu, Yu Cao, Luoqi Chen, Xun Chen
  • Patent number: 8880209
    Abstract: A 3D modeling apparatus includes: a support body which supports a modeled object formed by laminating a resin material that is cured by energy of an energy ray; an illumination mechanism which illuminates the resin material with the energy ray, on the basis of image data of laminated cross-sections which constitutes 3D data of an object to be modeled which is an object of modeling, in order to form the modeled object; and a supply mechanism which supplies a material that constitutes a part of the modeled object and is different from the resin material, to the resin material that is cured as being illuminated by the illumination mechanism, on the basis of the cross-section image data.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: November 4, 2014
    Assignee: Sony Corporation
    Inventor: Hiroyuki Yasukochi
  • Publication number: 20140316549
    Abstract: A three-dimensional object (1) made by way of a stereolithography process, includes a plurality of supports (3) that are connected to the body (2) of the object through joining elements (4) in each one of which it is possible to identify a shaped area (5), recessed with respect to the external surface of the joining element (4) and having the bottom corner (6) that delimits a pre-established fracture area (7) for the detachment of the support (3). Each one of the joining elements (4) includes a first body (8) projecting from the external surface that delimits the body (2) of the object and a second body (9) projecting from the support (3), the bodies (8) and (9) being connected to each other so as to define the shaped area (5) whose bottom corner (6) delimits the pre-established fracture area (7). Each one of the bodies (8, 9) has its convex curved external surface that constitutes part of the external surface of a sphere or an ellipsoid.
    Type: Application
    Filed: November 20, 2012
    Publication date: October 23, 2014
    Applicant: DWS, S.R.L.
    Inventor: Sergio Zenere
  • Patent number: 8862260
    Abstract: The invention relates to a process or device for the production of a three-dimensional object by layer-wise solidification of a material which is solidifiable under the application of electromagnetic irradiation by means of mask illumination, wherein the mask is produced using an image forming unit having a prescribed resolution, which is formed from a constant number of image forming elements (pixels) being discrete and being arranged in a spatially mutually fixed manner. For the improvement of the resolution along the outer and inner contours of the sectional areas of the object to be generated layer-wise in the sub-pixel range, a multiple illumination per layer is performed, which consists of a series of multiple images that are mutually shifted in the sub-pixel range in the image/construction plane, wherein a separate mask/bitmap is produced for each shifted image.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: October 14, 2014
    Assignee: Envisiontec GmbH
    Inventors: Alexandr Shkolnik, Hendrik John, Ali El-Siblani
  • Patent number: 8845949
    Abstract: The present invention relates to a new and improved stereolithography method and system for generating a three-dimensional object by forming successive, adjacent, cross-sectional laminae of that object, thereby providing an object being specially processed to reduce differential shrinkage.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: September 30, 2014
    Assignee: Materialise N.V.
    Inventor: Sam Coeck
  • Patent number: 8843859
    Abstract: The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: September 23, 2014
    Assignee: Mentor Graphics Corporation
    Inventors: Juan Andres Torres Robles, Oberdan Otto, Yuri Granik
  • Publication number: 20140277679
    Abstract: Disclosed are methods and systems for using hieroglyphs for communication in a rapid fabrication environment. The method includes receiving, by a control system for an articulated robotic arm, one or more images of a fabrication machine build space. The method includes identifying, by the control system, a hieroglyph present in the one or more images and translating the identified hieroglyph into one or more instructions for manipulation of the articulated robotic arm. The method includes causing the articulated robotic arm to carry out the instructions translated from the identified hieroglyph. Accordingly foreign objects are inserted into fabricated objects during an automated rapid fabrication process without extensive redesign of the rapid fabrication machine. In some implementations, an unmodified third-party stereolithographic rapid fabrication machine can be used.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: Northeastern University
    Inventors: Brian Weinberg, Constantinos Mavroidis
  • Patent number: 8838263
    Abstract: The unique advantages of computer-controlled fabrication of a patient-specific orthotic device using an automated fabrication machine capable of following computer instructions to create 3D surface contours and new developments in non-invasive three-dimensional (3D) scanning have made it possible to acquire digital models of freeform surfaces such as the surface anatomy of the human body and to then fabricate such a patient-specific device with high precision. Such a patient-specific device brings significant improvement in patient-specific fit, comfort, and function of medical devices (and, in particular, to orthoses that require a close fit to the wearer's body to act effectively). The combination of these two technologies is ideally suited for the development of patient-specific orthotic devices. A patient specific ankle-foot orthotic device using this technology is disclosed. This exemplary device is used to help stabilize the ankle-foot region, for example, in patients with impaired gait.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: September 16, 2014
    Assignees: Spaulding Rehabilitation Hospital Corporation, Northeastern University, Technest Holding, Inc.
    Inventors: Mark L. Sivak, Richard G. Ranky, Joseph A. DiPisa, Alyssa Leigh Caddle, Kara Lyn Gilhooly, Lauren Chiara Govoni, Seth John Sivak, Michael Lancia, Paolo Bonato, Constantinos Mavroidis
  • Patent number: 8832611
    Abstract: Systems and methods for process aware metrology are provided. One method includes selecting nominal values and one or more different values of process parameters for one or more process steps used to form the structure on the wafer, simulating one or more characteristics of the structure that would be formed on the wafer using the nominal values, and determining parameterization of the optical model based on how the one or more characteristics of the structure vary between at least two of the nominal values and the one or more different values.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: September 9, 2014
    Assignee: KLA-Tencor Corp.
    Inventors: Xuefeng Liu, Yung-Ho Alex Chuang, John Fielden, Bin-Ming Benjamin Tsai, Jingjing Zhang
  • Patent number: 8806394
    Abstract: Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing projection optics characteristics. The projection optics can be used to shape wavefront in the lithographic projection apparatus. According to the embodiments herein, the methods can be accelerated by using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs).
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: August 12, 2014
    Assignee: ASML Netherlands B.V.
    Inventors: Hanying Feng, Yu Cao, Jun Ye
  • Patent number: 8756536
    Abstract: The present invention provides a generation method of generating data for a mask pattern to be used for an exposure apparatus including a projection optical system for projecting a mask pattern including a main pattern and auxiliary pattern onto a substrate, including a step of setting a generation condition under which the auxiliary pattern is generated, and a step of determining whether a value of an evaluation function describing an index which indicates a quality of an image of the mask pattern calculated, wherein if it is determined that the value of the evaluation function falls outside a tolerance range, the generation condition is changed to set a new generation condition.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: June 17, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tadashi Arai
  • Patent number: 8738166
    Abstract: There is provided a method for manufacturing a three-dimensional shaped object. The method of the present invention comprises the repeated steps of: (i) forming a solidified layer by irradiating a predetermined portion of a powder layer on a base plate with a light beam, thereby allowing a sintering of the powder in the predetermined portion or a melting and subsequent solidification thereof; and (ii) forming another solidified layer by newly forming a powder layer on the resulting solidified layer, followed by the irradiation of a predetermined portion of the powder layer with the light beam; wherein the solidified layers are formed such that they have a high-density portion whose solidified density is 95 to 100% and a low-density portion whose solidified density is 0 to 95% (excluding 95%); and wherein the high-density portion is a portion of the three-dimensional shaped object, to which the force is applied when the three-dimensional shaped object is used.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: May 27, 2014
    Assignee: Panasonic Corporation
    Inventors: Satoshi Abe, Masataka Takenami, Isao Fuwa, Yoshikazu Higashi, Norio Yoshida
  • Patent number: 8713489
    Abstract: A parameter correction method includes: obtaining, from a variability-aware simulation, a simulation result value of a predetermined product performance for a reference candidate value set concerning statistics of predetermined product characteristics; calculating a likelihood by substituting the reference candidate value set, the obtained simulation result value, statistics of measurement values of the predetermined product characteristics and a measurement value of the predetermined product performance into a likelihood function that is defined from a probability density function for the statistics of the predetermined product characteristics and a probability density function for the predetermined product performance, and is a function to calculate a combined likelihood of the statistics of the predetermined product characteristics and the predetermined product performance; and searching for a reference candidate value set in case where the calculated likelihood becomes maximum, by carrying out the obtaini
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: April 29, 2014
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Higuchi, Hidetoshi Matsuoka
  • Patent number: 8703037
    Abstract: A solid imaging apparatus and method employing sub-pixel shifting in multiple exposures of the digitally light projected image of a cross-section of a three-dimensional object on a solidifiable liquid medium. The multiple exposures provide increased resolution, preserving image features in a three-dimensional object and smoothing out rough or uneven edges that would otherwise be occur using digital light projectors that are limited by the number of pixels in an image projected over the size of the image. Algorithms are used to select pixels to be illuminated within the boundary of each image projected in the cross-section being exposed.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: April 22, 2014
    Assignee: 3D Systems, Inc.
    Inventors: Charles W. Hull, Jouni P. Partanen, Charles R. Sperry, Patrick Dunne, Suzanne M. Scott, Dennis F. McNamara, Chris R. Manners
  • Patent number: 8707222
    Abstract: In an electronic design automation technique for optical proximity correction, a mask is represented by a function with an exact analytical form over a mask region. Using the physics of optical projection, a solution based on a spatial frequency analysis is determined. Spatial frequencies above a cutoff are determined by the optical system do not contribute to the projected image. Spatial frequencies below this cutoff affect the print (and the mask), while those above the cutoff only affect the mask. Frequency components in the function below this cutoff frequency may be removed, which will help to reduce computational complexity.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: April 22, 2014
    Assignee: Gauda, Inc.
    Inventors: P. Jeffrey Ungar, Ilhami H. Torunoglu
  • Patent number: 8707221
    Abstract: Embodiments of the invention include systems and methods for automatically predicting production yield for a circuit assembly according to attributes of its components and defect data mapped thereto. Embodiments receive a proposed design specification for a circuit assembly, including bill of materials (BOM) and schematic data, at a yield prediction environment. The yield prediction environment maps a set of attributes to each component in the BOM and maps a set of possible defects to each component according to its attributes. Defects may be further mapped to a manufacturing process assigned to populate each component in the circuit assembly. The defects are associated with predicted frequencies of occurrence, which can be used to roll up a yield prediction for the circuit assembly. Embodiments further allow “what-if” analyses to be performed so that different yield prediction results can be compared according to different form factor options and/or different manufacturing process options.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: April 22, 2014
    Assignee: Flextronics AP, LLC
    Inventor: Michael Anthony Durkan
  • Patent number: 8694929
    Abstract: A method and an apparatus for determining the position of a structure on a mask for microlithography, in which the position is determined by comparing an aerial image, measured by a recording device, of a portion of the mask with an aerial image determined by simulation. The position determination includes carrying out a plurality of such comparisons which differ from one another with regard to the input parameters of the simulation.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: April 8, 2014
    Assignees: Carl Zeiss SMT GmbH, Carl Zeiss SMS GmbH
    Inventors: Dirk Seidel, Michael Arnz
  • Patent number: 8694927
    Abstract: A method of designing a pattern layout includes defining one shot area including a plurality of chip areas, generating an initial common layout in the plurality of chip areas, primarily correcting the initial layout to form a primary corrected layout, and secondarily correcting the primary corrected layout independently to form a plurality of secondary corrected layouts.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: April 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Moon-Gyu Jeong
  • Patent number: 8689157
    Abstract: Some embodiments of the invention provide a method for verifying an integrated circuit (IC) design. The method receives a process description file that specifies a process technology for building the IC. The process description file describes a particular device type in which a first conductor overlaps a second conductor by recessing from the second conductor in one or more cut-outs. Based on the process description file, the method finds a section of the IC design that matches the particular device type and uses the description of the particular device type to compute a capacitance value and a resistance value for the section of the IC design.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: April 1, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chi-Yuan Lo, Mikhail Khapaev
  • Patent number: 8667430
    Abstract: A method of fabricating an integrated circuit includes designing an optical photomask for forming a pre-pattern opening in a photoresist layer on a semiconductor substrate, wherein the photoresist layer and the pre-pattern opening are coated with a self-assembly material that undergoes directed self-assembly (DSA) to form a DSA pattern. Designing the optical photomask includes using a computing system, inputting a DSA target pattern, and using the computing system, applying a DSA model to the DSA target pattern to generate a first DSA directing pattern. Further, the step of designing the optical photomask includes using the computing system, calculating a residual between the DSA target pattern and the DSA directing pattern, and using the computing system, applying the DSA model to the first DSA directing pattern and the residual to generate a second, updated DSA directing pattern. Generating the second, updated DSA directing pattern includes linearizing a self-consistent field theory equation.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventor: Azat Latypov
  • Patent number: 8667428
    Abstract: In an exemplary embodiment, a method of fabricating an integrated circuit includes designing an optical photomask for forming a pre-pattern opening in a photoresist layer on a semiconductor substrate, wherein the photoresist layer and the pre-pattern opening are coated with a self-assembly material that undergoes directed self-assembly (DSA) to form a DSA pattern. The step of designing the optical photomask includes using a computing system, inputting a DSA target pattern, and using the computing system, applying a DSA model to the DSA target pattern to generate a first DSA directing pattern. Further, the step of designing the optical photomask includes using the computing system, calculating a residual between the DSA target pattern and the DSA directing pattern, and using the computing system, applying the DSA model to the first DSA directing pattern and the residual to generate a second, updated DSA directing pattern.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventor: Azat Latypov
  • Patent number: 8656320
    Abstract: A method for creating a photolithography mask from a set of initial mask cells arranged to form an initial mask. The set includes first and second initial mask cells having a mask element in common within an initial region of the initial mask. The method includes a creation of a first modified mask cell and of a second modified mask cell including OPC processing operations, a comparison of the position of the mask element in common between the first modified mask cell and the second modified mask cell, and if the result of the comparison is greater than a threshold, a creation of a new mask region including an optical proximity correction processing operation on the initial region, and a creation of the photolithography mask from the new mask region.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: February 18, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Christian Gardin
  • Patent number: 8627243
    Abstract: Methods for optimizing conductor patterns for conductors formed by ECP and CMP processes. A method includes receiving layout data for an IC design where electrochemical plating (ECP) processes form patterned conductors in at least one metal layer over a semiconductor wafer; determining from the received layout data a global effects factor corresponding to a global pattern density; determining layout effects factors for unit grid areas corresponding to the pattern density of the at least one metal layer within the unit grid areas, determining local effects factors for each unit grid area; using a computing device, executing an ECP simulator using at least one of the global effects factor and the local effects factors, and using the layout effects factor; outputting an predicted post-ECP hump data map from the ECP simulator; and if indicated by a threshold comparison, modifying the layout data.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: January 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Feng Lin, Yu-Wei Chou, Wen-Cheng Huang, Cheng-I Huang, Ching-Hua Hsieh
  • Patent number: 8626328
    Abstract: System, method and computer program product including instructions executed by a processor system for configuring and controlling a facility to perform a manufacturing process and updating a tool controlling the process according to a model employed for mapping calculated coefficients that characterize non-linear variations observed of a product to actual control parameters governing the processes/tools used by the facility during the manufacturing process. In a semiconductor manufacturing process, the method enables real-time control of variation in an exposure step of a patterning process using an exposure tool to minimize a nonlinear variation in one or more pattern attributes by adjusting the exposure tool or the patterning process corresponding to the calculated coefficients. In the method, measurements of product attributes, obtained by finite sampling over a well defined domain (e.g.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventor: Christopher P. Ausschnitt
  • Patent number: 8626330
    Abstract: A method and apparatus for atomic layer deposition (ALD) is described. In one embodiment, an apparatus comprises a vacuum chamber body having a contiguous internal volume comprised of a first deposition region spaced-apart from a second deposition region, the chamber body having a feature operable to minimize intermixing of gases between the first and the second deposition regions, a first gas port formed in the chamber body and positioned to pulse gas preferentially to the first deposition region to enable a first deposition process to be performed in the first deposition region, and a second gas port formed in the chamber body and positioned to pulse gas preferentially to the second deposition region to enable a second deposition process to be performed in the second deposition region is provided.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: January 7, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Barry L. Chin, Alfred W. Mak, Lawrence Chung-Lai Lei, Ming Xi, Hua Chung, Ken Kaung Lai, Jeong Soo Byun
  • Patent number: 8595657
    Abstract: Methods of fabricating a photo mask are provided. The method includes collecting sample data, setting a preliminary mask layout, performing an optical proximity correction using the sample data and a preliminary mask layout to obtain an optimized preliminary mask layout, verifying the optimized preliminary mask layout to obtain a final mask layout, and fabricating the photo mask using the final mask layout. Verification of the optimized preliminary mask layout includes operating a verification simulator using the sample data and the optimized preliminary mask layout as input data to obtain verification image data. The verification image data includes a plurality of contours of a pattern at different vertical positions.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: November 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hosun Cha, Eunmi Lee, Sungwoo Lee
  • Patent number: 8589830
    Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving an IC design layout having a feature with an outer boundary, performing a dissection on the feature to divide the outer boundary into a plurality of segments, and performing, using the segments, an optical proximity correction (OPC) on the feature to generate a modified outer boundary. The method also includes simulating a photolithography exposure of the feature with the modified outer boundary to create a contour and performing an OPC evaluation to determine if the contour is within a threshold. Additionally, the method includes repeating the performing a dissection, the performing an optical proximity correction, and the simulating if the contour does not meet the threshold, wherein each repeated dissection and each repeated optical proximity correction is performed on the modified outer boundary generated by the previously performed optical proximity correction.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: November 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chang, Chin-Min Huang, Wei-Kuan Yu, Cherng-Shyan Tsay, Lai Chien Wen, Hua-Tai Lin
  • Patent number: 8584344
    Abstract: A method of forming a functional razor cartridge for repeated shaving comprises rapid prototyping a housing of a razor cartridge. The housing has a front wall, a rear wall and opposing side walls disposed transverse to and between said front and rear walls. The method further comprises loading a metal insert with one or more elongate blade assemblies and disposing the metal insert in the housing such that the one or more blade assemblies extend between the opposing side walls of the housing.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: November 19, 2013
    Assignee: The Gillette Company
    Inventors: Mark Peterson, Dominic Michael Piff
  • Patent number: 8589828
    Abstract: A method for reducing layer overlay errors by synchronizing the density of mask material in the frame area across the masks in a set is disclosed. An exemplary method includes creating a mask design database corresponding to a mask and containing a die area with one or more dies and a frame area outside the die area. Fiducial features within the frame area are identified, and from the fiducial features, an idle frame area is identified. A reference mask design, which corresponds to a reference mask configured to be aligned with the mask, is used to determine a reference density for the idle frame area. The idle frame area of the mask design database is modified to correspond to the reference density. The modified mask design database is then available for further use including manufacturing the mask.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: November 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chang Lee, Chia-Jen Chen, Lee-Chih Yeh, Anthony Yen
  • Patent number: 8584057
    Abstract: A method of data preparation in lithography processes is described. The method includes providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid, converting the IC layout design GDS grid to a first exposure grid, applying a non-directional dither technique to the first exposure, coincident with applying dithering to the first expose grid, applying a grid shift to the first exposure grid to generate a grid-shifted exposure grid and applying a dither to the grid-shifted exposure grid, and adding the first exposure grid (after receiving dithering) to the grid-shifted exposure grid (after receiving dithering) to generate a second exposure grid.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: November 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Copmany, Ltd.
    Inventors: Pei-Yi Liu, Shy-Jay Lin, Wen-Chuan Wang, Jaw-Jung Shin, Burn Jeng Lin
  • Publication number: 20130297063
    Abstract: Apparatus for producing an object by sequentially forming thin layers of a construction material one on top of the other responsive to data defining the object, the apparatus comprising: a plurality of printing heads each having a surface formed with a plurality of output orifices and controllable to dispense the construction material through each orifice independently of the other orifices; a shuttle to which the printing heads are mounted; a support surface; and a controller adapted to control the shuttle to move back and forth over the support surface and as the shuttle moves to control the printing heads to dispense the construction material through each of their respective orifices responsive to the data to form a first layer on the support surface and thereafter, sequentially the other layers; wherein each printing head is dismountable from the shuttle and replaceable independently of the other printing heads.
    Type: Application
    Filed: June 4, 2013
    Publication date: November 7, 2013
    Inventors: Eliahu M. KRITCHMAN, Eduardo NAPADENSKY