Abstract: A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to further form a number of elements on a surface of a semiconductor wafer. A pattern on a reticle is first generated using a medium such as computer software to interconnect a number of active areas on the wafer. The pattern is then modified according to a number of rules to create a pattern where substantially all spaces between planned elements exhibit a desired gap width. Layers of elements such as trace lines can be better covered with an ILD in a simplified deposition process as a result of the novel pattern formation described herein.

Abstract: A planar pattern (11), having a plurality of apertures of the same size (Wx×Wy), is determined by a two-dimensional layout determination tool (10), and a three-dimensional structure, having a depth d and an undercut amount Uc for making the phase of the transmitted light be shifted by 180 degrees with every even-numbered aperture, is determined by a three-dimensional structure determination tool (20). Simulation of transmitted light is executed for a structural body having the planar pattern (11) and the three-dimensional structure (21) by a three-dimensional simulator (30) to determine the light intensity deviation D of transmitted light for an odd-numbered aperture without a trench and an even-numbered aperture with a trench. At a two-dimensional simulator (40), simulations using a two-dimensional model prepared based on this deviation D are performed to determine a correction amount ? for making the deviation D zero and obtain a new planar pattern (12).

Abstract: An apparatus for providing gross location, planarization, and mechanical restraint to one or more electronic components such as semiconductor dice to be subjected to stereolithographic processing. A double platen assembly including a first platen and a second platen mutually removably connected and configured and arranged to substantially secure an electronic component assembly in position therebetween. At least one of the platens is configured such that a portion of electronic components of a carrier substrate secured by the double platen assembly is viewable for exposure to an energy beam such as a laser beam used to cure a liquid into an associated dielectric stereolithographic packaging structure. Another embodiment includes the use of an adhesive-coated film for holding, locating and securing a plurality of individual electronic components for processing. A method of forming solder balls is also disclosed.

Abstract: A method and system for performing dummy metal insertion in design data for an integrated circuit is disclosed, wherein the design data includes dummy metal objects inserted by a dummy fill tool. After a portion of the design data is changed, a check is performed to determine whether any dummy metal objects intersect with any other objects in the design data. If so, the intersecting dummy metal objects are deleted from the design data, thereby avoiding having to rerun the dummy fill tool.

Abstract: A programmed material consolidation apparatus includes at least one fabrication site and a material consolidation system associated with the at least one fabrication site. The at least one fabrication site may be configured to receive one or more fabrication substrates, such as semiconductor substrates. A machine vision system with a translatable or locationally fixed camera may be associated with the at least one fabrication site and the material consolidation system. A cleaning component may also be associated with the at least one fabrication site. The cleaning component may share one or more elements with the at least one fabrication site, or may be separate therefrom. The programmed material consolidation apparatus may also include a substrate handling system, which places fabrication substrates at appropriate locations of the programmed material consolidation apparatus.

Abstract: A programmed material consolidation apparatus includes at least one fabrication site and a material consolidation system associated with the at least one fabrication site. The at least one fabrication site may be configured to receive one or more fabrication substrates, such as semiconductor substrates. A machine vision system with a translatable or locationally fixed camera may be associated with the at least one fabrication site and the material consolidation system. A cleaning component may also be associated with the at least one fabrication site. The cleaning component may share one or more elements with the at least one fabrication site, or may be separate therefrom. The programmed material consolidation apparatus may also include a substrate handling system, which places fabrication substrates at appropriate locations of the programmed material consolidation apparatus.

Abstract: A semiconductor manufacturing apparatus includes: a hot plate that heats an article to be processed; a temperature control section that controls temperature of the hot plate; a main body control section that controls the entirety of the apparatus based on a process recipe; and an elevating mechanism that elevates the article to be processed above the hot plate. The semiconductor manufacturing apparatus further includes: a storage section that stores temperature data of the hot plate; an elevation control section that controls the elevating mechanism and sends elevation timing data to the storage section; a management range calculation section that calculates a management range corresponding to parameter behavior in a transient gradient state based on the temperature data, process recipe data, and the elevation timing data; and an abnormality detection section that detects apparatus abnormality with the use of the management range calculated by the management range calculation section.

Abstract: A method for generating a photolithography mask for optically transferring a pattern formed in the mask onto a substrate utilizing an imaging system.

Abstract: Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.

Abstract: Systems and/or methods are disclosed for measuring and/or controlling an amount of impurity that is dissolved within an immersion medium employed with immersion lithography. The impurity can be photoresist from a photoresist layer coated upon a substrate surface. A known grating structure is built upon the substrate. A real time immersion medium monitoring component facilitates measuring and/or controlling the amount of impurities dissolved within the immersion medium by utilizing light scattered from the known grating structure.

Abstract: A method is provided for creating a phase mask for lithographic exposure operations. In this case, phase-shifting regions (10) with a different phase are defined on both sides of critical structures (6), which fall below an extent limit. At least one phase shifter correction is carried out such that at least two mutually facing phase-shifting regions (10) are joined together to form a contiguous phase-shifting region (10) if their distance from one another falls below a predetermined minimum distance.

Abstract: A stereolithographic method which comprises irradiating the surface of a photohardenable resin composition with light through an image drawing mask capable of changing its mask image with the image drawing mask being moved in parallel to the surface of the photohardenable resin composition and the mask image of the image drawing mask being changed in synchronism with the movement of the image drawing mask according to the sectional shape pattern on the photohardened resin layer to be formed to form a photohardened resin layer having a predetermined sectional shape pattern and a stereolithographic apparatus therefor.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.

Abstract: Systems and methods that improve process control in semiconductor manufacturing are disclosed. According to an aspect of the invention, conditions in a cluster tool environment and/or a wafer therein can be monitored in-situ via, for example, a scatterometry system, to determine whether parameters associated with wafer production are within control limits. A cluster tool environment can include, for example, a lithography track, a stepper, a plasma etcher, a cleaning tool, a chemical bath, etc. If an out-of-control condition is detected, either associated with a tool in the cluster tool environment or with the wafer itself, compensatory measures can be taken to correct the out-of-control condition. The invention can further employ feedback/feed-forward loop(s) to facilitate compensatory action in order to improve process control.

Abstract: A multi-layer immersion medium monitoring system for a lithographic process monitors characteristics of an immersion medium of a semiconductor manufacturing process. The multi-layer immersion medium includes at least a first liquid of a first density (or viscosity) and a second liquid of a lower density (or viscosity), both of which are interspersed between a final optical component and a semiconductor layer. The higher density layer is provided to reduce turbulence in the immersion medium during the lithographic processes. A scatterometry system monitors optical characteristics of the multi-layer immersion medium to effectuate control of a lithographic process.

Abstract: A computer implemented method for LSI mask manufacturing stores performance information of a lithography unit, connected to a network, in a lithography unit database. The method receives a lithography data and a lithography reservation condition from a user terminal connected to the network. The method stores the lithography data in a lithography data database. The method searches for a lithography unit matching to the lithography reservation condition, generating a list of lithography units, and sending the list to the user terminal. In addition, the method receives information of a lithography unit specified by the user terminal and sending a lithography request to the lithography unit specified by the user terminal.

Abstract: The invention relates to a process for producing a shaped body by selective laser melting, in which a shaped body is built up from pulverulent metallic material using CAD data of a model, in which a powder layer is applied using an applicator unit, and in which the applied powder layer is fixed to a layer below it using a focused laser beam, in which process the powder layer is levelled to a desired layer thickness as a result of a levelling device passing over the shaped body at least once, and during the levelling elevations that project above the desired layer height of the applied powder, of the layer which was last melted by the laser beam are uncovered by the levelling device.

Abstract: A system is disclosed for monitoring and controlling laser cladding process by powder injection in real-time. The invention combines laser cladding technique along with automated direct feedback control to achieve a good quality clad in terms of dimensional and metallurgical characteristics. The system uses optical CCD-based detectors as the feedback system. The optical CCD-based detectors along with a pattern recognition algorithm is used to determine the clad characteristics in real-time. These characteristics are clad's dimensions, solidification rate, and roughness that are fed into a closed loop control system to adjust the laser power and table velocity to produce desired clad quality.

Abstract: Interactive, computer based orthodontist treatment planning, appliance design and appliance manufacturing is described. A scanner is described which acquires images of the dentition which are converted to three-dimensional frames of data. The data from the several frames are registered to each other to provide a complete three-dimensional virtual model of the dentition. Individual tooth objects are obtained from the virtual model. A computer-interactive software program provides for treatment planning, diagnosis and appliance from the virtual tooth models. A desired occlusion for the patient is obtained from the treatment planning software. The virtual model of the desired occlusion and the virtual model of the original dentition provide a base of information for custom manufacture of an orthodontic appliance.

Abstract: The present invention provides an optical modeling method capable of inhibiting distortion in an object to be modeled and modeling with higher precision. A square exposure region is divided into a plurality of pixels which are further divided into first and second pixel sub-groups, the first pixel sub-group is exposed such that neighboring pixels or more are not exposed at one time, and then unexposed pixels incorporated in the second pixel sub-group are exposed two neighboring pixels or more are not exposed at one time. A photo-curable resin is exposed twice, and then cured in an amount of one photo-curable resin layer. Accordingly, the neighboring pixels are not exposed at one time, the producing of curing shrinkage is limited within one pixel, and distortion due to the curing shrinkage does not spread to the pixels neighboring the one pixel, whereby distortion in the object to be modeled can be inhibited significantly, and modeling with higher precision is made possible.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.

Abstract: A lithography system and method for calculating an optimal discrete time trajectory for a movable device is described. A trajectory planner of the lithography system calculates an optimal discrete time trajectory subject to maximum velocity and maximum acceleration constraints. The trajectory planner begins by calculating a continuous time, three-segment trajectory for a reticle stage, a wafer stage or a framing blade, including a first phase for acceleration at the maximum acceleration to the maximum velocity, a second phase for travel at the maximum velocity and a third phase for deceleration at the negative maximum acceleration to a final velocity. Next, the trajectory planner converts said continuous time, three-segment trajectory to a discrete time trajectory. The time of execution of the resulting trajectory is at most three quanta greater than the time of execution of the continuous time trajectory. One advantage of the system is the reduction of scanning times of a lithography system.

Abstract: A photomask for eliminating antenna effects in an integrated circuit and integrated circuit manufactured with the photomask are disclosed. The photomask includes a substrate and a patterned layer formed on at least a portion of the substrate. The patterned layer may be formed using a mask pattern file created by analyzing a pattern in a mask layout file to identify a region including an antenna ratio less than a first design rule. A feature located in the identified region is moved based on a second design rule from a first position to a second position in the mask layout file to create a space in the identified region. A grounding feature is placed in the space and automatically connected to a gate feature in the mask layout file such that the antenna ratio is increased to greater than or approximately equal to the first design rule.

Abstract: A system and method are disclosed in which a substrate includes a plurality of functional sites, wherein each site comprises a micro-device for handling microcomponent parts. For instance, in a preferred embodiment, functional sites are included on a substrate for at least performing rotational tasks. That is, in a preferred embodiment, a plurality of functional sites are included on a substrate, wherein each functional site comprises a micro-device for handling a microcomponent part presented thereto to perform rotation of the part in some manner. The plurality of micro-devices may be operable to rotate a microcomponent part about various different axes of rotation. For instance, in one embodiment, full rotational handling (rotation about all three axes of a three-dimensional coordinate system) may be provided by the micro-devices.

Abstract: A method for adaptively fabricating a waveguide comprises: measuring misplacement of a photonic device relative to a substrate; generating computer readable instructions for using a plurality of graphics primitives to form the waveguide; and photocomposing the waveguide on the substrate in accordance with the computer readable instructions. A reticle comprises a plurality of graphics primitives with at least one of the plurality of graphics primitives comprising a tapered end. A waveguide comprises a plurality of waveguide segments with each of the plurality of waveguide segments comprising a tapered end and being adjacent to at least one other of the plurality of waveguide segments.

Abstract: The invention relates to a method of improving control over the dimensions of a patterned photoresist, which enables better control of the critical dimensions of a photomask or reticle which is fabricated using the patterned photoresist. In addition, the method may be used to enable improved control over the dimensions of a semiconductor device fabricated using a patterned photoresist. In particular, a patterned photoresist is treated with an etchant plasma to reshape the surface of the patterned photoresist, where reshaping includes the removal of “t”-topping at the upper surface of the patterned resist, the removal of standing waves present on patterned surfaces, and the removal of feet which may be present at the base of the patterned photoresist, where the photoresist contacts an underlying layer such as an ARC layer.

Abstract: A stereolithographic method and apparatus for applying packaging material to workpieces, such as preformed electronic components, including semiconductor dice, with a high degree of precision, and resulting articles. A machine vision system including at least one camera is operably associated with a computer controlling a stereolithographic system for application of material so that the system may recognize the position and orientation of workpieces, such as semiconductor dice, to which the material is to be applied. The requirement for precise mechanical workpiece alignment is eliminated, and the ability of the system to recognize size, configuration and topography of different workpieces affords greater manufacturing flexibility. The method includes stereolithographic application of material for packaging electronic components, and the electronic components so packaged are also part of the invention.

Abstract: In solid freeform fabrication processes that make use of a removable support material, pre-calculation of the amount of support material needed for a build is difficult (inaccurate or slow) because the digital data for generating the support material is often not generated until the build is in progress. A method is proposed that has been shown to generate rapid and accurate estimates of the amount of both build and support material needed before a build begins, to accurately predict before a build begins when replenishment materials are needed, and to track material consumptions over time.

Abstract: A method including determining a first flare convolution based on a feature density of projected structures on a substrate layout, determining a second flare convolution based on a mask for a given substrate layout, determining a system flare variation by summing the first flare convolution and the second flare convolution, and determining a critical dimension variation based on the system flare variation.

Abstract: A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to further form a number of elements on a surface of a semiconductor wafer. A pattern on a reticle is first generated using a medium such as computer software to interconnect a number of active areas on the wafer. The pattern is then modified according to a number of rules to create a pattern where substantially all spaces between planned elements exhibit a desired gap width. Layers of elements such as trace lines can be better covered with an ILD in a simplified deposition process as a result of the novel pattern formation described herein.

Abstract: Disclosed are data processing method, apparatus, and computer readable medium for generating data about mask, reticle, etc., for making exposure, and exposing method, apparatus and computer readable medium for performing exposure during manufacture of LSI, semiconductor device, magnetic device, liquid crystal, etc. When generating revision exposure data from design data, the correction position of revision data is designated and data processing of only designated correction portion is performed. Positional information of correction portion is added to header or footer section of revision exposure data.

Abstract: A method of generating a mask of use in printing a target pattern on a substrate. The method includes the steps of (a) determining a maximum width of features to be imaged on the substrate utilizing phase-structures formed in the mask; (b) identifying all features contained in the target pattern having a width which is equal to or less than the maximum width; (c) extracting all features having a width which is equal to or less than the maximum width from the target pattern; (d) forming phase-structures in the mask corresponding to all features identified in step (b); and (e) forming opaque structures in the mask for all features remaining in target pattern after performing step (c).

Abstract: A method, system, and computer program product for non-real-time trajectory planning and real-time trajectory execution. A trajectory planning process receives data generated by high-level control software. This data defines positions and scan velocities, where multiple axis motion must be precisely synchronized. The trajectory planning process creates sequences of constant acceleration intervals that allow critical motions to be executed at maximum throughput. The output of a trajectory planning process is known as a profile. A profile executor, using the profile output by the trajectory planner process, generates continuous, synchronized, filtered, multi-axis position and acceleration commands (i.e., execution data) that drive control servos. Time intervals generated by the trajectory planner are quantized to be integer multiples of a real time clock period.

Abstract: In one embodiment of the invention, a method of manufacturing a semiconductor device comprises the steps of: a) providing an organic semiconductor layer; b) depositing a reactive species on a portion of the organic semiconductor layer; and c) reacting the reactive species with the portion of the organic layer to form a dielectric layer.

Abstract: Methods for the preparation of multilayered resists are described. To efficiently pattern large contiguous areas rapidly, a procedure has been developed using spot-size modulation of the focused laser beam to more efficiently pattern interior portions. Critical portions at the perimeter are patterned at high resolutions. The spot-size is progressively increased towards the interior allowing a controlled transition to coarser spot-sizes without impacting the exposure dose in critical portions. Patterning times are significantly reduced since in effect shells are patterned. An algorithm is defined to subdivide a layer into different zones, determine the appropriate focused spot-sizes used for each zone, and define the laser scan trace within a zone to enable efficient patterning of broad areas in positive tone resists.

Abstract: A method of optimizing production of semiconductor devices on a wafer comprises steps of characterizing at least one effect of at least one manufacturing component on at least one optimization criterion; inputting user optimization data; and, based on the at least one effect and the user optimization data, performing optimization to determine a layout of semiconductor devices on the wafer that optimizes performance according to the user optimization data.

Abstract: A layout pattern generating unit within a lithography process margin evaluating apparatus generates a plurality of design layout patterns, using an analysis condition and information stored in a layout pattern template holding unit. In addition, a simulation condition generating unit generates a plurality of simulation conditions, using the analysis condition and information stored in a simulation condition template holding unit. A simulation unit generates a plurality of actual layout patterns, using a generated condition. Thus, the lithography process margin evaluating apparatus can reduce operational burden and improve accuracy.

Abstract: A solid freeform fabrication method and apparatus for making objects in a layer by layer manner in which the objects have special geometrical features requiring specialized control parameters. The method and apparatus automatically determines and selects the build parameters for the build process based on automatic part feature recognition. A general build style is first determined having a plurality of default parameters for building the object. Data representing the object is imported and oriented with a Z-axis. The data is then processed by slicing software that automatically identifies special build types for specific ranges of Z-values and selects the alternative parameters needed to successfully build these features. Preferably a look-up table contains special sets of values for the parameters for each special build type possible in which the slicing algorithm can select from. During slicing, operator intervention is not needed to prepare all the parameters necessary for a successful build.

Abstract: One embodiment of the invention provides a system that facilitates optical proximity correction for alternating aperture phase shifting designs. During operation, the system receives a layout, which includes a complementary mask and a phase shifting mask. A subset of trim features on the complementary mask that are designed to protect the dark areas left unexposed by the phase shifting mask are adjusted first using a rules-based optical proximity correction process. This is then supplemented by a model-based correction to the phase shifters, Additionally, the portions of the trim that are co-extensive with the original layout can be corrected, e.g. at the time of the correction of the complementary mask using either rule or model based corrections.

Abstract: A management system including a plurality of semiconductor exposure apparatuses is provided for controlling various exposures in manufacturing a semiconductor device. When plural numbers of times of exposure are performed, the management system determines a combination of semiconductor exposure apparatuses having the most appropriate exposure condition for each number of times of exposure based on a distortion generated in the semiconductor exposure apparatus.

Abstract: A programmed material consolidation apparatus includes at least one fabrication site and a material consolidation system associated with the at least one fabrication site. The at least one fabrication site may be configured to receive one or more fabrication substrates, such as semiconductor substrates. A machine vision system with a translatable or locationally fixed camera may be associated with the at least one fabrication site and the material consolidation system. A cleaning component may also be associated with the at least one fabrication site. The cleaning component may share one or more elements with the at least one fabrication site, or may be separate therefrom. The programmed material consolidation apparatus may also include a substrate handling system, which places fabrication substrates at appropriate locations of the programmed material consolidation apparatus.

Abstract: A method of producing an article formed from a photosensitive polymer resin, the article having at least two different densities and the article being a unitary article having substantially no structural joint between regions of different density.

Abstract: A programmed material consolidation apparatus includes at least one fabrication site and a material consolidation system associated with the at least one fabrication site. The at least one fabrication site may be configured to receive one or more fabrication substrates, such as semiconductor substrates. A machine vision system with a translatable or locationally fixed camera may be associated with the at least one fabrication site and the material consolidation system. A cleaning component may also be associated with the at least one fabrication site. The cleaning component may share one or more elements with the at least one fabrication site, or may be separate therefrom. The programmed material consolidation apparatus may also include a substrate handling system, which places fabrication substrates at appropriate locations of the programmed material consolidation apparatus.

Abstract: A hearing device for inserting into or adjacent to the ear of an individual. A shell is custom-shaped to fit the individual. The shell is made mainly of a first material and includes a part made mainly of the first material. The part has an inner surface. A pattern of embossments or indentations is provided in the inner surface. The pattern is made out of the first material. The pattern represents an individualized identification code of the part or the device. The pattern is generated concurrent to the manufacture of said part. The pattern can be generated using a laser sintering process, a laser lithography process, a stereo lithography process, or a thermojet process.

Abstract: Methods and systems for treating teeth include capturing a digital dental model taken within an oral cavity; modifying the digital model in planning a dental treatment or in designing a dental prosthetic; and creating a physical model from the original or modified digital models.

Abstract: A trough adjusted optical proximity correction for vias which takes into account the topography on a wafer created by prior processing. The vias are classified into one of two groups, coincident vias which have an edge coincident with an edge of the trough, and noncoincident vias which do not have an edge coincident with an edge of the trough, by analyzing the via and trough designs. Any coincident via is marked as valid for an optical proximity correction (OPC). Any noncoincident via is marked invalid for OPC. OPC is then performed to the via level. Only vias marked as valid for OPC will keep the correction. All other vias will keep their original design size. Alternatively, coincident vias can be simply treated differently from noncoincident vias. For instance, coincident vias can be subjected to an aggressive OPC correction, while noncoincident vias are subjected to a less aggressive OPC correction.