Abstract: Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The signal is then returned to the SoC, where it may be examined by a closed-loop engine of the SoC. A result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

Abstract: A semiconductor memory device which stores operation environment information such as use time data, operating temperature data, or operating voltage data includes an internal circuit configured to perform a function set in the semiconductor memory device, and an operation environment information storing circuit configured to sense information about an operation environment of the semiconductor memory device when the semiconductor memory device operates, store the operation environment information in non-volatile memory cells, and provide the operation environment information stored in the non-volatile memory cells to an outside based on a request of reading out information.

Abstract: This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or pages. By performing a test transaction to program each bit of each such unit, the maximum expected programming time of each unit may be determined in advance and used for scheduling purposes. For example, in a straightforward implementation, a relatively accurate, empirically measured time limit may be identified and used to efficiently manage and schedule flash memory transactions without awaiting ultimate resolution of attempts to write to a non-responsive page. This disclosure also provides other uses of empirically-measured maximum flash memory transaction times, including via multiple memory modes and prioritized memory; for example, if a high performance mode is desired, low variation in flash memory transaction times may be tolerated, and units not satisfying these principles may be marked relatively quickly.

Abstract: A method for projecting an electron beam used notably in lithography by direct or indirect writing as well as in electron microscopy, is provided. Notably for critical dimensions or resolutions of less than 50 nm, the proximity effects created by the forward and backward scattering of the electrons of the beam in interaction with the target must be corrected. This is traditionally done using the convolution of a point spread function with the geometry of the target. In the prior art, said point spread function uses Gaussian distribution laws. At least one of the components of the point spread function is a linear combination of Voigt functions and/or of functions approximating Voigt functions, such as the Pearson VII functions. In certain embodiments, some of the functions are centered on the backward scattering peaks of the radiation.

Abstract: An air flow meter has a housing, a flow rate sensor, and a physical-quantity measuring sensor. The housing therein defines a bypass passage into which a part of air flowing in a duct flows. The flow rate sensor is disposed in the bypass passage. The physical-quantity measuring sensor measures a physical quantity of air flowing in the duct and is disposed separately from the flow rate sensor. The housing has a recessed portion that is recessed from an inner wall surface of the bypass passage and that has a blind-passage shape. The physical-quantity measuring sensor is disposed in the recessed portion.

Abstract: A power over Ethernet (PoE) connection check method comprising: for a first time period, generating a first detection power over the first set of wires while not generating a second detection power over the second set of wires and obtaining a first indication of a power attribute over the first set of wires; during a second time period, generating the first detection power and generating a second detection power, greater than the first detection power, over the first set of wires; during the second time period, obtaining a second indication of the power attribute over the first set of wires; determining a first difference between the first indication and the second indication; and controlling a first power enable circuit and a second power enable circuit to provide power to the powered device over the first and second sets of wires respectively, responsive to the determined difference.

Abstract: A method of operating a test device for a logic-based processing device includes the steps of providing an original set of test instructions, generating one or more Quick Error Detection (QED) test programs, and causing the one or more QED test programs to be executed on the logic-based processing device. Each one of the QED test programs includes the original test program with additional instructions inserted at strategic locations within the original set, wherein the additional instructions and the strategic locations vary between each of the QED test programs.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.

Abstract: A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

Abstract: A method for monitoring a power supply connected to a superordinate controller via a signal line, wherein the superordinate controller queries whether the power supply is operating faultlessly at variable intervals, where during faultless operation, a power-good signal is continuously transmitted by the power supply to the superordinate controller via the signal line and, if a fault occurs, an indicating signal is transmitted by the power supply to the superordinate controller via the signal line as a switching sequence of high and low signals such that each signal change of the switching sequence occurs only after a time period that is longer than an expected greatest query interval and each signal of the switching sequence that does not correspond to the power-good signal is shorter than a specified signal duration for indicating a total failure of the power supply, whereby the superordinate controller receives more information than previously.

Abstract: An electronic device is provided. The electronic device includes a printed circuit board (PCB), an antenna structure, a radio frequency signal transceiving circuit and a testing structure. The antenna structure is disposed on the PCB. The radio frequency signal transceiving circuit is disposed on the PCB, and is connected to the antenna structure through a conductive line. The testing structure includes a testing point and a grounding structure. The testing point is disposed on the conductive line, and the grounding structure is disposed on the PCB.

Abstract: The operation of electrical appliances receiving electrical power from an electrical system may be indirectly monitored using monitoring units engaged with outlets on branch circuits of the electrical system. Electrical systems providing power to appliances to be monitored in accordance with the present invention may comprise split phase alternating current systems, tri-phase systems, or any other type of electrical system. Known loads may be applied to calibrate the monitoring system. The monitoring system may measure the power consumption of appliances operating on the electrical system and/or detect possible fault conditions. The monitoring system may be distributed across multiple monitoring units and other computing devices. Output devices may be used to output a summary of the power consumption or other operation of monitored electrical appliances.

Abstract: On-chip field testing methods and apparatus are disclosed. Example on-chip testers disclosed herein include a decoder having a test data input and a test stimuli interface. Disclosed example on-chip testers also include a multiplexer having a first multiplexer interface coupled to the test stimuli interface, a second multiplexer interface coupled to an automatic test equipment interface, a third multiplexer interface coupled to a design-for-testing subsystem interface and an interface selection input. Disclosed example on-chip testers further include a memory having a memory interface coupled to the test data input.

Abstract: Necessary unit data indicative of the type and number of equipment units used in component mounting operation is obtained on the basis of production plan data, mounting data, and component library for each of production lots in advance. New allocation processing for allocating an equipment unit necessary for production execution of a new production lot to be newly produced on an electronic component mounting line for the new production lot on the basis of the necessary unit data is executed, and component reservation processing for registering the allocation result as the inventory data is conducted by a unit reservation unit.

Abstract: A built-in self-test circuit includes a command storage unit that stores commands inputted from an external device, an input/output control unit that controls the command storage unit to sequentially store the commands and sequentially output stored commands as internal commands in a test operation, and a command decoder unit that decodes the internal commands outputted from the command storage unit and outputs a test command.

Abstract: A magnetic current sensor calibration system includes a plurality of sensors and a substrate. The substrate has a first surface and a second surface, and the sensors are mounted on the first surface. The substrate includes a bipolar calibration conductor and a unipolar calibration conductor. The bipolar calibration conductor is spaced apart from the plurality of sensors and is disposed between the first and second surfaces. The unipolar calibration conductor is spaced apart from the plurality of sensors and the bipolar calibration conductor, and is disposed between the first and second surfaces.

Abstract: A method for diagnosing an electrical circuit including at least one electrical device, an actuator for the device controlled by a high side actuating switch and a low side actuating switch, and at least one additional switch not in series with any of the HS or LS switch, the method including: to each of the possible statuses of the circuit, giving a code; sequentially putting the circuit in at least some of these statuses for a given time period; during each of these periods, measuring voltage and/or current in different parts of the circuit and giving a code to the measurement; and establishing a diagnosis of correct functioning or of a malfunctioning of at least some elements of the circuit according to a pre-established correlation between the status codes and the measurement codes.

Abstract: The invention provides methods and devices that address problems encountered when attempting to accurately reconstruct visual stimuli being displayed to a user as they interact with online-content, typically through a browser interface. In one embodiment, the invention provides for the browser to maintain a record of selected technical parameters and relevant data that may impact the manner in which online-content is being displayed to the user, taking into consideration the current context in which the browser is being operated. In another embodiment, the invention is a device for recording events as reported from a browser interface. The events are recorded in a selected format and syntax to form a primary index of events and related outcomes which comprise the users interface experience. In operation, the devices detect events as detected at the browser interface. Next, the devices identify, categorize, and filter detected events as to their relevance to the visual stimuli being presented to the user.

Abstract: Methods and apparatus for processing a signal comprise at least one circuit configured to generate a measured signal during a measured time period and a reference signal during a reference time period. Also included is at least one dual- or multi-path analog-to-digital converter comprising at least a first processing circuit configured to process the measured signal, at least a second processing circuit configured to process the reference signal, and a third processing circuit configured to process both the measured signal and the reference signal.

Abstract: The disclosed approaches compile a hierarchical representation of a circuit design into a flattened netlist and store the flattened netlist a memory circuit. The circuit design instantiates a plurality of memory blocks of a target device and specifies logic circuits that access the plurality of memory blocks, respectively. The flattened netlist is modified by determining a subset of the plurality of memory blocks. The quantity of memory reserved in each memory block of the subset is less than a capacity of said each memory block. One memory block is instantiated, for a pair of the memory blocks of the subset, in place of each memory block of the pair in the flattened netlist in the memory circuit. A portion of the flattened netlist that specifies the logic circuits that access each memory block of the pair is modified to access the one memory block instead of each memory block of the pair.

Abstract: Diagnostic test devices improve communication to a user thereof through provision of audible output. The test device can include a test member, such as lateral flow assay test strip. The test device further includes an electronic communication circuit that can comprise an audio output element as well as a microcontroller. Other elements in the electronic communication circuit includes one or more sensor elements, a display element, and one or more switching elements.—Methods provide indicia for operation of a test device that comprise steps for assembly of a diagnostic test device that provides for audio output.

Abstract: A system for providing a computer language with which to write rules is provided. The system may include a rules container, a rules classes container and an engine/graph. The rules classes container may provide a code library of rules and unit test from which to inherit. The system may also include a rules GUI that may accept code of a rule in a code field window. The rules GUI may also include a documentation presentation window. The documentation presentation window may include a non-editable, reader-friendly view of the rule. Viewing the documentation window adjacent to the code field window may enable a user to understand the code and edit the code. Each rule may depend from another rule or provide a dependency for another rule. The system may save the rules into the rules container. The engine/graph may create a graph of the rules documentation based on the dependencies.

Abstract: Embodiments of the present disclosure provide methods for using a compliance model to determine compatibility of a channel with a bus's chip I/O circuitry at its ends. The method includes identifying at least one design criteria and obtaining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. In certain embodiments, the boundary sets may be derived using a genetic algorithm. The method further includes verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

Abstract: The operation of electrical appliances receiving electrical power from an electrical system may be indirectly monitored using monitoring units engaged with outlets on branch circuits of the electrical system. Electrical systems providing power to appliances to be monitored in accordance with the present invention may comprise split phase alternating current systems, tri-phase systems, or any other type of electrical system. Known loads may be applied to calibrate the monitoring system. The monitoring system may measure the power consumption of appliances operating on the electrical system and/or detect possible fault conditions. The monitoring system may be distributed across multiple monitoring units and other computing devices. Output devices may be used to output a summary of the power consumption or other operation of monitored electrical appliances.

Abstract: Embodiments of the present disclosure provide methods for testing channel compliance. The method generally includes identifying at least one design criteria and determining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. The boundary sets may be used for verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

Abstract: Embodiments of the present disclosure provide apparatus for testing channel compliance. The apparatus generally performs operations that includes identifying at least one design criteria and determining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. The boundary sets may be used for verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

Abstract: Embodiments of the present disclosure provide apparatus for using a compliance model to determine compatibility of a channel with a bus's chip I/O circuitry at its ends. The apparatus includes at least one processor and a memory coupled to the at least one processor. The processor is configured to: identify at least one design criteria; obtain boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria; and verify whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

Abstract: A method for real-time testing of a control unit for an internal combustion engine using a simulator is provided. The control unit and the simulator are connected to one another by a first data channel. The control unit transmits engine control data to the simulator through the first data channel and the simulator calculates engine state variables in real time on its first simulator processor with a first sampling step size and transmits at least some of the engine state variables to the control unit. Thus, selected engine state variables can be made available at a different frequency, and in particular at a higher frequency, than is possible by the first sampling step size of the first simulator processor, in that the simulator calculates at least one specific engine state variable using a partial engine model and with a second sampling step size different from the first sampling step size.

Abstract: A method for testing computing hardware detects the current time as being within a predetermined time period and transfers virtual machines (VMs) from a plurality of physical machines to other physical machines as targets according to a load balancing strategy. The load balancing strategy sums of a load ratio of one physical machine including the VM and a load ratio of one physical machine as a target for the transfer; if the sum of the two ratios is less than a preset load ratio, the VM-transferring physical machine is put into a standby state when the transfer takes place as long as the current time is still inside the predetermined time period. Physical machines which are in the standby state and have not been tested are awoken, and the awoken physical machines are connected to the server for testing.

Abstract: For automated verification of appliance procedures using a processor device in a computing environment, a testing configuration is dynamically configured for automatically testing software by adding and/or removing at least one application device from one of the testing configurations for creating a plurality of appliance configurations.

Abstract: A method for predicting electromagnetic radiation characteristics, a computer-readable recording medium and a simulator are provided. The method includes the steps of obtaining a plurality of first radiation currents in an equivalent circuit model of an electronic component, calculating a radiation resistance according to the first radiation currents, inserting the radiation resistance into the equivalent circuit model, and then obtaining a plurality of second radiation currents in the equivalent circuit model, and predicting electromagnetic radiation characteristics of the electronic component according to the second radiation currents.

Abstract: A difference measurement circuit including a first port and a second port for connection to a first set of nodes and a second set of nodes of a sensor unit. The circuit further includes switching units for switching excitation signals emanating from excitation nodes from being applied to the first set of nodes via the first port to being applied to the second set of nodes via the second port and for switching differential measurement signals measured at sensing nodes from being obtained from the second set of nodes via the second port to being obtained from the first set of nodes via the first port. A corresponding method is described. The circuit further includes redundancy testing circuitry for evaluating the similarity or deviation between measurement signals obtained in different states of the switching units.

Abstract: Methods and apparatuses for performing receive and transmit path tuning of a toggle mode interface between a primary controller and a secondary controller is disclosed. A first component having a variable setting and connected with a data bus of the interface is iteratively adjusted. For each setting of the first component, test data written to the secondary controller and a delay unit having a variable delay setting and connected with a strobe line of the interface is adjusted. Delay settings are identified where the read data is equal to the written data. Settings for the first component and corresponding delay setting that produce the largest range of delay settings where the read data is equal to the written data is selected. The first component may correspond to a driver unit in the primary controller or an ODT unit in the secondary controller.

Abstract: Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.

Abstract: A photo conductive antenna irradiated with light pulse and generating terahertz wave includes a first layer formed by a semi-insulating substrate, a second layer located on the first layer and formed using a material having lower carrier mobility than carrier mobility of the semi-insulating substrate, a first electrode and a second electrode located on the second layer and applying a voltage to the first layer, a first region in which the second layer is formed on the first layer, and a second region in which the second layer is formed on the first layer, wherein the second region is located between the first electrode and the second electrode in a plan view, and the light pulse is applied to the second region.

Abstract: A method is provided for measuring a semiconductor structure, which allows the spatially resolved determination of dark saturation current and/or series resistance and/or resistance of the emitter layer of the semiconductor structure via luminescence measurement, without restrictions being given such that one of the parameters must be known in advance or spatially consistent.

Abstract: The present disclosure generally relates to the automated testing of a system that includes software or hardware components. In some embodiments, a testing framework generates a set of test cases for a system under test using a grammar. Each test case may perform an action, such as provide an input to the system under test, and result in an output from the system under test. The inputs and outputs are then compared to the expected results to determine whether the system under test is performing correctly. Specifically, the system under test may be analyzed to determine whether it is capable of properly processing control instructions and input signals and/or generating expected output control signals and additional control/feedback information. The data can then be interpreted in the grammar system and/or used as input to a fault isolation engine to determine anomalies in the system under test.

Abstract: A testing backplane apparatus includes first test ports configured to receive a first processor assembly under test and the plurality of first test ports may be an even number of first test ports or an odd number of first test ports. The testing backplane apparatus includes second test ports, where each first test port corresponds to a second test port and the second test ports connect to a second processor assembly. The testing backplane apparatus includes a signal pathway from each first test port to a second test port. The signal pathway includes a signal path length within a range between a maximum signal path length and a minimum signal path length. Each port on the first processor assembly corresponds to each port on the second processor assembly and the testing backplane apparatus is configured differently from a backplane used as a final destination for operating the first processor assembly.

Abstract: A serial communication test device, a system including the same, and a method thereof are provided, which relate to a technology that allows a master chip and a slave ship for Serial Peripheral Interface (SPI) communication to double-check data to increase reliability. The serial communication test device includes an interface that is configured to transmit and receive data to and from an external chip. A controller is configured to store data to be error-checked in a register to output the stored data to the external chip through the interface and to store data received from the external chip through the interface in a data storage unit. The controller compares the data stored in the register with the data stored in the data storage unit and determines whether the data stored in the register is substantially similar to data to be error-checked.

Abstract: In a power protection and distribution assembly a trip system monitors electrical current and sends a current status signal to an arc flash protection system indicating whether current characteristic of an arc event is detected. The arc flash protection system evaluates this current status signal along with a light status signal indicating whether light characteristic of an arc event has been detected. Based on this evaluation, the arc flash protection system sends a control signal to the trip system for controlling the trip system to trip a breaker. The systems each include a full-duplex signaling module for sending the signals between the systems over a pair of conductors. Each signaling module sends one of the signals by modulating the magnitude of a current through or a voltage across the conductors, and receives the other signal by demodulating the magnitude of the current through or the voltage across the conductors, as distinctively modulated by the other signaling module.

Abstract: In nonbinary iterative decoding, a data recovery scheme corrects for corrupted or defective data by determining reliability metrics for blocks of decoded nonbinary data. Block or windowed detectors generate block reliability metrics for data blocks (rather than individual bits) of decoded data using soft information from the regular decoding mode or from new iterative decoding iterations performed during defect detection mode. A defect detection system triggers corrective decoding of selected data blocks based on the block reliability metrics, by for example, comparing the block reliability metrics to a threshold or by selecting an adjustable number of the least reliable data blocks.

Abstract: The encoder includes a scale provided with a periodic pattern, a sensor relatively movable with respect to the scale and reading the periodic pattern to output analog signals each having a changing period corresponding to the periodic pattern and having mutually different phases, an A/D converter performing time-division analog-to-digital conversion on the analog signals output from the sensor to produce digital signals, and a phase detector detecting a phase from the digital signals. The encoder further includes a corrector calculating a correction value by using a relative movement speed of the scale and the sensor and the detected phase detected by the phase detector, and calculating a corrected phase from the correction value and the detected phase, and a position detector calculating a position in a direction in which the scale and the sensor are relativity moved by using the corrected phase.

Abstract: A wire harness continuity inspection method includes: specifying a first certain electrical wire and a second certain electrical wire of which one end is connected to the other end of the first certain electrical wire, described in the first region-based connector/wiring information, and regarding them as a single electrical wire; referring to auxiliary device-based wiring information to obtain a first terminal of a first electrical component and a second terminal of a second electrical component connected by a circuit line, which are described in the auxiliary device-based wiring information; referring to the region-based connector/wiring information to specify a first electrical wire of which one end is connected to the first terminal of the first electrical component, described in the region-based connector/wiring information; and determining whether the terminal connected to the other end of the first electrical wire is identical to the second terminal of the second electrical component.

Abstract: A method and apparatus for estimating a height of an epitaxially grown semiconductor material in other semiconductor devices. The method includes epitaxially growing first, second, and third portions of semiconductor material on a first semiconductor device, measuring a height of the third portion of semiconductor material and a height of the first or second portion of semiconductor material, measuring a first saturation current through the first and second portions of semiconductor material, measuring a second saturation current through the first and third portions of semiconductor material, and preparing a model of the first saturation current relative to the height of the first or second portion of semiconductor material and the second saturation current relative to an average of the height of the first and third portions of semiconductor material. The model is used to estimate the height of an epitaxially grown semiconductor material in the other semiconductor devices.

Abstract: Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.

Abstract: A method of storing repair data of a memory array in a one-time programming memory (OTPM) includes performing a first test and repair of the memory array using a built-in self-test-and-repair (BISTR) module to determine first repair data. The method includes loading the first repair data in a repair memory and in a duplicated repair memory of the BISTR module. The method includes performing a second test and repair to determine second repair data. The method includes storing the second repair data in the repair memory of the BISTR module and in the repair memory of the memory array. The method includes processing the repair data in the repair memory and the duplicated repair memory of the BISTR module. The method includes storing the output of the logic gate in the repair memory of the memory array. The method includes storing content of the repair memory in the OTPM.

Abstract: A semiconductor device includes an identification information generation circuit having a power supply control circuit whose output voltage is controlled by a control signal, and a memory array having a first cell power line and a second cell power line. The power supply control circuit outputs a first supply voltage and a second supply voltage to a first cell power line and a second power line, respectively, when the control signal is in a first state, and outputs an intermediate voltage to the first cell power line and the second cell power line when the control signal is in a second state.

Abstract: Techniques and devices for measuring phase noise in radio frequency (RF), microwave, or millimeter signals based on photonic delay.

Abstract: A brightness measuring method of device with backlight is performed by a controlling device, for measuring legends of backlight provided by a backlight module of a device under test (DUT). The method includes turning on a uniform light source external to the DUT for illuminating the DUT; capturing and receiving an image of the DUT illuminated with uniform light as a base image; identifying a complete pattern of a to-be-measured legend in the base image; turning off the uniform light source and turning on the backlight of the DUT so as to illuminate the legend of DUT; capturing and receiving an image of the DUT illuminated with backlight as a comparison image, wherein the scope of the comparison image overlaps the scope of the base image; and calculating brightness values of a plurality of pixels in the comparison image whose positions overlap the positions of the complete pattern.

Abstract: A testing system and a method thereof are provided. The testing system includes an audio/video playback apparatus and a testing apparatus. The audio/video playback apparatus is configured to receive an audio/video signal, and analyze the audio/video signal to generate a signal analysis result and a processed audio/video signal. The processed audio/video signal is configured to be displayed on a screen of the audio/video playback apparatus. The testing apparatus includes a switching module and a determining unit. The switching module controls at least one audio/video transmission interface of the audio/video playback apparatus, so as to select and transmit the corresponding audio/video signal to the audio/video playback apparatus.