Abstract: A magnetic current sensor calibration system includes a plurality of sensors and a substrate. The substrate has a first surface and a second surface, and the sensors are mounted on the first surface. The substrate includes a bipolar calibration conductor and a unipolar calibration conductor. The bipolar calibration conductor is spaced apart from the plurality of sensors and is disposed between the first and second surfaces. The unipolar calibration conductor is spaced apart from the plurality of sensors and the bipolar calibration conductor, and is disposed between the first and second surfaces.

Abstract: Methods and apparatus for processing a signal comprise at least one circuit configured to generate a measured signal during a measured time period and a reference signal during a reference time period. Also included is at least one dual- or multi-path analog-to-digital converter comprising at least a first processing circuit configured to process the measured signal, at least a second processing circuit configured to process the reference signal, and a third processing circuit configured to process both the measured signal and the reference signal.

Abstract: The disclosed approaches compile a hierarchical representation of a circuit design into a flattened netlist and store the flattened netlist a memory circuit. The circuit design instantiates a plurality of memory blocks of a target device and specifies logic circuits that access the plurality of memory blocks, respectively. The flattened netlist is modified by determining a subset of the plurality of memory blocks. The quantity of memory reserved in each memory block of the subset is less than a capacity of said each memory block. One memory block is instantiated, for a pair of the memory blocks of the subset, in place of each memory block of the pair in the flattened netlist in the memory circuit. A portion of the flattened netlist that specifies the logic circuits that access each memory block of the pair is modified to access the one memory block instead of each memory block of the pair.

Abstract: Diagnostic test devices improve communication to a user thereof through provision of audible output. The test device can include a test member, such as lateral flow assay test strip. The test device further includes an electronic communication circuit that can comprise an audio output element as well as a microcontroller. Other elements in the electronic communication circuit includes one or more sensor elements, a display element, and one or more switching elements.—Methods provide indicia for operation of a test device that comprise steps for assembly of a diagnostic test device that provides for audio output.

Abstract: A system for providing a computer language with which to write rules is provided. The system may include a rules container, a rules classes container and an engine/graph. The rules classes container may provide a code library of rules and unit test from which to inherit. The system may also include a rules GUI that may accept code of a rule in a code field window. The rules GUI may also include a documentation presentation window. The documentation presentation window may include a non-editable, reader-friendly view of the rule. Viewing the documentation window adjacent to the code field window may enable a user to understand the code and edit the code. Each rule may depend from another rule or provide a dependency for another rule. The system may save the rules into the rules container. The engine/graph may create a graph of the rules documentation based on the dependencies.

Abstract: Embodiments of the present disclosure provide methods for using a compliance model to determine compatibility of a channel with a bus's chip I/O circuitry at its ends. The method includes identifying at least one design criteria and obtaining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. In certain embodiments, the boundary sets may be derived using a genetic algorithm. The method further includes verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

Abstract: The operation of electrical appliances receiving electrical power from an electrical system may be indirectly monitored using monitoring units engaged with outlets on branch circuits of the electrical system. Electrical systems providing power to appliances to be monitored in accordance with the present invention may comprise split phase alternating current systems, tri-phase systems, or any other type of electrical system. Known loads may be applied to calibrate the monitoring system. The monitoring system may measure the power consumption of appliances operating on the electrical system and/or detect possible fault conditions. The monitoring system may be distributed across multiple monitoring units and other computing devices. Output devices may be used to output a summary of the power consumption or other operation of monitored electrical appliances.

Abstract: Embodiments of the present disclosure provide methods for testing channel compliance. The method generally includes identifying at least one design criteria and determining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. The boundary sets may be used for verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

Abstract: Embodiments of the present disclosure provide apparatus for testing channel compliance. The apparatus generally performs operations that includes identifying at least one design criteria and determining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. The boundary sets may be used for verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

Abstract: Embodiments of the present disclosure provide apparatus for using a compliance model to determine compatibility of a channel with a bus's chip I/O circuitry at its ends. The apparatus includes at least one processor and a memory coupled to the at least one processor. The processor is configured to: identify at least one design criteria; obtain boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria; and verify whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.

Abstract: A method for real-time testing of a control unit for an internal combustion engine using a simulator is provided. The control unit and the simulator are connected to one another by a first data channel. The control unit transmits engine control data to the simulator through the first data channel and the simulator calculates engine state variables in real time on its first simulator processor with a first sampling step size and transmits at least some of the engine state variables to the control unit. Thus, selected engine state variables can be made available at a different frequency, and in particular at a higher frequency, than is possible by the first sampling step size of the first simulator processor, in that the simulator calculates at least one specific engine state variable using a partial engine model and with a second sampling step size different from the first sampling step size.

Abstract: For automated verification of appliance procedures using a processor device in a computing environment, a testing configuration is dynamically configured for automatically testing software by adding and/or removing at least one application device from one of the testing configurations for creating a plurality of appliance configurations.

Abstract: A method for testing computing hardware detects the current time as being within a predetermined time period and transfers virtual machines (VMs) from a plurality of physical machines to other physical machines as targets according to a load balancing strategy. The load balancing strategy sums of a load ratio of one physical machine including the VM and a load ratio of one physical machine as a target for the transfer; if the sum of the two ratios is less than a preset load ratio, the VM-transferring physical machine is put into a standby state when the transfer takes place as long as the current time is still inside the predetermined time period. Physical machines which are in the standby state and have not been tested are awoken, and the awoken physical machines are connected to the server for testing.

Abstract: A method for predicting electromagnetic radiation characteristics, a computer-readable recording medium and a simulator are provided. The method includes the steps of obtaining a plurality of first radiation currents in an equivalent circuit model of an electronic component, calculating a radiation resistance according to the first radiation currents, inserting the radiation resistance into the equivalent circuit model, and then obtaining a plurality of second radiation currents in the equivalent circuit model, and predicting electromagnetic radiation characteristics of the electronic component according to the second radiation currents.

Abstract: A difference measurement circuit including a first port and a second port for connection to a first set of nodes and a second set of nodes of a sensor unit. The circuit further includes switching units for switching excitation signals emanating from excitation nodes from being applied to the first set of nodes via the first port to being applied to the second set of nodes via the second port and for switching differential measurement signals measured at sensing nodes from being obtained from the second set of nodes via the second port to being obtained from the first set of nodes via the first port. A corresponding method is described. The circuit further includes redundancy testing circuitry for evaluating the similarity or deviation between measurement signals obtained in different states of the switching units.

Abstract: Methods and apparatuses for performing receive and transmit path tuning of a toggle mode interface between a primary controller and a secondary controller is disclosed. A first component having a variable setting and connected with a data bus of the interface is iteratively adjusted. For each setting of the first component, test data written to the secondary controller and a delay unit having a variable delay setting and connected with a strobe line of the interface is adjusted. Delay settings are identified where the read data is equal to the written data. Settings for the first component and corresponding delay setting that produce the largest range of delay settings where the read data is equal to the written data is selected. The first component may correspond to a driver unit in the primary controller or an ODT unit in the secondary controller.

Abstract: Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.

Abstract: A photo conductive antenna irradiated with light pulse and generating terahertz wave includes a first layer formed by a semi-insulating substrate, a second layer located on the first layer and formed using a material having lower carrier mobility than carrier mobility of the semi-insulating substrate, a first electrode and a second electrode located on the second layer and applying a voltage to the first layer, a first region in which the second layer is formed on the first layer, and a second region in which the second layer is formed on the first layer, wherein the second region is located between the first electrode and the second electrode in a plan view, and the light pulse is applied to the second region.

Abstract: A method is provided for measuring a semiconductor structure, which allows the spatially resolved determination of dark saturation current and/or series resistance and/or resistance of the emitter layer of the semiconductor structure via luminescence measurement, without restrictions being given such that one of the parameters must be known in advance or spatially consistent.

Abstract: The present disclosure generally relates to the automated testing of a system that includes software or hardware components. In some embodiments, a testing framework generates a set of test cases for a system under test using a grammar. Each test case may perform an action, such as provide an input to the system under test, and result in an output from the system under test. The inputs and outputs are then compared to the expected results to determine whether the system under test is performing correctly. Specifically, the system under test may be analyzed to determine whether it is capable of properly processing control instructions and input signals and/or generating expected output control signals and additional control/feedback information. The data can then be interpreted in the grammar system and/or used as input to a fault isolation engine to determine anomalies in the system under test.

Abstract: A testing backplane apparatus includes first test ports configured to receive a first processor assembly under test and the plurality of first test ports may be an even number of first test ports or an odd number of first test ports. The testing backplane apparatus includes second test ports, where each first test port corresponds to a second test port and the second test ports connect to a second processor assembly. The testing backplane apparatus includes a signal pathway from each first test port to a second test port. The signal pathway includes a signal path length within a range between a maximum signal path length and a minimum signal path length. Each port on the first processor assembly corresponds to each port on the second processor assembly and the testing backplane apparatus is configured differently from a backplane used as a final destination for operating the first processor assembly.

Abstract: A serial communication test device, a system including the same, and a method thereof are provided, which relate to a technology that allows a master chip and a slave ship for Serial Peripheral Interface (SPI) communication to double-check data to increase reliability. The serial communication test device includes an interface that is configured to transmit and receive data to and from an external chip. A controller is configured to store data to be error-checked in a register to output the stored data to the external chip through the interface and to store data received from the external chip through the interface in a data storage unit. The controller compares the data stored in the register with the data stored in the data storage unit and determines whether the data stored in the register is substantially similar to data to be error-checked.

Abstract: In a power protection and distribution assembly a trip system monitors electrical current and sends a current status signal to an arc flash protection system indicating whether current characteristic of an arc event is detected. The arc flash protection system evaluates this current status signal along with a light status signal indicating whether light characteristic of an arc event has been detected. Based on this evaluation, the arc flash protection system sends a control signal to the trip system for controlling the trip system to trip a breaker. The systems each include a full-duplex signaling module for sending the signals between the systems over a pair of conductors. Each signaling module sends one of the signals by modulating the magnitude of a current through or a voltage across the conductors, and receives the other signal by demodulating the magnitude of the current through or the voltage across the conductors, as distinctively modulated by the other signaling module.

Abstract: In nonbinary iterative decoding, a data recovery scheme corrects for corrupted or defective data by determining reliability metrics for blocks of decoded nonbinary data. Block or windowed detectors generate block reliability metrics for data blocks (rather than individual bits) of decoded data using soft information from the regular decoding mode or from new iterative decoding iterations performed during defect detection mode. A defect detection system triggers corrective decoding of selected data blocks based on the block reliability metrics, by for example, comparing the block reliability metrics to a threshold or by selecting an adjustable number of the least reliable data blocks.

Abstract: The encoder includes a scale provided with a periodic pattern, a sensor relatively movable with respect to the scale and reading the periodic pattern to output analog signals each having a changing period corresponding to the periodic pattern and having mutually different phases, an A/D converter performing time-division analog-to-digital conversion on the analog signals output from the sensor to produce digital signals, and a phase detector detecting a phase from the digital signals. The encoder further includes a corrector calculating a correction value by using a relative movement speed of the scale and the sensor and the detected phase detected by the phase detector, and calculating a corrected phase from the correction value and the detected phase, and a position detector calculating a position in a direction in which the scale and the sensor are relativity moved by using the corrected phase.

Abstract: A wire harness continuity inspection method includes: specifying a first certain electrical wire and a second certain electrical wire of which one end is connected to the other end of the first certain electrical wire, described in the first region-based connector/wiring information, and regarding them as a single electrical wire; referring to auxiliary device-based wiring information to obtain a first terminal of a first electrical component and a second terminal of a second electrical component connected by a circuit line, which are described in the auxiliary device-based wiring information; referring to the region-based connector/wiring information to specify a first electrical wire of which one end is connected to the first terminal of the first electrical component, described in the region-based connector/wiring information; and determining whether the terminal connected to the other end of the first electrical wire is identical to the second terminal of the second electrical component.

Abstract: A method and apparatus for estimating a height of an epitaxially grown semiconductor material in other semiconductor devices. The method includes epitaxially growing first, second, and third portions of semiconductor material on a first semiconductor device, measuring a height of the third portion of semiconductor material and a height of the first or second portion of semiconductor material, measuring a first saturation current through the first and second portions of semiconductor material, measuring a second saturation current through the first and third portions of semiconductor material, and preparing a model of the first saturation current relative to the height of the first or second portion of semiconductor material and the second saturation current relative to an average of the height of the first and third portions of semiconductor material. The model is used to estimate the height of an epitaxially grown semiconductor material in the other semiconductor devices.

Abstract: Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.

Abstract: A method of storing repair data of a memory array in a one-time programming memory (OTPM) includes performing a first test and repair of the memory array using a built-in self-test-and-repair (BISTR) module to determine first repair data. The method includes loading the first repair data in a repair memory and in a duplicated repair memory of the BISTR module. The method includes performing a second test and repair to determine second repair data. The method includes storing the second repair data in the repair memory of the BISTR module and in the repair memory of the memory array. The method includes processing the repair data in the repair memory and the duplicated repair memory of the BISTR module. The method includes storing the output of the logic gate in the repair memory of the memory array. The method includes storing content of the repair memory in the OTPM.

Abstract: A semiconductor device includes an identification information generation circuit having a power supply control circuit whose output voltage is controlled by a control signal, and a memory array having a first cell power line and a second cell power line. The power supply control circuit outputs a first supply voltage and a second supply voltage to a first cell power line and a second power line, respectively, when the control signal is in a first state, and outputs an intermediate voltage to the first cell power line and the second cell power line when the control signal is in a second state.

Abstract: Techniques and devices for measuring phase noise in radio frequency (RF), microwave, or millimeter signals based on photonic delay.

Abstract: A brightness measuring method of device with backlight is performed by a controlling device, for measuring legends of backlight provided by a backlight module of a device under test (DUT). The method includes turning on a uniform light source external to the DUT for illuminating the DUT; capturing and receiving an image of the DUT illuminated with uniform light as a base image; identifying a complete pattern of a to-be-measured legend in the base image; turning off the uniform light source and turning on the backlight of the DUT so as to illuminate the legend of DUT; capturing and receiving an image of the DUT illuminated with backlight as a comparison image, wherein the scope of the comparison image overlaps the scope of the base image; and calculating brightness values of a plurality of pixels in the comparison image whose positions overlap the positions of the complete pattern.

Abstract: A testing system and a method thereof are provided. The testing system includes an audio/video playback apparatus and a testing apparatus. The audio/video playback apparatus is configured to receive an audio/video signal, and analyze the audio/video signal to generate a signal analysis result and a processed audio/video signal. The processed audio/video signal is configured to be displayed on a screen of the audio/video playback apparatus. The testing apparatus includes a switching module and a determining unit. The switching module controls at least one audio/video transmission interface of the audio/video playback apparatus, so as to select and transmit the corresponding audio/video signal to the audio/video playback apparatus.

Abstract: A mirrored live-data flow of the live-data flow passing through a selected point within a network is monitored at a first processing node. The live-data flow comprises data that is in active transmission between endpoints in the network and prior to exit from the network and onward storage of the data in a database. Each packet within the mirrored data flow is decoded at the first processing node according to each protocol associated with a packet. Packets having a plurality of protocols associated therewith are decoded in parallel with each other. Each of the decoded packets are compared at the first processing node to a set of predetermined or deduced conditions. A predetermined or deduced response is executed based upon detection of a predetermined or deduced condition within the decoded packets.

Abstract: An entropy source and a random number (RN) generator are disclosed. In one aspect, a low-energy entropy source includes a magneto-resistive (MR) element and a sensing circuit. The MR element is applied a static current and has a variable resistance determined based on magnetization of the MR element. The sensing circuit senses the resistance of the MR element and provides random values based on the sensed resistance of the MR element. In another aspect, a RN generator includes an entropy source and a post-processing module. The entropy source includes at least one MR element and provides first random values based on the at least one MR element. The post-processing module receives and processes the first random values (e.g., based on a cryptographic hash function, an error detection code, a stream cipher algorithm, etc.) and provides second random values having improved randomness characteristics.

Abstract: Techniques are generally disclosed for using an operating entity, including a method, apparatus, and/or system to control usage of the operating entity. In various embodiments, an in-use signal generator may be configured to generate at least one in-use signal, with the at least one in-use signal having a signal duration representative of at least one usage episode of the operating entity. An aging circuit may be coupled to the in-use signal generator and configured to output at least one age-affected signal in response to the at least one in-use signal. A metering module may be coupled to the aging circuit and, in response to the at least one age-affected signal, and configured to measure a signal characteristic of the at least one age-affected signal and translate the signal characteristic into a generated quantity of accumulative usage of the aging circuit.

Abstract: A sound recording device of the present disclosure is can be connected with an external sound pickup device. The sound recording device includes a connector having a plurality of terminals to which the external sound pickup device can be connected, and a determiner that determines a type of the external sound pickup device when the external sound pickup device is connected to the connector, based on a correlation between signals of specific terminals out of the plurality of terminals.

Abstract: An inspecting device inspects an inspecting target that is a semiconductor device or a photo device. The inspecting device includes: a stage for holding an inspecting target; a femtosecond laser for emitting pulsed light; a galvano mirror for obliquely irradiating the inspecting target with the pulsed light, while changing an optical path of the pulsed light, to scan the inspecting target with the pulsed light; and a detection part for detecting an electromagnetic wave emitted non-coaxially with the pulsed light from the inspecting target in accordance with the illumination with the pulsed light.

Abstract: A testing system including a preset display device, preset shutter glasses and a testing device is disclosed. The preset display device generates a synchronization signal and outputs a timing signal relating to the synchronization signal. The preset shutter glasses receive the synchronization signal to generate a masking signal. The testing device processes the timing signal and the masking signal according to a setting signal and determines whether the preset shutter glasses are normal according to the processed result.

Abstract: An integrated circuit device comprises at least one clock monitor. The at least one clock monitor comprises a timer arranged to receive a clock signal, generate a first timing signal arranged to toggle between states in response to a trigger edge of the clock signal, and generate a second timing signal arranged to toggle between states in response to a trigger edge of the clock signal such that a state transition of the second timing signal in response to a trigger edge of the clock signal is delayed by a period T with respect to the trigger edge of the clock signal in response to which that transition occurs. The at least one clock monitor further comprises a detector arranged to receive at a first input thereof the first timing signal, receive at a second input thereof the second timing signal, compare states of the first and second timing signals, and configure an indication of a timing discrepancy based at least partly on the comparison of the first and second timing signals.

Abstract: Some embodiments of the present invention provide techniques and systems for performing aggressive and dynamic scenario reduction during different phases of optimization. Specifically, essential scenarios at gates and timing end-points can be identified and then used during the dynamic scenario reduction process. In some embodiments, margin values associated with various constraints can be used to determine the set of essential scenarios to account for constrained objects that are near critical in addition to the constrained objects that are the worst violators. In some embodiments, at any point during the optimization process, only the set of essential scenarios are kept active, thereby substantially reducing runtime and memory requirements without compromising on the quality of results.

Abstract: Apparatus including functional components of circuitry defined on a semiconductor chip, the functional components including a component having modifiable operating characteristics, a performance measuring circuit providing an output indicative of operating characteristics of the circuitry defined on the semiconductor chip during operation of the circuitry, and computer implemented software means for controlling a value for an operating characteristic of the component having modifiable operating characteristics in response to the output provided by the performance measuring circuit.

Abstract: Automated test procedures, carried out under software control, can be employed to test a device, testing individual pins, and/or groups of pins, to detect and diagnose or characterize various types of failures. A distributed FA system includes a shared database for device definitions, test setups, and test results. Test platforms provide I/O curve tracing which can provide both a qualitative visual representation and a quantitative measured performance. The disclosed system enables and exploits front line testing of devices in the field. Response to the customer can be nearly immediate. Eliminate “false returns” by differentiation of use versus a real quality issue.

Abstract: Described herein are methods and systems for providing corrective maintenance using global knowledge sharing. A method to provide corrective maintenance with a CM system includes performing a query to generate a ranking of fixable causes based on factors (e.g., symptoms, configuration, test). The ranking may be determined based on a fixable cause percent match with the factors. The ranking of fixable causes may be associated with one or more solutions for each fixable cause. The ranking can be updated based on performing tests or solutions.

Abstract: A system for testing a plurality of transistors on a wafer having a storage device or personal computer connected via a bus to a plurality of drivers. Each of the voltage drivers having a microcontroller adapted to receive test parameters and provide test data from a plurality of voltage drivers. By utilizing a bus structure, the personal computer can look on one bus for flags indicating test data is available from a driver and receive the data. In addition a bus may be used to provide test parameters to the drivers. In this manner, multiple drivers may be run at the same time incorporating multiple tests. When data is available it is transferred to the personal computer, for providing test parameters to a plurality of drivers, and connected via a second bus for receiving test results from the plurality of drivers.

Abstract: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

Abstract: A motherboard testing apparatus for testing a motherboard by subjecting it to sequential power-on and power-off modes includes a control module, a switch module and a display module. The control module stores power-on and power-off number of times and outputs control signals accordingly. The switch module provides a first voltage to the motherboard according to the control signals. The switch module includes a photocoupler and a delay. The photocoupler includes an LED and a phototransistor. The delay includes a winding element and a switch element. The display module displays the time periods and the number of times the motherboard abnormally power-on and power-off. The LED receives the control signals. The phototransistor turns on when the LED emits light. The winding element is powered up and closes the switch element. The switch element outputs the first voltage.

Abstract: A High Voltage Interlock Strategy (HVIS) uses feedback current to detect cable connectivity status for a high-voltage cable configured to connect a power conversion circuit with a remote permanent magnet synchronous machine (PMSM). One or more feedback factors are calculated based on detected feedback current. Various algorithms for calculating a feedback factor, and for determining connectivity status based on calculated feedback factors, can be practiced, according to the PMSM operational mode. Fault detection action can be performed in response to detecting a cable disconnect. The HVIS can be implemented by software, making it a safe, economical solution for cable connectivity detection.

Abstract: A panel inspection apparatus and a display panel are provided in the present invention. The panel inspection apparatus includes a data line detecting circuit and a scan line detecting circuit. The data line detecting circuit includes a data line detection switch, a control line of the data line detection switch, and a data line of the data line detection switch. The scan line detecting circuit includes a scan line detection switch, a control line of the scan line detection switch, and a data line of the scan line detection switch. The present invention further provides a display panel. The panel inspection apparatus does not need to be removed after detection of the panel in accordance with the panel inspection apparatus and the display panel of the present invention. Therefore, production costs of the display panel are reduced, and productivity of the display panel is improved.

Abstract: A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.