Abstract: Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.

Abstract: A method for calibrating a DDR memory controller is described. The method provides an optimum delay for a core clock delay element to produce an optimum capture clock signal. The method issues a sequence of read commands so that a delayed version of a dqs signal toggles continuously. The method delays a core clock signal to sample the delayed dqs signal at different delay increments until a 1 to 0 transition is detected on the delayed dqs signal. This core clock delay is recorded as “A.” The method delays the core clock signal to sample the core clock signal at different delay increments until a 0 to 1 transition is detected on the core clock signal. This core clock delay is recorded as “B.” The optimum delay value is computed from the A and B delay values.

Abstract: Some embodiments relate to a wafer. The wafer includes a first dummy component comprising two or more first dummy component transmission lines. One of the first dummy component transmission lines operably couples a first signal test pad to a second signal test pad, and an other of the first dummy component transmission lines operably couples a third signal test pad to a fourth signal test pad. A second dummy component comprises two or more second dummy component transmission lines. One of the second dummy component transmission lines operably couples a fifth signal test pad to a sixth signal test pad, and an other of the second dummy component transmission lines operably couples a seventh signal test pad to an eighth signal test pad. Other embodiments are also disclosed.

Abstract: Efficient production testing of integrated circuits. A first production test is implemented on a group of integrated circuits and failures among the test group are assessed. Specifically, the results of the first test are analyzed such that integrated circuits having a recoverable fail and integrated circuits having a non-recoverable fail are differentiated. The integrated circuits are integrated based on the analyzed results and a second production test is implemented. The second production test tests the integrated circuits responsive to the segregation, such that the second production test is limited only to integrated circuits with a recoverable fail. The next succeeding production test will then use the new test program in the second production test with the handler bin designated as having integrated circuits not to be re-tested.

Abstract: A re-configurable test circuit for use in an automated test equipment includes a test circuit, a test processor and a programmable logic device. The pin electronics circuit is configured to interface the re-configurable test circuit with a DUT. The test processor includes a timing circuit configured to provide one or more adjustable-timing signals having adjustable timing. The programmable logic device is configured to implement a state machine, a state sequence of which depends on one or more input signals received from the pin electronics circuit, to provide an output signal, which depends on a current or previous state of the state machine, to the pin electronics circuit in response to the signal(s) received from the pin electronics circuit. The test processor is coupled to the programmable logic device to provide at least one of the adjustable-timing signal(s) to the programmable logic device to define timing of the programmable logic device.

Abstract: The invention relates to a system for controlling at least one actuator (6) for thrust reverser cowlings (2) on a turbojet engine, comprising a set of actuator and/or control components with at least one actuator (6) for cowlings (2) driven by at least one electric motor (7) and control means (9) for the electric motor (7). The control means (9) comprise test means (20), with an interface (22) destined for receiving test requests from a user. The test means (20) are designed on reception of a test request to carry out a test cycle on one or more components (7, 6, 15, 18) of the system comprising an isolated actuation to the component(s) (7, 6, 15, 18) with regard to the other components of the system.

Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.

Abstract: The present invention provides a method for adjusting a maximum power of a circuit having a first voltage output and a first power. The method includes the following steps: (a) obtaining a voltage coefficient by measuring the first power of the circuit and calculating an open-circuit voltage of the first voltage output; (b) estimating an estimated power based on the voltage coefficient; and (c) repeating the steps (a) to (b) for a specific number of times, in which the specific number of times is determined based on a variation of the estimated power during a time period.

Abstract: A processor link that couples a first processor and a second processor is selected for validation and a plurality of communication parameter settings associated with the first and the second processors is identified. The first and the second processors are successively configured with each of the communication parameter settings. One or more test data pattern(s) are provided from the first processor to the second processor in accordance with the communication parameter setting. Performance measurements associated with the selected processor link and with the communication parameter setting are determined based, at least in part, on the test data pattern as received at the second processor. One of the communication parameter settings that is associated with the highest performance measurements is selected. The selected communication parameter setting is applied to the first and the second processors for subsequent communication between the first and the second processors via the processor link.

Abstract: Disclosed is a test structure that can be used to characterize a specific interface resistance within a multi-layer conductive structure, such as a multi-layer ohmic contact. In the test structure first and second transmission line model (TLM) structures both incorporate a row of essentially identical contact pads separated by spaces with progressively increasing lengths. Conductive mesas, also with progressively increasing lengths, are positioned within the spaces between all but the initial pair of adjacent contacts pads. The first and second TLM structures differ only with respect to the presence of a single conductive layer on each of the conductive mesas. System, method and computer program product embodiments are able to extract resistance parameters associated with the first and second TLM structures, including conductive mesa to conductive layer interface resistances, based current-voltage measurements acquired from both of the TLM structures.

Abstract: A magnetic field sensor includes built in self-test circuits that allow a self-test of most of, or all of, the circuitry of the magnetic field sensor, including self-test of a magnetic field sensing element used within the magnetic field sensor, while the magnetic field sensor is functioning in normal operation.

Abstract: A method includes reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit as part of verification thereof. The method also includes extracting, through the processor, a set of optimized instructions of a test algorithm involved in the verification such that the set of optimized instructions covers a maximum portion of logic functionalities associated with the design of the electronic circuit. Further, the method includes executing, through the processor, the test algorithm solely relevant to the optimized set of instructions to reduce a verification time of the design of the electronic circuit.

Abstract: A method includes providing on a substrate having at least two through substrate vias (“TSVs”) a plurality of test structures for de-embedding the measurement of the intrinsic characteristics of a device under test (DUT) including at least two of the TSVs; measuring the intrinsic characteristics [L] for a first and a second test structure on the substrate including two pads coupled with a transmission line of length L; using simultaneous solutions of ABCD matrix or T matrix form equations, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the pads and the transmission lines; de-embedding the measurements of the third and fourth test structures using the intrinsic characteristics of the pads and the transmission lines; and using simultaneous solutions of ABCD matrix or T matrix form equations for BM_L and BM_LX, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the TSVs.

Abstract: A test apparatus that tests a device under test, including a control apparatus that controls testing of the device under test, a test unit that sends and receives signals to and from the device under test, and a buffer section that buffers access requests transmitted from the control apparatus to the test unit and, prior to completion of a write request to a predetermined buffer control address from the control apparatus, issues previously buffered access requests to the test unit side.

Abstract: The invention described here enables in-operation, low-cost, non-invasive measurement of component performance and condition for assessing device longevity prediction, resilience and reliability. The non-invasive component measurements to be performed and subsequently evaluated are based on at least a set of physically unclonable functions and other measurements which can be error corrected, and the error correction factor and other measurements provides insight to the device condition. The system as well is adaptive and allows the introduction of new measurements across not only similar components but to include the family of components similarly fabricated.

Abstract: A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ interface with one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.

Abstract: Techniques for improving parametric chip yield of manufactured chips are provided. In one aspect, a method for optimizing parametric chip yield is provided. The method includes the following steps. Parametric chip yield is computed based on performance and power consumption of a plurality of manufactured chips subject to a given voltage binning scheme. It is then determined whether the parametric chip yield computed is optimal. If the parametric chip yield is not optimal, the voltage binning scheme is altered and the compute and determine steps are repeated. Otherwise the binning scheme is left unaltered.

Abstract: A system and method for checking a ground via of control chips of a printed circuit board (PCB) provides a graphical user interface (GUI) displaying a layout of the PCB. The control chip has a plurality of ground pins. The computer searches for signal path routing of each ground pin and ground vias along each signal path routing of each ground pin. If there are any ground vias having the same absolute coordinates, the computer determines that the ground vias are shared by more than one ground pin.

Abstract: A system for detecting the miswiring of an electrical appliance that includes a microprocessor having first and second input connections to sample signals on two different electrical power lines. The microprocessor further includes a third input connection for a neutral line. In an embodiment of the invention, there is at least one switch through which electrical power can flow into a load. The at least one switch is controlled by the microprocessor. In a particular embodiment, the microprocessor is configured to compare the signals sampled at the first and second input connections to determine whether the electrical appliance has been wired correctly.

Abstract: Methods and devices to measure voltage margins of electromechanical devices are disclosed. The voltage margins are determined based on responses to test voltages which cause the devices to change states. State changes of the devices are detected by monitoring integrated current or charge used to drive the devices with the test voltages.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: Circuits, methods, and apparatus for testing media devices. One example provides a test system for testing a number of media players. One or more computers can control the testing of the media players and collect results. Each media player tested may be connected to a computer via an adapter. The adapter may include a connection control circuit and an interface. The connection control circuit may connect and disconnect a power supply to the media player being tested. The voltage waveform produced when the power supply is connected and disconnected may be designed to mimic the voltage waveform produced when a user connects and disconnects a cable or docking station from the media player. The interface may receive commands to provide specific instructions to the media player. The interface may monitor the status and activities performed by the media player and report back to the computer.

Abstract: The present invention systems and methods facilitate increased die yields by flexibly changing the operational characteristics of functional components in an integrated circuit die. The present invention system and method enable integrated circuit chips with defective functional components to be salvaged. Defective functional components in the die are disabled in a manner that maintains the basic functionality of the chip. A chip is tested and a functional component configuration process is performed on the chip based upon results of the testing. If an indication of a defective functional component is received, the functional component is disabled. Workflow is diverted from disabled functional components to enabled functional components.

Abstract: The present invention systems and methods facilitate configuration of functional components included in a remotely located integrated circuit die. In one exemplary implementation, a die functional component reconfiguration request process is engaged in wherein a system requests a reconfiguration code from a remote centralized resource. A reconfiguration code production process is executed in which a request for a reconfiguration code and a permission indicator are received, validity of permission indicator is analyzed, and a reconfiguration code is provided if the permission indicator is valid. A die functional component configuration process is performed on the die when an appropriate reconfiguration code is received by the die. The functional component configuration process includes directing alteration of a functional component configuration. Workflow is diverted from disabled functional components to enabled functional components.

Abstract: Consistent with embodiments of the present disclosure, a method involves a redriver circuit with compliance test mode features. A redriver circuit is configured to process received compliance patterns for a compliance test mode. A compliance test mode is detected by a redriver circuit having a first input port and a second input port. The redriver detects the presence of a remote receiver termination on both input ports, monitors both input ports to detect received data and enters compliance test mode in response to no received data being detected on the input ports for a set period of time. Compliance patterns are tracked by monitoring for valid signal levels on the second input port. De-emphasis is controlled on at least one input port in response thereto.

Abstract: A tool to aid a test engineer in creating a concurrent test plan. The tool may quickly map test system resources to specific pins to satisfy the requirements of a concurrent test. The tool may project test time when such a mapping is possible. When a mapping is not possible, the tool may inform its user, including making suggestions of additional resources that could allow the test system to perform the test or suggestions for other variations in input parameters that would allow a mapping. The tool employs an assignment process in which groups of associated pins are identified, along with associated resource requirements for each group. Groups of test system resources that collectively fulfill a higher level requirement are identified and the assignment is made by mapping resource sets to resource groups, using ordering and matching heuristics to reduce processing time.

Abstract: A method, system and apparatus for testing of multi-component integrated circuits are provided. A multi-component integrated circuit has multiple identical components to be tested. A testing apparatus is provided that is configured to simultaneously apply a test signal to each of a plurality of components of a multi-component integrated circuit to execute a first test on each of the components. A processor receives a group test result for the first test that indicates that one or more of the components failed the first test. The group test result comprises failure data that does not directly indicate whether each component passed or failed the first test. The failure data can be processed to determine which components failed the first test.

Abstract: In accordance with a preferred embodiment of the present invention, a method of testing a device includes a circuit includes a device-under-test and an emulated apparatus. The emulated apparatus includes digital circuitry that models a real device. The circuit is powered and a response of the circuit is calculated. The calculated response is determined at least based on the emulated apparatus. An analog response signal is generated based on the digitally calculated response. The analog response signal is applied to the device under test.

Abstract: A method and apparatus for scanning an integrated circuit comprising a plurality of time-synchronized laser microscopes, each of which is configured to scan the same field of view of an integrated circuit under test that generates a plurality of images of the integrated circuit under test, a data processor, coupled to the laser scanning microscope, for processing the plurality of images, comprising, a netlist extractor (NE) that produces one or more netlists defining structure of the integrated circuit under test.

Abstract: In a system and method for testing a serial port of a computing device, the serial port electronically connects to a test fixture. Test data is sent to a receive data (RXD) pin by a transmit data (TXD) pin. A test result is received from the serial port by the RXD pin. The TXD pin and the RXD pin work normally if the test data is identical to the test result. When voltages of a request to send (RTS) pin and a data terminal ready (DTR) pin are set at high level, the RTS pin, a data carrier detect (DCD) pin, the DTR pin, a ring indicator (RI) pin, a data send ready (DSR) pin and a clear to send (CTS) pin work normally, upon the condition that status values of the serial port indicate the voltages of the above six pins are at high level.

Abstract: A tester module for automatic test equipment (ATE) includes test instruments for testing an integrated circuit device under test (DUT). A plurality of sensors include sensors coupled to or proximate to the test instruments for detecting a plurality of different maintenance triggers associated with the test instruments. A memory stores code including operating system code for controlling the test instruments and for implementing a system maintenance compliance tool. A processor is coupled to the test instruments the sensors and the memory. The processor runs the operating system code including the system maintenance compliance tool. The system maintenance compliance tool upon receiving notification of at least a first maintenance trigger automatically blocks the ATE being used for the testing. The system maintenance compliance tool can include a listing of needed maintenance actions associated with the maintenance triggers that when completed automatically releases the ATE to allow resumption of testing.

Abstract: A method for determining disposition of via hole on printed circuit board (PCB) includes the steps of: providing a PCB on which is disposed with a geometric layout and a via hole; providing a line on the PCB for intersecting the geometric layout to form a plurality of points of intersection; defining line segments by segmenting the line at each of the points of intersection to form a plurality of line segments; deleting some of the line segments having one end not being point of intersection for the geometric layout to form a plurality of segmented regions; searching a closed region by repeatedly searching region from any one of the points in the plurality of segmented regions; determining whether a closed region is a smallest closed region; determining whether a via hole is located within the smallest closed region.

Abstract: A semiconductor device having a test function includes a program counter for storing a breaking address in a storage unit in response to control signals, increasing a count address in response to the control signals, and storing the increased count address in the storage unit; a controller for stopping the increase of the count address when the count address is identical to the breaking address and outputting a pump holding signal; an oscillator for generating a clock signal in response to an enable signal and maintaining a current cycle of the clock signal in response to the pump holding signal; and a pump unit for generating an output voltage in response to the clock signal.

Abstract: A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.

Abstract: A method for operating a powertrain system including a torque machine mechanically coupled to an internal combustion engine includes, upon detecting a pending fault associated with a power switch configured to control power flow to the torque machine, disabling torque output from the torque machine and executing retry events. The retry events are iteratively executed with a debounce time period preceding each retry event. Presence of a fault associated with the power switch is detected when a quantity of the retry events during a time window exceeds a threshold.

Abstract: An approach is provided in which a system under test is subjected to thermal cycling that include transferring the system under test between two different environments that generate two different ambient temperatures. In turn, a test system tests the electronic assembly in response to the electronic assembly being subjected to the thermal cycles.

Abstract: A system for use in automated test equipment. In one embodiment, the system includes a configurable integrated circuit (IC) programmable to provide test patterns for use in automated test equipment. The configurable IC includes a configurable interface core that is programmable to provide functionality of one or more protocol based interfaces for a device under test (DUT) and is programmable to interface with the DUT. The system also includes a connection configurable to couple the configurable IC to the DUT.

Abstract: A field device is composed of a sensor, which works according to a defined measuring principle, and a control/evaluation unit, for a particular safety-critical application, conditions and evaluates, along at least two equivalent measuring paths, measurement data delivered by the sensor. The control/evaluation unit is implemented on an FPGA, provided with at least a first section and a second section. In each section, a digital measuring path, is dynamically reconfigurable. The sections are isolated from one another by permanently configured spacer regions, wherein the spacer regions are embodied in such a way, that a temperature and/or a voltage change in one of the sections has no influence on the other section or other sections, and, in the case of malfunction, no connection occurs between the sections.

Abstract: A method of characterizing a die can include correlating, using a processor, a static voltage profile of a die under test in wafer form with a plurality of test static voltage profiles. The plurality of test static voltage profiles can be associated with dynamic performance profiles. The method further can include predicting dynamic performance of the die under test according to the dynamic performance profile associated with a test static voltage profile that is correlated with the static voltage profile.

Abstract: A mechanism is provided for mitigating aging of a set of components in the data processing system. A modeled age of a component in the set of components is identified. A desired aging requirement for the component is identified and a determination is made as to whether the modeled age of the component is greater than the desired age of the component. Responsive to the modeled age of the component being greater than the desired age of the component, a policy is implemented to mitigate the aging of the component.

Abstract: Embodiments of the invention include systems and methods for automatically predicting production yield for a circuit assembly according to attributes of its components and defect data mapped thereto. Embodiments receive a proposed design specification for a circuit assembly, including bill of materials (BOM) and schematic data, at a yield prediction environment. The yield prediction environment maps a set of attributes to each component in the BOM and maps a set of possible defects to each component according to its attributes. Defects may be further mapped to a manufacturing process assigned to populate each component in the circuit assembly. The defects are associated with predicted frequencies of occurrence, which can be used to roll up a yield prediction for the circuit assembly. Embodiments further allow “what-if” analyses to be performed so that different yield prediction results can be compared according to different form factor options and/or different manufacturing process options.

Abstract: A method for operating a data processing system to generate a test for a device under test (DUT) is disclosed. The method utilizes a model of the DUT that includes a plurality of blocks connected by wires and a set of control inputs. Each block includes a plurality of ports, each port being either active or inactive. Each block is also characterized by a set of constraints that limit which ports are active. The active ports of at least one of the blocks are constrained by one of the control inputs. A test vector having one component for each port of each block and one component for each control input is determined such that each set of constraints for each block is satisfied. The test vector defines a test for the DUT.

Abstract: A magnetic field sensor includes a diagnostic circuit that allows a self-test of most of, or all of, the circuitry of the magnetic field sensor, including a self-test of a magnetic field sensing element used within the magnetic field sensor. The magnetic field sensor can generate a diagnostic magnetic field to which the magnetic field sensor is responsive.

Abstract: A judgment unit judges the pass/fail of DUTs. A power supply circuit has changeable characteristics, and supplies a power supply signal to the DUTs. A condition setting unit performs a pilot test before a main test for the DUTs, and acquires a test condition to be used in the main test. The condition setting unit executes: (a) measuring a first device characteristic value for each of multiple pilot samples sampled from among the DUTs while emulating a power supply characteristic close to what is used in a user environment in which the DUT is actually used; (b) measuring a predetermined second device characteristic value for each of the multiple pilot sample devices while emulating a power supply characteristic close to what is used in a tester environment in which the main test is performed; and (c) determining the test condition based on the first and second device characteristic values.

Abstract: A method and apparatus for conducting a transition test of a source synchronous interface is disclosed. A system includes a source synchronous transmitter and source synchronous receiver. The source synchronous transmitter includes a first scannable flop having an output coupled to a data input of a second scannable flop in the source synchronous receiver. During a transition test, the source synchronous transmitter is configured to transmit data from the first scannable flop to the second scannable flop, along with a clock signal at an operational clock speed. The first scannable flop is coupled to feedback circuitry configured to cause transitions of the transmitted data. The second scannable flop may capture the transmitted data. The captured data may be subsequently used to determine if the desired transitions were detected by the second scannable flop.

Abstract: A method of connecting to an integrated circuit. A target integrated circuit (102) is provided with an embedded agent (104) for exporting signals. While the target integrated circuit (102) is operating, data signals from one or more collection points (252) in the integrated circuit (102) are collected by the embedded agent (104), at least at a clock rate of operation of the integrated circuit at the one or more collection points (252), in parallel to the target circuit (102) operation. The collected data signals are inserted into packets, by the embedded agent (104) and the packets are transmitted to a unit external to the integrated circuit, in real time.

Abstract: A system and method of testing High Brightness LED (HBLED) is provided, and more particularly, a system and method of Controlled Energy Testing of HBLED with improved accuracy and repeatability is provided. In one embodiment, the system includes a programmable constant power source for providing a constant power to a Device Under Test (DUT), in this case, an HBLED, wherein the programmable constant power source adjusts an output voltage or an output current to ensure that a given amount of power is supplied to the HBLED for a predetermined amount of time and to provide precise control of a junction temperature of the HBLED for the duration of the test sequences; a Parametric Measurement Unit (PMU) including a processor for executing a plurality of HBLED test sequences, and a spectrometer for measuring a set of HBLED parameters including power and color (wavelength) of an optical output of the HBLED; and a controller for coordinating timing of acquiring the set of measured HBLED parameters.

Abstract: A magnetic field sensor includes a reference-field-sensing circuit channel that allows a calibration or a self-test of the circuitry of the magnetic field sensor. The magnetic field sensor can generate a reference magnetic field to which the magnetic field sensor is responsive.

Abstract: In one embodiment, the invention is a method and apparatus for selecting voltage and frequency levels for use in at-speed testing. One embodiment of a method for selecting a set of test conditions with which to test an integrated circuit chip includes formulating a statistical optimization problem and obtaining a solution to the statistical optimization problem, where the solution is the set of test conditions.

Abstract: Techniques described herein generally relate to optimizing energy consumption in a computer system. In some examples an energy usage benchmark can be determined for a system component of the computer system by measuring performance levels and energy usages of the system component under a range of energy settings and utilization rates of the system component. A utilization rate of the system component can be determined based on prediction factors including the execution of a first set of instructions on the computer system. The system component can be configured to execute a second set of instructions after the first set of instructions by selecting an energy setting from the range of energy settings for operating the system component. The energy setting can be selected based on the energy usage benchmark and the determined utilization rate.