Abstract: A system for detecting the miswiring of an electrical appliance that includes a microprocessor having first and second input connections to sample signals on two different electrical power lines. The microprocessor further includes a third input connection for a neutral line. In an embodiment of the invention, there is at least one switch through which electrical power can flow into a load. The at least one switch is controlled by the microprocessor. In a particular embodiment, the microprocessor is configured to compare the signals sampled at the first and second input connections to determine whether the electrical appliance has been wired correctly.

Abstract: Techniques for improving parametric chip yield of manufactured chips are provided. In one aspect, a method for optimizing parametric chip yield is provided. The method includes the following steps. Parametric chip yield is computed based on performance and power consumption of a plurality of manufactured chips subject to a given voltage binning scheme. It is then determined whether the parametric chip yield computed is optimal. If the parametric chip yield is not optimal, the voltage binning scheme is altered and the compute and determine steps are repeated. Otherwise the binning scheme is left unaltered.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: Methods and devices to measure voltage margins of electromechanical devices are disclosed. The voltage margins are determined based on responses to test voltages which cause the devices to change states. State changes of the devices are detected by monitoring integrated current or charge used to drive the devices with the test voltages.

Abstract: The present invention systems and methods facilitate increased die yields by flexibly changing the operational characteristics of functional components in an integrated circuit die. The present invention system and method enable integrated circuit chips with defective functional components to be salvaged. Defective functional components in the die are disabled in a manner that maintains the basic functionality of the chip. A chip is tested and a functional component configuration process is performed on the chip based upon results of the testing. If an indication of a defective functional component is received, the functional component is disabled. Workflow is diverted from disabled functional components to enabled functional components.

Abstract: Circuits, methods, and apparatus for testing media devices. One example provides a test system for testing a number of media players. One or more computers can control the testing of the media players and collect results. Each media player tested may be connected to a computer via an adapter. The adapter may include a connection control circuit and an interface. The connection control circuit may connect and disconnect a power supply to the media player being tested. The voltage waveform produced when the power supply is connected and disconnected may be designed to mimic the voltage waveform produced when a user connects and disconnects a cable or docking station from the media player. The interface may receive commands to provide specific instructions to the media player. The interface may monitor the status and activities performed by the media player and report back to the computer.

Abstract: Consistent with embodiments of the present disclosure, a method involves a redriver circuit with compliance test mode features. A redriver circuit is configured to process received compliance patterns for a compliance test mode. A compliance test mode is detected by a redriver circuit having a first input port and a second input port. The redriver detects the presence of a remote receiver termination on both input ports, monitors both input ports to detect received data and enters compliance test mode in response to no received data being detected on the input ports for a set period of time. Compliance patterns are tracked by monitoring for valid signal levels on the second input port. De-emphasis is controlled on at least one input port in response thereto.

Abstract: The present invention systems and methods facilitate configuration of functional components included in a remotely located integrated circuit die. In one exemplary implementation, a die functional component reconfiguration request process is engaged in wherein a system requests a reconfiguration code from a remote centralized resource. A reconfiguration code production process is executed in which a request for a reconfiguration code and a permission indicator are received, validity of permission indicator is analyzed, and a reconfiguration code is provided if the permission indicator is valid. A die functional component configuration process is performed on the die when an appropriate reconfiguration code is received by the die. The functional component configuration process includes directing alteration of a functional component configuration. Workflow is diverted from disabled functional components to enabled functional components.

Abstract: A tool to aid a test engineer in creating a concurrent test plan. The tool may quickly map test system resources to specific pins to satisfy the requirements of a concurrent test. The tool may project test time when such a mapping is possible. When a mapping is not possible, the tool may inform its user, including making suggestions of additional resources that could allow the test system to perform the test or suggestions for other variations in input parameters that would allow a mapping. The tool employs an assignment process in which groups of associated pins are identified, along with associated resource requirements for each group. Groups of test system resources that collectively fulfill a higher level requirement are identified and the assignment is made by mapping resource sets to resource groups, using ordering and matching heuristics to reduce processing time.

Abstract: In accordance with a preferred embodiment of the present invention, a method of testing a device includes a circuit includes a device-under-test and an emulated apparatus. The emulated apparatus includes digital circuitry that models a real device. The circuit is powered and a response of the circuit is calculated. The calculated response is determined at least based on the emulated apparatus. An analog response signal is generated based on the digitally calculated response. The analog response signal is applied to the device under test.

Abstract: A method and apparatus for scanning an integrated circuit comprising a plurality of time-synchronized laser microscopes, each of which is configured to scan the same field of view of an integrated circuit under test that generates a plurality of images of the integrated circuit under test, a data processor, coupled to the laser scanning microscope, for processing the plurality of images, comprising, a netlist extractor (NE) that produces one or more netlists defining structure of the integrated circuit under test.

Abstract: A method, system and apparatus for testing of multi-component integrated circuits are provided. A multi-component integrated circuit has multiple identical components to be tested. A testing apparatus is provided that is configured to simultaneously apply a test signal to each of a plurality of components of a multi-component integrated circuit to execute a first test on each of the components. A processor receives a group test result for the first test that indicates that one or more of the components failed the first test. The group test result comprises failure data that does not directly indicate whether each component passed or failed the first test. The failure data can be processed to determine which components failed the first test.

Abstract: A method for determining disposition of via hole on printed circuit board (PCB) includes the steps of: providing a PCB on which is disposed with a geometric layout and a via hole; providing a line on the PCB for intersecting the geometric layout to form a plurality of points of intersection; defining line segments by segmenting the line at each of the points of intersection to form a plurality of line segments; deleting some of the line segments having one end not being point of intersection for the geometric layout to form a plurality of segmented regions; searching a closed region by repeatedly searching region from any one of the points in the plurality of segmented regions; determining whether a closed region is a smallest closed region; determining whether a via hole is located within the smallest closed region.

Abstract: A semiconductor device having a test function includes a program counter for storing a breaking address in a storage unit in response to control signals, increasing a count address in response to the control signals, and storing the increased count address in the storage unit; a controller for stopping the increase of the count address when the count address is identical to the breaking address and outputting a pump holding signal; an oscillator for generating a clock signal in response to an enable signal and maintaining a current cycle of the clock signal in response to the pump holding signal; and a pump unit for generating an output voltage in response to the clock signal.

Abstract: In a system and method for testing a serial port of a computing device, the serial port electronically connects to a test fixture. Test data is sent to a receive data (RXD) pin by a transmit data (TXD) pin. A test result is received from the serial port by the RXD pin. The TXD pin and the RXD pin work normally if the test data is identical to the test result. When voltages of a request to send (RTS) pin and a data terminal ready (DTR) pin are set at high level, the RTS pin, a data carrier detect (DCD) pin, the DTR pin, a ring indicator (RI) pin, a data send ready (DSR) pin and a clear to send (CTS) pin work normally, upon the condition that status values of the serial port indicate the voltages of the above six pins are at high level.

Abstract: A tester module for automatic test equipment (ATE) includes test instruments for testing an integrated circuit device under test (DUT). A plurality of sensors include sensors coupled to or proximate to the test instruments for detecting a plurality of different maintenance triggers associated with the test instruments. A memory stores code including operating system code for controlling the test instruments and for implementing a system maintenance compliance tool. A processor is coupled to the test instruments the sensors and the memory. The processor runs the operating system code including the system maintenance compliance tool. The system maintenance compliance tool upon receiving notification of at least a first maintenance trigger automatically blocks the ATE being used for the testing. The system maintenance compliance tool can include a listing of needed maintenance actions associated with the maintenance triggers that when completed automatically releases the ATE to allow resumption of testing.

Abstract: A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.

Abstract: A method for operating a powertrain system including a torque machine mechanically coupled to an internal combustion engine includes, upon detecting a pending fault associated with a power switch configured to control power flow to the torque machine, disabling torque output from the torque machine and executing retry events. The retry events are iteratively executed with a debounce time period preceding each retry event. Presence of a fault associated with the power switch is detected when a quantity of the retry events during a time window exceeds a threshold.

Abstract: An approach is provided in which a system under test is subjected to thermal cycling that include transferring the system under test between two different environments that generate two different ambient temperatures. In turn, a test system tests the electronic assembly in response to the electronic assembly being subjected to the thermal cycles.

Abstract: A system for use in automated test equipment. In one embodiment, the system includes a configurable integrated circuit (IC) programmable to provide test patterns for use in automated test equipment. The configurable IC includes a configurable interface core that is programmable to provide functionality of one or more protocol based interfaces for a device under test (DUT) and is programmable to interface with the DUT. The system also includes a connection configurable to couple the configurable IC to the DUT.

Abstract: A field device is composed of a sensor, which works according to a defined measuring principle, and a control/evaluation unit, for a particular safety-critical application, conditions and evaluates, along at least two equivalent measuring paths, measurement data delivered by the sensor. The control/evaluation unit is implemented on an FPGA, provided with at least a first section and a second section. In each section, a digital measuring path, is dynamically reconfigurable. The sections are isolated from one another by permanently configured spacer regions, wherein the spacer regions are embodied in such a way, that a temperature and/or a voltage change in one of the sections has no influence on the other section or other sections, and, in the case of malfunction, no connection occurs between the sections.

Abstract: A method of characterizing a die can include correlating, using a processor, a static voltage profile of a die under test in wafer form with a plurality of test static voltage profiles. The plurality of test static voltage profiles can be associated with dynamic performance profiles. The method further can include predicting dynamic performance of the die under test according to the dynamic performance profile associated with a test static voltage profile that is correlated with the static voltage profile.

Abstract: A mechanism is provided for mitigating aging of a set of components in the data processing system. A modeled age of a component in the set of components is identified. A desired aging requirement for the component is identified and a determination is made as to whether the modeled age of the component is greater than the desired age of the component. Responsive to the modeled age of the component being greater than the desired age of the component, a policy is implemented to mitigate the aging of the component.

Abstract: A method for operating a data processing system to generate a test for a device under test (DUT) is disclosed. The method utilizes a model of the DUT that includes a plurality of blocks connected by wires and a set of control inputs. Each block includes a plurality of ports, each port being either active or inactive. Each block is also characterized by a set of constraints that limit which ports are active. The active ports of at least one of the blocks are constrained by one of the control inputs. A test vector having one component for each port of each block and one component for each control input is determined such that each set of constraints for each block is satisfied. The test vector defines a test for the DUT.

Abstract: Embodiments of the invention include systems and methods for automatically predicting production yield for a circuit assembly according to attributes of its components and defect data mapped thereto. Embodiments receive a proposed design specification for a circuit assembly, including bill of materials (BOM) and schematic data, at a yield prediction environment. The yield prediction environment maps a set of attributes to each component in the BOM and maps a set of possible defects to each component according to its attributes. Defects may be further mapped to a manufacturing process assigned to populate each component in the circuit assembly. The defects are associated with predicted frequencies of occurrence, which can be used to roll up a yield prediction for the circuit assembly. Embodiments further allow “what-if” analyses to be performed so that different yield prediction results can be compared according to different form factor options and/or different manufacturing process options.

Abstract: A magnetic field sensor includes a diagnostic circuit that allows a self-test of most of, or all of, the circuitry of the magnetic field sensor, including a self-test of a magnetic field sensing element used within the magnetic field sensor. The magnetic field sensor can generate a diagnostic magnetic field to which the magnetic field sensor is responsive.

Abstract: A judgment unit judges the pass/fail of DUTs. A power supply circuit has changeable characteristics, and supplies a power supply signal to the DUTs. A condition setting unit performs a pilot test before a main test for the DUTs, and acquires a test condition to be used in the main test. The condition setting unit executes: (a) measuring a first device characteristic value for each of multiple pilot samples sampled from among the DUTs while emulating a power supply characteristic close to what is used in a user environment in which the DUT is actually used; (b) measuring a predetermined second device characteristic value for each of the multiple pilot sample devices while emulating a power supply characteristic close to what is used in a tester environment in which the main test is performed; and (c) determining the test condition based on the first and second device characteristic values.

Abstract: A method of connecting to an integrated circuit. A target integrated circuit (102) is provided with an embedded agent (104) for exporting signals. While the target integrated circuit (102) is operating, data signals from one or more collection points (252) in the integrated circuit (102) are collected by the embedded agent (104), at least at a clock rate of operation of the integrated circuit at the one or more collection points (252), in parallel to the target circuit (102) operation. The collected data signals are inserted into packets, by the embedded agent (104) and the packets are transmitted to a unit external to the integrated circuit, in real time.

Abstract: A method and apparatus for conducting a transition test of a source synchronous interface is disclosed. A system includes a source synchronous transmitter and source synchronous receiver. The source synchronous transmitter includes a first scannable flop having an output coupled to a data input of a second scannable flop in the source synchronous receiver. During a transition test, the source synchronous transmitter is configured to transmit data from the first scannable flop to the second scannable flop, along with a clock signal at an operational clock speed. The first scannable flop is coupled to feedback circuitry configured to cause transitions of the transmitted data. The second scannable flop may capture the transmitted data. The captured data may be subsequently used to determine if the desired transitions were detected by the second scannable flop.

Abstract: A system and method of testing High Brightness LED (HBLED) is provided, and more particularly, a system and method of Controlled Energy Testing of HBLED with improved accuracy and repeatability is provided. In one embodiment, the system includes a programmable constant power source for providing a constant power to a Device Under Test (DUT), in this case, an HBLED, wherein the programmable constant power source adjusts an output voltage or an output current to ensure that a given amount of power is supplied to the HBLED for a predetermined amount of time and to provide precise control of a junction temperature of the HBLED for the duration of the test sequences; a Parametric Measurement Unit (PMU) including a processor for executing a plurality of HBLED test sequences, and a spectrometer for measuring a set of HBLED parameters including power and color (wavelength) of an optical output of the HBLED; and a controller for coordinating timing of acquiring the set of measured HBLED parameters.

Abstract: A magnetic field sensor includes a reference-field-sensing circuit channel that allows a calibration or a self-test of the circuitry of the magnetic field sensor. The magnetic field sensor can generate a reference magnetic field to which the magnetic field sensor is responsive.

Abstract: In one embodiment, the invention is a method and apparatus for selecting voltage and frequency levels for use in at-speed testing. One embodiment of a method for selecting a set of test conditions with which to test an integrated circuit chip includes formulating a statistical optimization problem and obtaining a solution to the statistical optimization problem, where the solution is the set of test conditions.

Abstract: Techniques described herein generally relate to optimizing energy consumption in a computer system. In some examples an energy usage benchmark can be determined for a system component of the computer system by measuring performance levels and energy usages of the system component under a range of energy settings and utilization rates of the system component. A utilization rate of the system component can be determined based on prediction factors including the execution of a first set of instructions on the computer system. The system component can be configured to execute a second set of instructions after the first set of instructions by selecting an energy setting from the range of energy settings for operating the system component. The energy setting can be selected based on the energy usage benchmark and the determined utilization rate.

Abstract: A burn-in method for an embedded Multi Media Card (eMMC), and a test board using the same, and an eMMC tested by the same. The disclosed burn-in method comprises the steps as below: writing a test pattern to a flash memory of the eMMC; electrically connecting a command line of the eMMC to ground to operate the eMMC in a boot state; performing a burn-in procedure on the flash memory when the eMMC is in the boot state and the test pattern is recognized as being contained in the flash memory; and collecting a test report during the burn-in procedure, wherein the test report is stored in the flash memory.

Abstract: A method of controlling a quantity of non-process of record (POR) process limiting yield (PLY) inspections in wafer processing includes setting aside planned capacity for non-POR work, upon receipt of a request for non-POR work, estimating a time required for completion of the request and comparing the estimated time against a remainder of the set aside planned capacity, approving the request in an event the comparison indicates that the estimated time is available in the set aside planned capacity and rejecting the request in an event the comparison indicates that the estimated time is not available in the set aside planned capacity.

Abstract: A method for diagnosing a faulty board includes generating a table of debug knowledge in accordance with predefined debug rules, and configuring a diagnostic engine in accordance with the table of debug knowledge. The method also includes subjecting the faulty board to the diagnostic engine to generate a suggested repair, receiving feedback regarding an effectiveness of the suggested repair, and reconfiguring the diagnostic engine in accordance with the feedback regarding the effectiveness of the suggested repair.

Abstract: A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is typically calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal. To compensate for voltage and temperature variations over time during normal operation, a runtime dynamic calibration mechanism and procedure is also provided.

Abstract: In accordance with an embodiment of the invention, precision control of error injection may be accomplished by way of synchronous error signals accompanying data transfers along various pipeline stages of a data path. The synchronous error signals may be used to trigger error events in a given protocol logic block (i.e. in a given sub-component of the data path). The protocol logic block is configurable to determine whether any action is to be taken upon the assertion of the error signal. Multiple error events may be triggered as the data signal (and its accompanying synchronous error signal) passes through pipelined functions of the data path so as to create complex error conditions. In addition, deterministic handling of created errors may be accomplished using a loopback path with bypassable blocks on both forward and reverse transformations. Other embodiments, aspects and features are also disclosed.

Abstract: An automation process verifies that a test bed includes a set of devices specified by at least one script which are to be executed by the automation process on the test bed. The test bed is locked and the set of devices is allocated to the automation process. Performance data collection and logging for the set of devices is started and the at least one script is executed on the set of devices. After executing the at least one script, the set of devices is de-allocated and the test bed is unlocked. A notification is generated indicating that the at least one script has been executed.

Abstract: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

Abstract: A chip diagnostics management system includes secure design information that define production features of integrated circuit devices and are accessible according to selected levels of access privilege. A database of device defect information includes information of defects of devices produced according to the production features of the design information and associated wafers, production lots, and dies in or with which the devices were produced. A diagnostic manager correlates device defect information from plural wafers with the design information to identify a device location with a probability of being associated with the device defect information. A diagnostic manager viewer indicates the device location together with an amount of design information correlated the level of access privilege assigned to a selected user.

Abstract: A circuit constant analysis method for an equivalent circuit of an inductance element includes determining values of various elements constituting the equivalent circuit from measured values of select electrical characteristics of the actual inductance element. The equivalent circuit includes: a parallel circuit connecting in parallel an inductance Ls, a capacitance Cp, and a resistance Rp; a capacitance Cr connected in series to said resistance Rp; an inductance Lr connected in parallel to said resistance Rp; a resistance Rs connected in series to said parallel circuit; a plurality of closed circuits including a resistance Rmi and an inductance Lmi magnetically coupled with a coupling coefficient ki by a mutual inductance Mi to said inductance Ls; and a resistance Rc connected in series to said capacitance Cp.

Abstract: Embodiments of the invention include systems and methods for automatically predicting production yield for a circuit assembly according to attributes of its components and defect data mapped thereto. Embodiments receive a proposed design specification for a circuit assembly, including bill of materials (BOM) and schematic data, at a yield prediction environment. The yield prediction environment maps a set of attributes to each component in the BOM and maps a set of possible defects to each component according to its attributes. Defects may be further mapped to a manufacturing process assigned to populate each component in the circuit assembly. The defects are associated with predicted frequencies of occurrence, which can be used to roll up a yield prediction for the circuit assembly. Embodiments further allow “what-if” analysis to be performed so that different yield prediction results can be compared according to different form factor options and/or different manufacturing process options.

Abstract: A voltage driver is provided having an input to receive test parameters from a microcontroller. The voltage driver having a first amplifier to provide an input to a first switch, based on the test parameters. The first switch having an output to a first connector such as a probe adapted to be connected to a device under test or DUT. A second switch having an input from a second connector to the device under test, the output of the second switch connected to a ground. A third switch has an input connected to the second switch input, the third switch having an output connected to the first connector to the device under test, wherein the first switch is open, and the second and third switch are closed to set the first connector and the second connector to ground. A buffer is provided such that the microcontroller is sets the test parameters in the first voltage driver, the first voltage driver is adapted to provide test data to the buffer.

Abstract: A switching-type categorizing and testing apparatus of a Radio Frequency integrated Circuit (RFIC) is used to test and categorize at least one RFIC module. The apparatus comprises at least one testing module and a plurality of categorizing modules. The testing module is used to test the RFIC module, and the categorizing modules comprise a first categorizing module and a second categorizing module. The testing module tests the RFIC module within one of the two categorizing modules at the same when the other categorizing module categorizes the RFIC module already tested. The present invention may further increase the testing and categorizing quantity so as to achieve the fast and cost-saving advantages.

Abstract: A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use.

Abstract: A testing assembly for measuring voltage across a circuit during an electrostatic discharge event is provided. The assembly includes a high-frequency read-out device configured for coupling with an input of the circuit and coupling with an output of the circuit, each of the couplings including components configured for substantially blocking high-frequency electric signals while passing low frequency electric signals. A method of operation and a computer program product are also disclosed.

Abstract: A method for inspecting short-circuit of circuit layout and a device using the same are provided, the method including: obtaining a circuit layout, wherein the circuit layout including a plurality of components; searching at least one of physical short-circuit components on the circuit layout among the components; adjusting the at least one of the physical short-circuit components so as to set the at least one of the physical short-circuit components to an open circuit state; inspecting whether the circuit layout has a short-circuit; and recovering the at least one of the physical short-circuit components to the at least one of the physical short-circuit components before adjustment. Thus, the short-circuit errors needed to be corrected in the circuit layout are detected exactly.

Abstract: A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry.

Abstract: A semiconductor device failure analysis method and apparatus and a computer program for the method and apparatus are provided. The method includes: an observation image acquisition process of acquiring a voltage contrast image by charging an exposed conductive layer of a semiconductor device and irradiating the exposed conductive layer with charged particles; a wiring search process of searching for end points connected to the conductive layer based on design data; and a determination process of comparing voltage contrasts of three levels or more set in advance, one of which is set for a wiring depending on a state of an end point of the wiring, with the voltage contrast image acquired in the observation image acquisition process to determine consistency/inconsistency. Since three or more levels are set, for example, a short-circuit formed by a conductive layer connected to a transistor diffusion layer and another wiring can be identified.