Abstract: Automatic part testing includes: booting a part under testing into a first operating environment; executing, via the first operating environment, one or more test patterns on the part; performing a comparison between one or more observed characteristics associated with the one or more test patterns and one or more expected characteristics; and modifying one or more operational parameters of a central processing unit of the part based on the comparison.

Abstract: In one embodiment, a processor includes: at least one core; a stress detector coupled to the at least one core to receive at least one of a voltage and a temperature at which the processor is to operate, calculate an effective stress based at least in part thereon, and maintain an accumulated effective stress; a clock circuit to calculate a lifetime duration of the processor in a platform; a meter to receive the accumulated effective stress, the lifetime duration and a stress model value and generate a control signal based on a comparison of the accumulated effective stress and the stress model value; and a power controller to control at least one parameter of a turbo mode of the processor based at least in part on the control signal. Other embodiments are described and claimed.

Abstract: Techniques relating to fused objects are disclosed. Embodiments include verifying the validity of a transition from a current tail template to a new tail template for a fused object. The validity of the transition is determined by analyzing the type transitions per memory slot. If the type transition, for each memory slot, constitutes a type-compatible transition, then the transition from the current tail template to the new tail template is valid. If the type transition, for any memory slot, is not type-compatible, then the transition from the current tail template to the new tail template is not valid. Embodiments include generating a fused object with a repeating tail. A tail template associated with a fused object is repeated multiple times in the tail of the fused object.

Abstract: Systems, methods, and non-transitory computer-readable media can receive, via a user interface provided to a user, test device information identifying one or more user computing devices as test devices. An advertisement request is received from a first user computing device. A determination is made that the first user computing device is identified as a test device. A test advertisement is transmitted to the first user computing device based on the determination that the first user computing device is identified as a test device.

Abstract: A semiconductor device includes a row address generation circuit, a first region, and a second region. The row address generation circuit is configured to generate a first row address from an active signal and a first bank address and configured to generate a second row address from the active signal and a second bank address. The first region is activated by the first row address and an internal address. The second region is activated by the second row address and the internal address. One of the first and second bank addresses is selectively generated according to a command/address signal.

Abstract: The invention concerns a test program executor for an Automated Test Equipment, wherein the test program executor is configured to execute a test flow having a plurality of test suites, wherein the test program executor is configured to asynchronously execute the plurality of test suites, wherein a test suite contains a call of a function of a subsystem, wherein the function of the subsystem is related with a subsystem operation that is to be executed by the subsystem, and to signal a call of a function of a subsystem by transmitting an asynchronous request to the subsystem, the asynchronous request having a call-specific call tree hierarchy address and the call-specific operation to be executed by the subsystem, and wherein the test program executor is further configured to determine an execution order of the subsystem operations, such that the execution order of the subsystem operations depends on their call-specific call tree hierarchy addresses.

Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) generator. Unstable bits of the plurality of key bits are identified, and a security key is generated based on the plurality of key bits, wherein the security key excludes the identified unstable bits.

Abstract: A processor executable method, system, and computer-readable media expedite the process of entering equations for use in developing simulations of chemical processes. The process of entering equations is expedited by dynamically inferring the dimensions of variables. The process infers the dimensions of all variables in user-added equations, and infers the dimensions of each variable in a user-added equation sequentially. The process automatically creates variables with unassigned dimensions in response to indications, such as inputs from a user, to declare new equations. The process assigns dimensions to variables based on relations between variables, such as logical relations between the dimensions of variables.

Abstract: A test system is provided for performing design for debug (DFD) operations. The test system includes a host processor coupled to an auxiliary device. The auxiliary device includes a protocol interface block for communicating with the host processor during normal functional mode. The auxiliary device further includes a circuit under test (CUT) and a hardened DFD hub that is controlled by the host processor via the protocol interface block. The DFD hub includes a DFD triggering component, a DFD tracing component, and a DFD access component. The host processor directs the DFD hub to perform DFD operations by sending control signals through the protocol interface block during a debugging mode. Test information gathered using the DFD hub is fed back to the host processor to help facilitate silicon bring-up, pre-production software stack optimization, and post-production performance metric monitoring.

Abstract: Provided is an information processing apparatus including: an input unit into which shape data of a surface to be measured including a plurality of recesses is input; and a setting unit that detects each of the plurality of recesses on the basis of the input shape data and sets, for the detected recess, a region to be removed including the recess.

Abstract: According to one general aspect, an apparatus may include a memory configured to store both data and metadata, such that for portions of data associated with the metadata, the data and metadata are interleaved such that a unit of metadata succeeds each power of two contiguous units of data. The apparatus may also include a memory manager circuit. The memory management circuit may be configured to receive a data access to the memory, wherein the data access includes a public memory address. The memory management circuit may be configured to determine if the public memory address is associated with metadata. The memory management circuit may be configured to, if so, convert the public memory address to a private memory address. The memory management circuit may be configured to complete the data access at the private memory address.

Abstract: A bandwidth estimation method is disclosed for measuring memory bandwidth consumption or the bandwidth consumption of any I/O bus in real time on a computer system without the use of hardware counters. The bandwidth estimation method, designed to run in isolation on a core in a multi-core computer system, generates temporally sequential and spatially random accesses to a bus such as the memory bus and reports the average latency per request. Using a pre-calculated latency-bandwidth relationship, the bandwidth on the bus is calculated and reported at runtime for every latency sample. The bandwidth estimation method allows profiling processors and computer systems in real time to determine the amount of memory or I/O traffic they are using while running a workload.

Abstract: An apparatus includes an array of memory cells comprising a first sub-block and a second sub-block electrically coupled by a channel. The apparatus also includes a measurement circuit configured to take a first measurement of a first sub-block of memory cells at a first offset threshold and a second measurement of the first sub-block of memory cells at a second offset threshold. The apparatus further includes a detection circuit configured to detect a disturb condition of the first sub-block based on at least one of the first measurement and the second measurement, and to initiate data maintenance in response to the disturb condition of the first sub-block.

Abstract: Methods and systems for performing analog-to-digital conversion is provided. In one example, an analog-to-digital converter (ADC) circuit comprises a leakage compensation circuit and a quantizer. The leakage compensation circuit is configured to: receive an input signal, the input signal being susceptible to a drift due to a charge leakage; receive a reference signal; and generate a leakage-compensated signal pair to compensate for the charge leakage, wherein the leakage-compensated signal pair comprises one of: (a) a leakage-compensated version of the input signal and the reference signal, (b) the input signal and a leakage-compensated version of the reference signal, or (c) a leakage-compensated version of the input signal and a leakage-compensated version of the reference signal. The quantizer is configured to perform a leakage-compensated quantization of the input signal based on the leakage-compensated signal pair to generate a digital output representing the input signal.

Abstract: Various aspects of the disclosed technology relate to techniques of logic diagnosis based on cell-aware diagnostic pattern generation. A first diagnosis process is performed on a failed integrated circuit based on a first fail log to generate a first set of defect suspects. The first fail log is generated by applying the first set of test patterns to the failed integrated circuit in a first scan-based test. A second set of test patterns are generated using fault models for internal defects in one or more cells included in the first set of defect suspects. The second set of test patterns are applied to the failure integrated circuit to generate a second fail log. A second diagnosis process is performed on the failure integrated circuit based on the second fail log.

Abstract: Disclosed is a test and measurement instrument including a plurality of ports. The ports are configured to source a test signal into a device under test (DUT), and receive a signal response from the DUT. The test and measurement instrument also includes a measurement unit configured to measure the signal response. The test and measurement instrument further includes a processor configured to compare the signal response to a data structure. The processor also determines a classification of, and/or connections to, at least one DUT component coupled to at least one of the ports based on results of the comparison.

Abstract: A method for creating binary classification models and using the binary classification models to select candidate training utterances from a plurality of live utterances is provided. The method may include receiving a plurality of intents and associated training utterances. The method may include creating, from the training utterances, a binary classification model for each intent. The binary classification model may include a vector representation of a line of demarcation between utterances associated with the intent and utterances disassociated from the intent. The method may also include receiving live utterances. An intent may be determined for each live utterance. The method may include creating a vector representation of the live utterance. The method may include selecting candidate training utterances based on a comparison between the vector representation of the live utterance and the vector representation included in the binary classification model of the intent determined for the live utterance.

Abstract: Techniques are described for adjusting policy characteristics based on a determined similarity between routes. A similarity metric may be determined indicating the similarity between a first route followed by a vehicle and/or driver and a second (e.g., previous) route followed by the vehicle and/or driver. A similarity metric may indicate the similarity in movements, and changes in movement, exhibited by the vehicle on the routes. The similarity metric may be determined through analysis of real time data collected by in-vehicle sensor(s), mobile user device(s), external sensors or other data sources. Based on the similarity metric, a premium, a deductible, a price, or other characteristic(s) of a policy may be determined. In some examples, policy characteristics may be adjusted (e.g., in real time) based on the analysis according to changing risk conditions if a driver is following routes that are dissimilar from typical routes.

Abstract: In a method of circuit yield analysis, the method includes: detecting a plurality of failed samples respectively located at a plurality of failure regions in a multi-dimensional parametric space; clustering the failed samples to identify the failure regions; filtering features of the failed samples to determine a parameter component that is a non-principal component in affecting circuit yield; applying a dimensional reduction method on a dimension corresponding to the parameter component; and constructing a final importance sampling (IS) distribution function using a mixed Gaussian (mGaussian) function corresponding to all of the failure regions containing a rare failure event.

Abstract: A yield prediction apparatus is provided. The yield prediction apparatus may include at least one processor coupled to at least one non-transitory computer-readable medium. The at least one processor may be configured to receive a first variable associated with operating characteristics of a semiconductor device, perform a simulation for the operating characteristics of the semiconductor device, perform a neural network regression analysis using a result of the simulation to determine a first function for the first variable, and predict a yield of the semiconductor integrated circuit based on an advanced Monte Carlo simulation. An input of the advanced Monte Carlo simulation may include the determined first function.

Abstract: Method and apparatus for managing connections within a netlist include using a clone module to the connections between different components within the netlist. A buffer may be inserted between components of a netlist to split a connection into multiple segments and then moved into an associated first instance. The inclusion of the buffer allows for one or more of pin cloning and subway utilization to occur when mapping between a functional hierarchy to a physical hierarchy is performed.

Abstract: The present disclosure generally relates to the automated testing of a system that includes software or hardware components. In some embodiments, a testing framework generates a set of test cases for a system under test using a grammar. Each test case may perform an action, such as provide an input to the system under test, and result in an output from the system under test. The inputs and outputs are then compared to the expected results to determine whether the system under test is performing correctly. Specifically, the system under test may be analyzed to determine whether it is capable of properly processing control instructions and input signals and/or generating expected output control signals and additional control/feedback information. The data can then be interpreted in the grammar system and/or used as input to a fault isolation engine to determine anomalies in the system under test.

Abstract: A system includes a magnetic sense element for detecting an external magnetic field along a sensing axis and a magnetic field source proximate the magnetic sense element for providing an auxiliary magnetic field along the sensing axis. The magnetic sense element produces a first output signal having a magnetic field signal component, responsive to the external magnetic field, that is modulated by an auxiliary magnetic field signal component responsive to the auxiliary magnetic field. A processing circuit identifies from the first output signal an influence of a magnetic interference field on the auxiliary magnetic field signal component, the magnetic interference field being directed along a non-sensing axis of the magnetic sense element, and applies a correction factor to the magnetic field signal component to produce a second output signal in which the influence of the magnetic interference field is substantially removed.

Abstract: Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

Abstract: An inspection device comprises a stage for placing a device under test thereon, a dynamic characteristics test probe, a static characteristics test probe, and a control device configured to perform positional control by moving at least one of the stage, the dynamic characteristics test probe, and the static characteristics test probe. The control device performs the positional control such that the dynamic characteristics test probe is set to a dynamic characteristics test state in which the dynamic characteristics test probe is brought into contact with the electrode when the dynamic characteristics test is performed, and performs the positional control such that the static characteristics test probe is set to a static characteristics test state in which the static characteristics test probe is brought into contact with the electrode while the dynamic characteristics test probe is separated from the electrode when the static characteristics test is performed.

Abstract: Disclosed herein is a system for non-contact measurement of an optoelectronic property. The system includes a sensing element configured to amplify an electromagnetic wave having a specific frequency, a thin film disposed on the sensing element such that an optoelectronic property of the thin film is measured, and an optoelectronic property measuring server configured to extract a physical property of the thin film based on the optoelectronic property of the thin film obtained when the electromagnetic wave amplified by the sensing element passes through the thin film.

Abstract: A method and apparatus for estimating a state of health (SOH) of a battery are provided. The method includes measuring a voltage and a partial discharge time of the battery, acquiring a normalized partial discharge time using a battery model of a reference battery normalized with respect to a time, calculating a full discharge time of the battery based on the partial discharge time and the normalized partial discharge time, and estimating the SOH based on a ratio between a stored full discharge time of the reference battery and the full discharge time of the battery.

Abstract: A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state. The peaks in the power supply current are compared to the reference peaks for the power supply current for a reference circuit having a same functionality as the integrated circuit to determine the integrated circuit's fitness.

Abstract: A digital serial communication system includes a first serial communication circuit configured to exchange information utilizing a first communication protocol, a second serial communication circuit configured to exchange information utilizing a second communication protocol, and a common bus interface configured to couple the first serial communication circuit to a first serial communication bus implementing the first communication protocol, and configured to couple the second serial communication circuit to a second serial communication bus implementing the second communication protocol.

Abstract: A digital control circuitry for a MEMS gyroscope is provided. The digital control circuitry comprises a digital primary loop circuitry configured to process a digitized primary signal, a digital secondary loop circuitry configured to process a digitized secondary signal and a digital phase shifting filter circuitry configured to generate two phase shifted demodulation signals from the digitized primary signal. The digital secondary loop is configured to demodulate the digitized secondary signal using the two phase shifted demodulation signals.

Abstract: A branch predictor, has a plurality of memory banks having entries that hold prediction information used to predict a direction of branch instructions fetched and executed by a processor that comprises the branch predictor. A count of events that occur in the processor is provided to hardware logic that performs an arithmetic and/or logical operation, e.g., XOR, on predetermined bits of the count to generate a random value. In response to the processor determining a correct direction of a branch instruction predicted by the branch predictor, the branch predictor uses the random value generated by the hardware logic to make a decision about updating the memory banks. Bits of a branch history pattern, along with the count, may also be used to generate the random value. The event counted may be a retire of an instruction or a cycle of a core or bus clock.

Abstract: An inspection method, and corresponding apparatus, enables classification of pupil images according to a process variable. The method comprises acquiring diffraction pupil images of a plurality of structures formed on a substrate during a lithographic process. A process variable of the lithographic process varies between formation of the structures, the variation of the process variable resulting in a variation in the diffraction pupil images. The method further comprises determining at least one discriminant function for the diffraction pupil images, the discriminant function being able to classify the pupil images in terms of the process variable.

Abstract: A three-dimensional stacked (3DS) memory module includes multiple memory chips and a data I/O chip physically integrated into the 3D stack. The data I/O chip includes multiple data interfaces and multiple respectively corresponding data buffers. A memory controller routes data traffic through all available data interfaces for maximum bandwidth. In some circumstances, the memory controller directs the data I/O chip to shut down (de-activate) one or more of the data interfaces (for example, to reduce power consumption of the memory module). All subsequent data traffic to and from the memory module is routed through the remaining active interfaces. All physical addresses in the 3DS memory module are addressable through the remaining active interfaces. In some circumstances, the memory controller directs the data I/O chip to re-activate some or all of the de-activated data interfaces. Once re-activated, subsequent data traffic to and from the memory module can again be routed through all active interfaces.

Abstract: A method and apparatus for controlling a voltage source converter to energize a DC link. A voltage order generating module generates a voltage order for controlling the voltage source converter to generate a DC voltage on the DC link. An oscillation damping module monitors the DC current flow to determine an indication of current oscillation and the voltage order is based on a voltage reference signal which is modulated by the indication of current oscillation to provide oscillation damping.

Abstract: Devices and methods for determining the quality thin film materials are disclosed. The thin film materials are provided on substrates forming thin film material structures. The devices comprise a housing, a THz module with a THz source emitter and a THz detector, and a reflective base moveable relative to the THz module and configured to support the thin film material structures. The THz source emitter is configured to irradiate the thin film materials. The THz detector is configured to measure at least one reflection of the irradiation. The device is configured to calculate a parameter indicative of the quality of the thin film material based on said reflection measurements.

Abstract: Dynamic characterization of complex high-order nonlinearity in transmitter (TX) and receiver (RX) signal chains of transceiver systems can be efficiently and accurately performed. A loopback connection may be used to facilitate self-characterization. Appropriate RX and TX configuration settings may be developed to facilitate de-coupling of individual RX and TX nonlinearities from measured cascade nonlinearity. The system's high-order response to a two-tone signal generation may be measured, and complex mathematical analysis may be performed to identify and isolate passband nonlinear components to extract a high-order memory-less model for the system. The extracted system model may be used in the corrective and non-iterative pre-distortion of generated signals and in the post-distortion of received signals to improve linearity performance of the transceiver.

Abstract: A device may determine one or more conditional parameters associated with determining whether a condition is satisfied during execution of a program. The one or more conditional parameters may vary over time. The device may execute the program to generate one or more execution parameters corresponding to the one or more conditional parameters. The device may compare the one or more execution parameters and the one or more conditional parameters. The device may determine that the condition is satisfied based on comparing the one or more execution parameters and the one or more conditional parameters. The device may perform an action, in association with the program, based on determining that the condition is satisfied.

Abstract: The present invention relates to a test method of a circuit, comprising: acquiring a plurality of value sets comprising values of a physical quantity linked to the activity of a circuit to be tested when the circuit executes an operation of a set of distinct cryptographic operations applied to a secret data, selecting at least a first subset in each value set, for each value set, counting by a processing unit occurrence numbers of values transformed by a first surjective function applied to the values of the first subset of the value set, to form an occurrence number set for the value set, for each operation of the operation set, and each of the possible values of a part of the secret data, computing a partial operation result, computing cumulative occurrence number sets by adding the occurrence number sets corresponding to the operations of the operation set, which when applied to a same value or equivalent value of the possible values of the part of the secret data, provide a partial operation result having

Abstract: An apparatus for testing an electrical component, having a simulation unit for producing a simulation signal, a plurality of test units, and at least one electrical connecting device, whereby the simulation unit and the plurality of test units are connected or connectable to each other in an electrically conductive fashion via the at least one connecting device, and the at least one connecting device has at least one electrical switch device, which is situated to make or break an electrical connection between the plurality of test units.

Abstract: Electronic test set embodiments and related methods are provided that can include a variety of safety components and/or processes which permit expandable or scalable automated testing of different types of equipment with or without installed sensitive, dangerous, vulnerable or expendable equipment. Embodiments can programmably or interface share measuring systems using expandable programmable interface systems that can scalably test a large number of components or electrical channels or bus lines. Embodiments can include multiple circuit board slot connectors adapted to receive programmable relay circuit cards that can selectively couple individual pins on ETS interface structures (e.g., cable connectors) to selected test equipment. Programmable relay circuit cards can be added to the ETS based on how many channels or bus connections are needed to interface with a system under test.

Abstract: Automatic test equipment (ATE) may include: a test instrument to implement a communication protocol to communicate to a unit under test (UUT), where the test instrument is memory storing bytecode that is executable, and where the test instrument being configured to identify an event in communication between the test instrument and the UUT and, in response to the event, to execute the bytecode. The ATE may also include a test computing system to execute a test program and an editor program, where the editor program is for receiving human-readable code and for generating the bytecode from the human-readable code, and the test program is for registering the event with the test instrument and for downloading the bytecode to the test instrument for storage in the memory.

Abstract: A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester.

Abstract: A method performed in a processing unit for determining calibration data to be used when processing data from a sensor unit connected to the processing unit, the method including receiving, from the sensor unit, an identifier which identifies and is calculated based on calibration data stored in the sensor unit, checking if there is an identifier stored in the processing unit identical to the received identifier, where the identifier stored in the processing unit identifies and is calculated based on calibration data stored in the processing unit, if an identical identifier is stored in the processing unit, using the calibration data stored in the processing unit identified by the identical identifier when processing data from the sensor unit, if no identical identifier is stored in the processing unit, requesting the sensor unit to transmit calibration data, and using the requested calibration data when processing data from the sensor unit.

Abstract: A calibration signal is transmitted from a transmitter antenna. A receiver antenna receives a loopback signal that results from an air coupling of the receiver antenna and the transmitter antenna. The loopback signal is compared to a target. If the loopback signal does not meet the target, then a gain of the calibration signal is adjusted and the loopback signal is again checked against the target. When the loopback signal meets the target, the gain is taken as a calibrated transmitter gain.

Abstract: A system and method is disclosed for detecting and correcting for errors in mapping table information stored in volatile memory of a non-volatile memory system. The method may include checking for mapping entry errors when retrieving mapping data for the non-volatile memory from a volatile memory cache. When an error is discovered, the method includes the processor generating a set of candidate mapping entries each having a different single bit difference from the mapping entry discovered to have an error. Each candidate is tested against one or more mapping data accuracy tests and, when one of the candidates is found to be a correct mapping entry based on the one or more tests, the original mapping table entry with the determined defect is replaced with the successful candidate mapping entry.

Abstract: The method relates to a Universal Plug and Play AV system, which comprises a media server included in a server device having a digital interface, to which a removable storage device is coupled, a media renderer included in a display device and a control point included in a control device for controlling the server device and the display device via Universal Plug and Play AV actions. The method comprises the steps of arranging an unmount icon in the display of the control device, unmounting the storage device in case said unmount icon is operated, and providing a feedback on the display device and/or the control device after said unmount action was performed on the server device.

Abstract: A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a first operand to be used. The machine instruction is executed, and execution includes for each block of memory of one or more blocks of memory of the first operand, generating a hash value using a 512 bit secure hash technique and at least one seed value of a parameter block of the machine instruction; and storing at least a portion of the generated hash value in a corresponding block of memory of the first operand, the generated hash value being at least a portion of a pseudorandom number.

Abstract: A system and method of electronic component authentication or component classification can reduce the vulnerability of systems (e.g., satellites, weapons, critical infrastructure, aerospace, automotive, medical systems) to counterfeits. Intrinsic deterministically random property data can be obtained from a set of authentic electronic components, processed, and clustered to create a classifier that can distinguish whether an unknown electronic component is authentic or counterfeit.

Abstract: A system includes a power converter including a primary bridge unit to receive a primary voltage from a voltage source, the primary bridge unit includes a first plurality of electronic switches, and each of the first plurality of electronics switches has a turn ON time and a turn OFF time. Further, the power converter includes a transformer including a primary winding and a secondary winding, the primary winding is coupled to the first plurality of electronic switches. Also, the power converter includes a secondary bridge unit including a second plurality of electronic switches coupled to the secondary winding. Additionally, the system includes a controller to determine an inductance of the power converter based on the primary voltage, the turn ON time of the first plurality of electronic switches, a switching cycle time of the power converter, and one of an average current and a peak current in the power converter.

Abstract: A difference measurement circuit having a first port and a second port for connection to a first set of nodes and a second set of nodes of a sensor unit. The circuit further has switching units for switching excitation signals emanating from excitation nodes from being applied to the first set of nodes (A, B) via the first port to being applied to the second set of nodes via the second port and for switching differential measurement signals measured at sensing nodes from being obtained from the second set of nodes via the second port to being obtained from the first set of nodes via the first port. The circuit further includes redundancy testing circuitry for evaluating the similarity or deviation between measurement signals obtained in different states of the switching units.