Abstract: Techniques are described for adjusting policy characteristics based on a determined similarity between routes. A similarity metric may be determined indicating the similarity between a first route followed by a vehicle and/or driver and a second (e.g., previous) route followed by the vehicle and/or driver. A similarity metric may indicate the similarity in movements, and changes in movement, exhibited by the vehicle on the routes. The similarity metric may be determined through analysis of real time data collected by in-vehicle sensor(s), mobile user device(s), external sensors or other data sources. Based on the similarity metric, a premium, a deductible, a price, or other characteristic(s) of a policy may be determined. In some examples, policy characteristics may be adjusted (e.g., in real time) based on the analysis according to changing risk conditions if a driver is following routes that are dissimilar from typical routes.

Abstract: In a method of circuit yield analysis, the method includes: detecting a plurality of failed samples respectively located at a plurality of failure regions in a multi-dimensional parametric space; clustering the failed samples to identify the failure regions; filtering features of the failed samples to determine a parameter component that is a non-principal component in affecting circuit yield; applying a dimensional reduction method on a dimension corresponding to the parameter component; and constructing a final importance sampling (IS) distribution function using a mixed Gaussian (mGaussian) function corresponding to all of the failure regions containing a rare failure event.

Abstract: A yield prediction apparatus is provided. The yield prediction apparatus may include at least one processor coupled to at least one non-transitory computer-readable medium. The at least one processor may be configured to receive a first variable associated with operating characteristics of a semiconductor device, perform a simulation for the operating characteristics of the semiconductor device, perform a neural network regression analysis using a result of the simulation to determine a first function for the first variable, and predict a yield of the semiconductor integrated circuit based on an advanced Monte Carlo simulation. An input of the advanced Monte Carlo simulation may include the determined first function.

Abstract: Method and apparatus for managing connections within a netlist include using a clone module to the connections between different components within the netlist. A buffer may be inserted between components of a netlist to split a connection into multiple segments and then moved into an associated first instance. The inclusion of the buffer allows for one or more of pin cloning and subway utilization to occur when mapping between a functional hierarchy to a physical hierarchy is performed.

Abstract: The present disclosure generally relates to the automated testing of a system that includes software or hardware components. In some embodiments, a testing framework generates a set of test cases for a system under test using a grammar. Each test case may perform an action, such as provide an input to the system under test, and result in an output from the system under test. The inputs and outputs are then compared to the expected results to determine whether the system under test is performing correctly. Specifically, the system under test may be analyzed to determine whether it is capable of properly processing control instructions and input signals and/or generating expected output control signals and additional control/feedback information. The data can then be interpreted in the grammar system and/or used as input to a fault isolation engine to determine anomalies in the system under test.

Abstract: A system includes a magnetic sense element for detecting an external magnetic field along a sensing axis and a magnetic field source proximate the magnetic sense element for providing an auxiliary magnetic field along the sensing axis. The magnetic sense element produces a first output signal having a magnetic field signal component, responsive to the external magnetic field, that is modulated by an auxiliary magnetic field signal component responsive to the auxiliary magnetic field. A processing circuit identifies from the first output signal an influence of a magnetic interference field on the auxiliary magnetic field signal component, the magnetic interference field being directed along a non-sensing axis of the magnetic sense element, and applies a correction factor to the magnetic field signal component to produce a second output signal in which the influence of the magnetic interference field is substantially removed.

Abstract: Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

Abstract: An inspection device comprises a stage for placing a device under test thereon, a dynamic characteristics test probe, a static characteristics test probe, and a control device configured to perform positional control by moving at least one of the stage, the dynamic characteristics test probe, and the static characteristics test probe. The control device performs the positional control such that the dynamic characteristics test probe is set to a dynamic characteristics test state in which the dynamic characteristics test probe is brought into contact with the electrode when the dynamic characteristics test is performed, and performs the positional control such that the static characteristics test probe is set to a static characteristics test state in which the static characteristics test probe is brought into contact with the electrode while the dynamic characteristics test probe is separated from the electrode when the static characteristics test is performed.

Abstract: Disclosed herein is a system for non-contact measurement of an optoelectronic property. The system includes a sensing element configured to amplify an electromagnetic wave having a specific frequency, a thin film disposed on the sensing element such that an optoelectronic property of the thin film is measured, and an optoelectronic property measuring server configured to extract a physical property of the thin film based on the optoelectronic property of the thin film obtained when the electromagnetic wave amplified by the sensing element passes through the thin film.

Abstract: A method and apparatus for estimating a state of health (SOH) of a battery are provided. The method includes measuring a voltage and a partial discharge time of the battery, acquiring a normalized partial discharge time using a battery model of a reference battery normalized with respect to a time, calculating a full discharge time of the battery based on the partial discharge time and the normalized partial discharge time, and estimating the SOH based on a ratio between a stored full discharge time of the reference battery and the full discharge time of the battery.

Abstract: A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state. The peaks in the power supply current are compared to the reference peaks for the power supply current for a reference circuit having a same functionality as the integrated circuit to determine the integrated circuit's fitness.

Abstract: A digital serial communication system includes a first serial communication circuit configured to exchange information utilizing a first communication protocol, a second serial communication circuit configured to exchange information utilizing a second communication protocol, and a common bus interface configured to couple the first serial communication circuit to a first serial communication bus implementing the first communication protocol, and configured to couple the second serial communication circuit to a second serial communication bus implementing the second communication protocol.

Abstract: A digital control circuitry for a MEMS gyroscope is provided. The digital control circuitry comprises a digital primary loop circuitry configured to process a digitized primary signal, a digital secondary loop circuitry configured to process a digitized secondary signal and a digital phase shifting filter circuitry configured to generate two phase shifted demodulation signals from the digitized primary signal. The digital secondary loop is configured to demodulate the digitized secondary signal using the two phase shifted demodulation signals.

Abstract: A branch predictor, has a plurality of memory banks having entries that hold prediction information used to predict a direction of branch instructions fetched and executed by a processor that comprises the branch predictor. A count of events that occur in the processor is provided to hardware logic that performs an arithmetic and/or logical operation, e.g., XOR, on predetermined bits of the count to generate a random value. In response to the processor determining a correct direction of a branch instruction predicted by the branch predictor, the branch predictor uses the random value generated by the hardware logic to make a decision about updating the memory banks. Bits of a branch history pattern, along with the count, may also be used to generate the random value. The event counted may be a retire of an instruction or a cycle of a core or bus clock.

Abstract: An inspection method, and corresponding apparatus, enables classification of pupil images according to a process variable. The method comprises acquiring diffraction pupil images of a plurality of structures formed on a substrate during a lithographic process. A process variable of the lithographic process varies between formation of the structures, the variation of the process variable resulting in a variation in the diffraction pupil images. The method further comprises determining at least one discriminant function for the diffraction pupil images, the discriminant function being able to classify the pupil images in terms of the process variable.

Abstract: A three-dimensional stacked (3DS) memory module includes multiple memory chips and a data I/O chip physically integrated into the 3D stack. The data I/O chip includes multiple data interfaces and multiple respectively corresponding data buffers. A memory controller routes data traffic through all available data interfaces for maximum bandwidth. In some circumstances, the memory controller directs the data I/O chip to shut down (de-activate) one or more of the data interfaces (for example, to reduce power consumption of the memory module). All subsequent data traffic to and from the memory module is routed through the remaining active interfaces. All physical addresses in the 3DS memory module are addressable through the remaining active interfaces. In some circumstances, the memory controller directs the data I/O chip to re-activate some or all of the de-activated data interfaces. Once re-activated, subsequent data traffic to and from the memory module can again be routed through all active interfaces.

Abstract: A method and apparatus for controlling a voltage source converter to energize a DC link. A voltage order generating module generates a voltage order for controlling the voltage source converter to generate a DC voltage on the DC link. An oscillation damping module monitors the DC current flow to determine an indication of current oscillation and the voltage order is based on a voltage reference signal which is modulated by the indication of current oscillation to provide oscillation damping.

Abstract: Devices and methods for determining the quality thin film materials are disclosed. The thin film materials are provided on substrates forming thin film material structures. The devices comprise a housing, a THz module with a THz source emitter and a THz detector, and a reflective base moveable relative to the THz module and configured to support the thin film material structures. The THz source emitter is configured to irradiate the thin film materials. The THz detector is configured to measure at least one reflection of the irradiation. The device is configured to calculate a parameter indicative of the quality of the thin film material based on said reflection measurements.

Abstract: Dynamic characterization of complex high-order nonlinearity in transmitter (TX) and receiver (RX) signal chains of transceiver systems can be efficiently and accurately performed. A loopback connection may be used to facilitate self-characterization. Appropriate RX and TX configuration settings may be developed to facilitate de-coupling of individual RX and TX nonlinearities from measured cascade nonlinearity. The system's high-order response to a two-tone signal generation may be measured, and complex mathematical analysis may be performed to identify and isolate passband nonlinear components to extract a high-order memory-less model for the system. The extracted system model may be used in the corrective and non-iterative pre-distortion of generated signals and in the post-distortion of received signals to improve linearity performance of the transceiver.

Abstract: A device may determine one or more conditional parameters associated with determining whether a condition is satisfied during execution of a program. The one or more conditional parameters may vary over time. The device may execute the program to generate one or more execution parameters corresponding to the one or more conditional parameters. The device may compare the one or more execution parameters and the one or more conditional parameters. The device may determine that the condition is satisfied based on comparing the one or more execution parameters and the one or more conditional parameters. The device may perform an action, in association with the program, based on determining that the condition is satisfied.

Abstract: The present invention relates to a test method of a circuit, comprising: acquiring a plurality of value sets comprising values of a physical quantity linked to the activity of a circuit to be tested when the circuit executes an operation of a set of distinct cryptographic operations applied to a secret data, selecting at least a first subset in each value set, for each value set, counting by a processing unit occurrence numbers of values transformed by a first surjective function applied to the values of the first subset of the value set, to form an occurrence number set for the value set, for each operation of the operation set, and each of the possible values of a part of the secret data, computing a partial operation result, computing cumulative occurrence number sets by adding the occurrence number sets corresponding to the operations of the operation set, which when applied to a same value or equivalent value of the possible values of the part of the secret data, provide a partial operation result having

Abstract: An apparatus for testing an electrical component, having a simulation unit for producing a simulation signal, a plurality of test units, and at least one electrical connecting device, whereby the simulation unit and the plurality of test units are connected or connectable to each other in an electrically conductive fashion via the at least one connecting device, and the at least one connecting device has at least one electrical switch device, which is situated to make or break an electrical connection between the plurality of test units.

Abstract: Electronic test set embodiments and related methods are provided that can include a variety of safety components and/or processes which permit expandable or scalable automated testing of different types of equipment with or without installed sensitive, dangerous, vulnerable or expendable equipment. Embodiments can programmably or interface share measuring systems using expandable programmable interface systems that can scalably test a large number of components or electrical channels or bus lines. Embodiments can include multiple circuit board slot connectors adapted to receive programmable relay circuit cards that can selectively couple individual pins on ETS interface structures (e.g., cable connectors) to selected test equipment. Programmable relay circuit cards can be added to the ETS based on how many channels or bus connections are needed to interface with a system under test.

Abstract: Automatic test equipment (ATE) may include: a test instrument to implement a communication protocol to communicate to a unit under test (UUT), where the test instrument is memory storing bytecode that is executable, and where the test instrument being configured to identify an event in communication between the test instrument and the UUT and, in response to the event, to execute the bytecode. The ATE may also include a test computing system to execute a test program and an editor program, where the editor program is for receiving human-readable code and for generating the bytecode from the human-readable code, and the test program is for registering the event with the test instrument and for downloading the bytecode to the test instrument for storage in the memory.

Abstract: A method performed in a processing unit for determining calibration data to be used when processing data from a sensor unit connected to the processing unit, the method including receiving, from the sensor unit, an identifier which identifies and is calculated based on calibration data stored in the sensor unit, checking if there is an identifier stored in the processing unit identical to the received identifier, where the identifier stored in the processing unit identifies and is calculated based on calibration data stored in the processing unit, if an identical identifier is stored in the processing unit, using the calibration data stored in the processing unit identified by the identical identifier when processing data from the sensor unit, if no identical identifier is stored in the processing unit, requesting the sensor unit to transmit calibration data, and using the requested calibration data when processing data from the sensor unit.

Abstract: A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester.

Abstract: A calibration signal is transmitted from a transmitter antenna. A receiver antenna receives a loopback signal that results from an air coupling of the receiver antenna and the transmitter antenna. The loopback signal is compared to a target. If the loopback signal does not meet the target, then a gain of the calibration signal is adjusted and the loopback signal is again checked against the target. When the loopback signal meets the target, the gain is taken as a calibrated transmitter gain.

Abstract: A system and method is disclosed for detecting and correcting for errors in mapping table information stored in volatile memory of a non-volatile memory system. The method may include checking for mapping entry errors when retrieving mapping data for the non-volatile memory from a volatile memory cache. When an error is discovered, the method includes the processor generating a set of candidate mapping entries each having a different single bit difference from the mapping entry discovered to have an error. Each candidate is tested against one or more mapping data accuracy tests and, when one of the candidates is found to be a correct mapping entry based on the one or more tests, the original mapping table entry with the determined defect is replaced with the successful candidate mapping entry.

Abstract: The method relates to a Universal Plug and Play AV system, which comprises a media server included in a server device having a digital interface, to which a removable storage device is coupled, a media renderer included in a display device and a control point included in a control device for controlling the server device and the display device via Universal Plug and Play AV actions. The method comprises the steps of arranging an unmount icon in the display of the control device, unmounting the storage device in case said unmount icon is operated, and providing a feedback on the display device and/or the control device after said unmount action was performed on the server device.

Abstract: A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a first operand to be used. The machine instruction is executed, and execution includes for each block of memory of one or more blocks of memory of the first operand, generating a hash value using a 512 bit secure hash technique and at least one seed value of a parameter block of the machine instruction; and storing at least a portion of the generated hash value in a corresponding block of memory of the first operand, the generated hash value being at least a portion of a pseudorandom number.

Abstract: A system and method of electronic component authentication or component classification can reduce the vulnerability of systems (e.g., satellites, weapons, critical infrastructure, aerospace, automotive, medical systems) to counterfeits. Intrinsic deterministically random property data can be obtained from a set of authentic electronic components, processed, and clustered to create a classifier that can distinguish whether an unknown electronic component is authentic or counterfeit.

Abstract: A system includes a power converter including a primary bridge unit to receive a primary voltage from a voltage source, the primary bridge unit includes a first plurality of electronic switches, and each of the first plurality of electronics switches has a turn ON time and a turn OFF time. Further, the power converter includes a transformer including a primary winding and a secondary winding, the primary winding is coupled to the first plurality of electronic switches. Also, the power converter includes a secondary bridge unit including a second plurality of electronic switches coupled to the secondary winding. Additionally, the system includes a controller to determine an inductance of the power converter based on the primary voltage, the turn ON time of the first plurality of electronic switches, a switching cycle time of the power converter, and one of an average current and a peak current in the power converter.

Abstract: A difference measurement circuit having a first port and a second port for connection to a first set of nodes and a second set of nodes of a sensor unit. The circuit further has switching units for switching excitation signals emanating from excitation nodes from being applied to the first set of nodes (A, B) via the first port to being applied to the second set of nodes via the second port and for switching differential measurement signals measured at sensing nodes from being obtained from the second set of nodes via the second port to being obtained from the first set of nodes via the first port. The circuit further includes redundancy testing circuitry for evaluating the similarity or deviation between measurement signals obtained in different states of the switching units.

Abstract: Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The signal is then returned to the SoC, where it may be examined by a closed-loop engine of the SoC. A result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

Abstract: A semiconductor memory device which stores operation environment information such as use time data, operating temperature data, or operating voltage data includes an internal circuit configured to perform a function set in the semiconductor memory device, and an operation environment information storing circuit configured to sense information about an operation environment of the semiconductor memory device when the semiconductor memory device operates, store the operation environment information in non-volatile memory cells, and provide the operation environment information stored in the non-volatile memory cells to an outside based on a request of reading out information.

Abstract: A method for projecting an electron beam used notably in lithography by direct or indirect writing as well as in electron microscopy, is provided. Notably for critical dimensions or resolutions of less than 50 nm, the proximity effects created by the forward and backward scattering of the electrons of the beam in interaction with the target must be corrected. This is traditionally done using the convolution of a point spread function with the geometry of the target. In the prior art, said point spread function uses Gaussian distribution laws. At least one of the components of the point spread function is a linear combination of Voigt functions and/or of functions approximating Voigt functions, such as the Pearson VII functions. In certain embodiments, some of the functions are centered on the backward scattering peaks of the radiation.

Abstract: This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or pages. By performing a test transaction to program each bit of each such unit, the maximum expected programming time of each unit may be determined in advance and used for scheduling purposes. For example, in a straightforward implementation, a relatively accurate, empirically measured time limit may be identified and used to efficiently manage and schedule flash memory transactions without awaiting ultimate resolution of attempts to write to a non-responsive page. This disclosure also provides other uses of empirically-measured maximum flash memory transaction times, including via multiple memory modes and prioritized memory; for example, if a high performance mode is desired, low variation in flash memory transaction times may be tolerated, and units not satisfying these principles may be marked relatively quickly.

Abstract: An air flow meter has a housing, a flow rate sensor, and a physical-quantity measuring sensor. The housing therein defines a bypass passage into which a part of air flowing in a duct flows. The flow rate sensor is disposed in the bypass passage. The physical-quantity measuring sensor measures a physical quantity of air flowing in the duct and is disposed separately from the flow rate sensor. The housing has a recessed portion that is recessed from an inner wall surface of the bypass passage and that has a blind-passage shape. The physical-quantity measuring sensor is disposed in the recessed portion.

Abstract: A method of operating a test device for a logic-based processing device includes the steps of providing an original set of test instructions, generating one or more Quick Error Detection (QED) test programs, and causing the one or more QED test programs to be executed on the logic-based processing device. Each one of the QED test programs includes the original test program with additional instructions inserted at strategic locations within the original set, wherein the additional instructions and the strategic locations vary between each of the QED test programs.

Abstract: A power over Ethernet (PoE) connection check method comprising: for a first time period, generating a first detection power over the first set of wires while not generating a second detection power over the second set of wires and obtaining a first indication of a power attribute over the first set of wires; during a second time period, generating the first detection power and generating a second detection power, greater than the first detection power, over the first set of wires; during the second time period, obtaining a second indication of the power attribute over the first set of wires; determining a first difference between the first indication and the second indication; and controlling a first power enable circuit and a second power enable circuit to provide power to the powered device over the first and second sets of wires respectively, responsive to the determined difference.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.

Abstract: A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

Abstract: A method for monitoring a power supply connected to a superordinate controller via a signal line, wherein the superordinate controller queries whether the power supply is operating faultlessly at variable intervals, where during faultless operation, a power-good signal is continuously transmitted by the power supply to the superordinate controller via the signal line and, if a fault occurs, an indicating signal is transmitted by the power supply to the superordinate controller via the signal line as a switching sequence of high and low signals such that each signal change of the switching sequence occurs only after a time period that is longer than an expected greatest query interval and each signal of the switching sequence that does not correspond to the power-good signal is shorter than a specified signal duration for indicating a total failure of the power supply, whereby the superordinate controller receives more information than previously.

Abstract: An electronic device is provided. The electronic device includes a printed circuit board (PCB), an antenna structure, a radio frequency signal transceiving circuit and a testing structure. The antenna structure is disposed on the PCB. The radio frequency signal transceiving circuit is disposed on the PCB, and is connected to the antenna structure through a conductive line. The testing structure includes a testing point and a grounding structure. The testing point is disposed on the conductive line, and the grounding structure is disposed on the PCB.

Abstract: The operation of electrical appliances receiving electrical power from an electrical system may be indirectly monitored using monitoring units engaged with outlets on branch circuits of the electrical system. Electrical systems providing power to appliances to be monitored in accordance with the present invention may comprise split phase alternating current systems, tri-phase systems, or any other type of electrical system. Known loads may be applied to calibrate the monitoring system. The monitoring system may measure the power consumption of appliances operating on the electrical system and/or detect possible fault conditions. The monitoring system may be distributed across multiple monitoring units and other computing devices. Output devices may be used to output a summary of the power consumption or other operation of monitored electrical appliances.

Abstract: A built-in self-test circuit includes a command storage unit that stores commands inputted from an external device, an input/output control unit that controls the command storage unit to sequentially store the commands and sequentially output stored commands as internal commands in a test operation, and a command decoder unit that decodes the internal commands outputted from the command storage unit and outputs a test command.

Abstract: Necessary unit data indicative of the type and number of equipment units used in component mounting operation is obtained on the basis of production plan data, mounting data, and component library for each of production lots in advance. New allocation processing for allocating an equipment unit necessary for production execution of a new production lot to be newly produced on an electronic component mounting line for the new production lot on the basis of the necessary unit data is executed, and component reservation processing for registering the allocation result as the inventory data is conducted by a unit reservation unit.

Abstract: On-chip field testing methods and apparatus are disclosed. Example on-chip testers disclosed herein include a decoder having a test data input and a test stimuli interface. Disclosed example on-chip testers also include a multiplexer having a first multiplexer interface coupled to the test stimuli interface, a second multiplexer interface coupled to an automatic test equipment interface, a third multiplexer interface coupled to a design-for-testing subsystem interface and an interface selection input. Disclosed example on-chip testers further include a memory having a memory interface coupled to the test data input.

Abstract: A method for diagnosing an electrical circuit including at least one electrical device, an actuator for the device controlled by a high side actuating switch and a low side actuating switch, and at least one additional switch not in series with any of the HS or LS switch, the method including: to each of the possible statuses of the circuit, giving a code; sequentially putting the circuit in at least some of these statuses for a given time period; during each of these periods, measuring voltage and/or current in different parts of the circuit and giving a code to the measurement; and establishing a diagnosis of correct functioning or of a malfunctioning of at least some elements of the circuit according to a pre-established correlation between the status codes and the measurement codes.

Abstract: The invention provides methods and devices that address problems encountered when attempting to accurately reconstruct visual stimuli being displayed to a user as they interact with online-content, typically through a browser interface. In one embodiment, the invention provides for the browser to maintain a record of selected technical parameters and relevant data that may impact the manner in which online-content is being displayed to the user, taking into consideration the current context in which the browser is being operated. In another embodiment, the invention is a device for recording events as reported from a browser interface. The events are recorded in a selected format and syntax to form a primary index of events and related outcomes which comprise the users interface experience. In operation, the devices detect events as detected at the browser interface. Next, the devices identify, categorize, and filter detected events as to their relevance to the visual stimuli being presented to the user.