Abstract: A digital on-die-test engine (OTE) is disclosed to generate stimuli signals for an analog/RF circuit, where the OTE is embedded within the circuitry. The stimuli signals are injected into the circuit, feed through the circuit, and are received back into the OTE for analysis. The OTE includes an input subsystem to receive signals from various locations throughout the circuit. The received signals are sub-sampled before being tested. The OTE includes memory-aware and memory-less algorithms for testing the signals. The OTE is capable of changing the configuration of the circuit, where needed, following the tests.

Abstract: A method for calculating resistive values of an electronic circuit represented in the form of masks and connections includes defining the circuit in the form of a first list of electrical components and connections between them, identifying circuit entry and exit ports, selecting part of the resistive components of the circuit alone, producing a matrix of resistances of the resistive components alone selected in the previous step, and calculating equivalent resistances.

Abstract: A supervisor monitoring system for autonomous test supervision is presented. A system can comprise a first supervisor monitor (SM) and a second SM, each configured to simultaneously monitor one or more tests conducted by one or more testing apparatus. First and second SMs can be configured to verify the other's integrity throughout a testing procedure, providing a failsafe system. The first and second SMs can be interlocked so that if the first SM detects a fault at the second SM, the first SM can interrupt testing monitored at the first SM, and can also interrupt testing monitored at the second SM, and vice versa. An SM can be configured to control a safety relay configured to couple a power channel of a battery exerciser to a battery cell, and be configured to monitor input at the battery exerciser from the cell to determine whether a test constraint has been violated.

Abstract: A method for emulating and debugging a microcontroller is described. In one embodiment, an event thread is executed on an emulator that operates in lock-step with the microcontroller. Event information is sampled at selected points. Trace information is also recorded at the selected points. As such, the event information and trace information are effectively pre-filtered. Accordingly, it is not incumbent on a designer to read and understand the event and trace information and sort out the information that is of interest. Instead, this task is essentially done automatically, helping the designer and reducing the probability of error. Furthermore, because only selected event and trace information is recorded, the resources of the in-circuit emulator system are not taxed.

Abstract: A computer-implemented system, method, and storage device simulate a periodic voltage waveform in a network model of the integrated circuit design. The method then determines resultant current values in each segment of nets of the integrated circuit design resulting from the periodic voltage waveform and performs a Fourier transform of the periodic voltage waveform to generate a frequency domain representation of the periodic voltage waveform. The frequency domain representation comprises multiple Fourier terms, each of the Fourier terms is a frequency that is a multiple of the base frequency. Next, the method performs an AC analysis of the resultant voltage at each frequency of the multiple Fourier terms. The AC analysis provides an electrical current value for each of the frequencies of the Fourier terms for each of the nets. This allows the method to compute a root mean square current through each of the nets based on the AC analysis.

Abstract: Observability and controllability in a test of an analog LSI are increased. Analog signals input from input terminals IN1 to IN3 are supplied to diffusion layer regions 221, 223 and 225 via transistors 301 to 303, and are accumulated as electric charge. A clock signal is applied to signal lines 121 and 122 alternately connected to gate electrodes 211 to 216, thus allowing the accumulated electric charge to be transferred to the right direction. Electric charge/voltage conversion amplifiers 411 to 413 are connected to the diffusion layer regions 221, 223 and 225, and the accumulated electric charge is converted into voltage and is output to output terminals VOUT1 to VOUT3 as analog signals. A scan-in terminal Sin is connected to a diffusion layer region 220, and a scan-out terminal Sout is connected to the diffusion layer region 225 via an electric charge/voltage conversion amplifier 401.

Abstract: A process for testing an integrated circuit includes collecting a set of points of a physical property while the integrated circuit is executing a multiplication, dividing the set of points into a plurality subsets of lateral points, calculating an estimation of the value of the physical property for each subset, and applying to the subset of lateral points a step of horizontal transversal statistical processing by using the estimations of the value of the physical property, to verify a hypothesis about the variables manipulated by the integrated circuit.

Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

Abstract: A test circuit for testing a flexible printed board (FPC) is provided, the test circuit includes a parameter preset module, a comparison module, and a prompt module. The parameter preset module is used to preset a parameter range indicating the suitable range of the resistance value of the FPC, and is further configured to connect to the FPC and convert the resistance value of the FPC to a related parameter. The comparison module compares the related parameter with the parameter range preset by the parameter preset module, and produces a comparison result. The prompt module produces a corresponding prompt signal according to the comparison result.

Abstract: An integrated circuit (IC) including a warranty and enforcement system, and a related design structure and HDL design structure are disclosed. In one embodiment, an IC includes a parameter obtainer for obtaining a value of a parameter of the IC; a warranty data storage system for storing warranty limit data regarding the IC; a comparator for determining whether a warranty limit has been exceeded by comparing the value of the parameter to a corresponding warranty limit; and an action taker for taking a prescribed action in response to the warranty limit being exceeded.

Abstract: On-chip high speed clock control techniques for testing circuits with multiple clock systems are disclosed. The techniques allow certain (e.g. compatible) high speed clocks to be activated with predefined waveforms during a capture period of a logic test, based on a clock control signal. The clock control signal may be supplied via a JTAG control port or via a scan chain load port. The clock control signal may also be generated by a BIST controller. The techniques may ensure glitch-free transitions from slow speed clocks during a shift period to fast speed clocks during a capture period.

Abstract: Methods and systems using one or more expert systems to increase electronic device reliability. One embodiment is a method to screen an electronic device by one or more expert systems to detect a potential failure of the electronic device, selectively testing the electronic device when the screening indicates a potential failure, and providing one or more outputs if the selective testing of the electronic device indicates a failure. A second embodiment is a system to screen an electronic device by one or more expert systems to detect a potential failure, selectively testing the electronic device when the screening indicates a potential failure and providing one or more outputs if the selective testing of the electronic device indicates the failure.

Abstract: A magnetic field sensor includes built in self-test circuits that allow a self-test of most of, or all of, the circuitry of the magnetic field sensor, including self-test of a magnetic field sensing element used within the magnetic field sensor, while the magnetic field sensor is functioning in normal operation.

Abstract: A method of and system for inspecting multi-layer reticles. The method includes: selecting a multi-layer reticle having an array of cells arranged in R rows and C columns; defining a full inspection region that includes all cells of the array of cells; and when R is equal to one (or is greater than two) and C is greater than two (or is equal to one) and a cell of the array of cells is a dummy cell in a first or last position of a row (or of a column) of the array of cells, then reducing the full inspection region to generate a shrunken inspection region that does not include the dummy cell, and then inspecting the shrunken inspection region for defects. If the dummy cell is between two non-dummy cells, then the dummy cell is a copy of one of the non-dummy cells, but is not inspected.

Abstract: A method of testing a processing includes performing a test of at least one logic block of a processor of a data processing system; receiving an interrupt; stopping the performing the test for the processor to respond to the interrupt, wherein the stopping the performing the test includes storing test data of the test to a memory prior to the processor responding to the interrupt; and after the processor responds to the interrupt, resuming performing the test, wherein the resuming performing the test includes retrieving the test data from the memory and using the retrieved test data for the resuming performing the test.

Abstract: A gas density transducer including: a piezoresistive bridge sensor operative to provide an output indicative of an applied pressure, a computing processor having multiple inputs and at least one output, with the output of the bridge sensor coupled to an input of the processor; a temperature sensor coupled to an input of the processor for providing at an output a signal indicative of a temperature of the bridge sensor, the output of the temperature sensor coupled to an input of the processor; and, at least one memory accessible by the processor and having stored therein: compensation coefficients for compensating the output of the bridge sensor for temperature variation; an algorithm for solving Van der Waal's equation; and, code for providing at an output of the processor a signal indicative of a gas density when the bridge is subjected to a gas containing environment.

Abstract: A method for testing multiple features of an electronic device sets a global timer and a series of feature test timers. The feature test timers are arranged in a sequence. The global timer is firstly activated. The feature test timers are then activated one by one according to the sequence and one or more features of the electronic device corresponding to each of the feature test timers are tested until the global timer times out.

Abstract: Apparatus for testing a conducted energy weapon includes analyzer to produce characteristic signals representative of characteristics of electrical current pulses delivered by the weapon into a resistive load when the weapon is discharged. Risk estimation device responsive to the characteristic signals produces a risk estimate representative of a risk of injury to a targeted subject due to electrical stimulation, or alternatively representative of a risk of failure to incapacitate the targeted subject. Indicator device responsive to the risk estimate indicates the risk of injury, or alternatively the risk of failure to incapacitate, and warns the user of the apparatus when the risk exceeds a predetermined threshold.

Abstract: Configuring at least one radio frequency (RF) instrument according to a plurality of RF measurement configurations for performing a plurality of tests on a device under test (DUT). A list of RF measurement configurations may be stored in a computer memory. The list of RF measurement configurations comprises a plurality of parameters for configuring operation of the at least one instrument. Information regarding the list of RF measurement configurations (e.g., a data stream) may be provided to the at least one RF instrument. The at least one RF instrument may perform the plurality of tests on the DUT, including the at least one RF instrument configuring itself according to the RF measurement configurations based on processing of the information. Configuring enables the at least one RF instrument to perform the plurality of tests on the DUT in a deterministic manner.

Abstract: A measured device coupled to test equipment providing at least two test factors and receiving a test result is disclosed. The measured device includes a combinatorial logic circuit and a main circuit. The combinatorial logic circuit includes a first storage module and a second storage module. The first storage module stores the test factors according to a first operation clock. The second storage module stores and outputs at least two output factors according to a second operation clock. The frequency of the second operation clock is higher than the frequency of the first operation clock. When the test factors are stored in the first storage module, the test factors stored in the first storage module are served as the output factors and the output factors are output and stored in the second storage module. The main circuit generates the test result according to the output factors output by the second storage module.

Abstract: A tester module for automatic test equipment (ATE) includes test instruments for testing an integrated circuit device under test (DUI). A plurality of sensors include sensors coupled to or proximate to the test instruments for detecting a plurality of different maintenance triggers associated with the test instruments. A memory stores code including operating system code for controlling the test instruments and for implementing a system maintenance compliance tool. A processor is coupled to the test instruments, the sensors and the memory. The processor runs the operating system code including the system maintenance compliance tool. The system maintenance compliance tool upon receiving notification of at least a first maintenance trigger automatically blocks the ATE being used for the testing. The system maintenance compliance tool can include a listing of needed maintenance actions associated with the maintenance triggers that when completed automatically releases the ATE to allow resumption of testing.

Abstract: A leak current calculation apparatus includes an acquiring section for acquiring partial circuit information, and a grouping section for forming a plurality of groups each comprising a part of the partial circuits connected with each other and for generating group information. The apparatus includes a leak difference value calculating section for calculating a leak difference value, which is a difference between a provisional maximum value acquired by adding up the maximum values of the leak current values of all the partial circuits and a sum of maximum values of the leak current values contained in the group information of the groups, and a maximum leak current calculating section for calculating the maximum leak current value of the integrated circuit by adjusting the provisional maximum value with the leak difference value.

Abstract: A tester for testing a device under test has a first channel unit and a second channel unit. The first channel unit has a corresponding first pin connection for a signal from a device under test, a corresponding first test processor adapted to process, at least partially, data obtained from the first pin connection, and a corresponding first memory coupled with the first test processor and adapted to store data provided by the first test processor. The first channel unit is adapted to transfer at least a part of the data obtained from the first pin connection to the second channel unit as transfer data. The second channel unit has a corresponding second test processor adapted to process, at least partly, the transfer data from the first channel unit.

Abstract: An apparatus, system and method are provided for testing a battery-powered electronic device-under-test in a transport frame engaged with a test fixture. A transport frame power supply is arranged to provide power to the DUT in a pre-testing stage. A switching circuit is arranged to switch from the transport frame power supply to a test fixture power supply in response to receiving a power switching signal indicating satisfaction of a pre-testing condition. Power from the test fixture power supply can then be switched back to the first transport frame, or to a second transport frame, to begin testing a second DUT. The ability to start a DUT test without having to wait for the DUT to boot-up in the test fixture reduces test time and increases efficiency of use of test equipment.

Abstract: Disclosed are a method and an apparatus for an intact evaluation of the unit cells in a fuel cell stack. Since the degradation of the unit cells can be detected intactly, i.e. without disassembly of the stack, the time required for the detection and analysis thereof can be greatly reduced.

Abstract: Wafer sort data can be converted to binary data, whereby each integrated circuit of the wafer is assigned a value of one or zero, depending on whether test data indicates the integrated circuit complies with a specification. In addition, each integrated circuit is assigned position data to indicate its position on the wafer. A frequency transform, such as a multidimensional discrete Fourier transform (DFT), is applied to the binary wafer sort data and position data to determine a spatial frequency spectrum that indicates error patterns for the wafer. The spatial frequency spectrum can be analyzed to determine the characteristics of the wafer formation process that resulted in the errors, and the wafer formation process can be modified to reduce or eliminate the errors.

Abstract: Disclosed are a method and an apparatus for detecting abnormality of a current sensor operative to measure a charge or discharge current of a battery pack. The method comprises measuring current and voltage of the battery pack; and detecting abnormality of the current sensor by comparing variations in current and voltage over a predetermined time with a current reference value and a voltage reference value, respectively. According to the present invention, it is capable of improving reliability of the battery pack, and in case that the current sensor is out of order, of protecting the battery pack from dangerous accidents such as explosion.

Abstract: A system includes a plurality of devices that are connected in series and a controller that communicates with the devices. Each of the devices has a plurality of input ports and corresponding output ports. The outputs of one device and the inputs of a next device are interconnected. The controller is coupled to the first device and the last device of the series-connection. The controller applies a test pattern to the plurality of input ports at the first device connected in series, by the controller. Each data channel defines a data path between corresponding pairs of input and output ports of the first and last devices. A data channel is enabled if the test pattern is detected at its corresponding output port.

Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and can calculate an effective reliability stress, maintain the effective reliability stress over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, and control one or more operating parameters of the processor based on the effective reliability stress. Other embodiments are described and claimed.

Abstract: Semiconductor devices with self-heating structures, methods of manufacture thereof, and testing methods are disclosed. In one embodiment, a semiconductor device includes a workpiece, an active electrical structure disposed over the workpiece, and at least one self-heating structure disposed proximate the active electrical structure.

Abstract: A fault diagnosis apparatus and method capable of simultaneously detecting the fault of a multiplexer and the fault of an A/D converter and isolating and identifying causes of these faults, the multiplexer and the A/D converter being used in a multi-channel analog input/output circuit. Test-voltage values are inputted from a diagnosis-voltage input unit into the multiplexer and the A/D converter constituting an analog-signal conversion unit, the multiplexer having plural channels, the A/D converter converting outputs from the multiplexer into digital signals, the test-voltage values being different from each other for each channel of the multiplexer. Comparisons are made between the digital voltage values and the test-voltage values inputted, the digital voltage values being outputted for each channel of the multiplexer. From this comparison result, it is judged whether the multiplexer is at fault or the A/D converter is at fault.

Abstract: Mechanisms for controlling an operation of one or more cores on an integrated circuit chip are provided. The mechanisms retrieve, from an on-chip non-volatile memory of the integrated circuit chip, baseline chip characteristics data representing operational characteristics of the one or more cores prior to the integrated circuit chip being operational in the data processing system. Current operational characteristics data of the one or more cores are compared with the baseline chip characteristics data. Deviations of the current operational characteristics data from the baseline chip characteristics data are determined and used to determine modifications to an operation of the one or more cores. Control signals are sent to one or more on-chip management units based on the determined modifications to cause the operation of the one or more cores to be modified.

Abstract: A test device for testing a motherboard includes a connector, a processor, and a controller. The motherboard includes a slot including a sleep unit and a wake port. The connector is inserted into the slot to make an electrical connection with the motherboard. The processor includes a first pin connected to the wake port, a second pin connected to the sleep unit, and a control port sending control signals to the first pin and the second pin. The controller includes a first control module, a second control module, and a timer. The timer is programmed with at least two time points. Wherein the first control module and the second control module respectively send signals to the control port at each time point, to control the motherboard to enter the sleep mode and wake mode by turns.

Abstract: In a method for testing integrity of signals transmitted from hard disk interfaces using a computing device, the computing device connects to an oscilloscope and a mechanical arm that is equipped with a test fixture. The mechanical arm controls the test fixture to make contact with one of the hard disk interfaces to be tested. The method adjusts an intensity grade of the signals through the hard disk interface, and controls the hard disk interface to produce a signal corresponding to the adjusted intensity grade. The test fixture obtains the signal from the hard disk interface, and the oscilloscope measures one or more test parameters of the signal. The method analyzes values of the test parameters to find an optimal signal, determines an intensity grade of the optimal signal as a driving parameter of the hard disk interface, and generates a test report of the hard disk interfaces.

Abstract: Testing system and method with wireless transmission tested data function are provided. An electronic device performs self-testing by a testing program or a testing instrument so as to generate tested data and transmits the tested data to a server via a wireless network. A processing device linked to the server via the wireless network obtains and processes the tested data so as to generate processed data. The processing device further transmits the processed data to the server via the wireless network. Accordingly, the processing device immediately and remotely monitors the electronic device, which is located on a production line, thereby effectively reducing manpower and costs.

Abstract: According to one aspect, an integrated magnetic particle measurement device for detecting a presence or absence of magnetic particles in a sample volume includes at least one sensor cell having a differential sensor pair. An active sensor oscillator frequency is responsive to one or more magnetic particles situated within a sample volume. The sensor cell is configured to be operative in the absence of an externally applied magnetic field. A frequency measurement circuit provides as a time-multiplexed output a first count representative of the active sensor oscillator frequency and a second count representative of the reference sensor oscillator frequency. A calculated difference between the first count and the second count is indicative of a presence or an absence of one or more magnetic particles within the sample volume. An integrated magnetic particle measurement system array and a method for detecting one or more magnetic particles are also described.

Abstract: The present invention certifies control modules of engineered safety feature instruments for a power plant automatically. The control modules can be tested before storing or operating. The test is done with enhanced testing speed and saved cost. Thus, safety of the control modules is confirmed.

Abstract: A front end of a vector network analyzer (VNA) on an integrated circuit includes a clock generator and two ports. The VNA couples to a device under test (DUT) using the two ports. Each port may include a plurality of receivers and a VSWR bridge, and can be configured as either an input or an output. The clock generator can generate a stimulus signal, an in-phase I clock signal, and a quadrature-phase Q clock signal. The output port provides the stimulus signal to the DUT and measures both reference and reflected power from the DUT, such as by utilizing two receivers by using direct conversion and the I and Q clock signals. The input port measures transmitted power through the DUT using a second VSWR bridge and one of its receivers by using direct conversion along with the I and Q clock signals. The VNA IC can provide S-parameter measurements to a processing unit for further processing and/or analysis to compute the DUT S-parameters.

Abstract: Provided is a test wafer unit for testing a plurality of semiconductor chips formed on a semiconductor wafer, the test wafer unit including: a test wafer having a shape corresponding to a shape of the semiconductor wafer; and a plurality of test circuits formed on the test wafer, each test circuit provided to correspond to two or more of the plurality of semiconductor chips and testing the two or more semiconductor chips. The test wafer unit may include a plurality of connection terminals formed on the test wafer in one to one relation with test terminals of the plurality of semiconductor chips, where each of the plurality of connection terminals is connected to a corresponding one of the test terminals.

Abstract: A first output pin of a microcontroller is connected to a control pin of a high speed switch chip. A second output pin of the microcontroller is connected to two control pins of first and second switch chips. Two output pins of the high speed switch chip are connected to two input pins of the first switch chip. Two input pins of a third switch chip are connected to two output pins of the second switch chip. Two control pins of the third switch chip are connected to a third output pin of the microcontroller. Three input pins of a bus switch chip are connected to fourth to sixth output pins of the microcontroller. A load board is connected to six output pins of the bus switch chip and four switch pins of the first and second switch chips.

Abstract: A test controller performs a test of a test-target component of a test-target system so as to generate at least one fail event indicating a possible fault in the test-target component. A trouble-shooting and analysis tool probes the test controller and/or hardware of the test-target system to investigate potential causes of the fail event other than a fault of said software component. The trouble-shooting and analysis tool then analyzes fail data including probe data to evaluate potential causes of the fail event.

Abstract: A bend test method includes bending a flip chip device into a bent configuration, heating the flip chip device, and inspecting the flip chip device for failure. The bend test method is completed in a relatively short amount of time, e.g., within one to three days. Thus, appropriate failure modes in flip chip devices are created in an accelerated manner so that reliability assessment of various flip chip device designs, materials, and process options can be completed in a few days instead of a few months. This greatly reduced development cycle time typically results in a larger market share for new flip chip device products.

Abstract: The invention generally relates to a circuit card assembly testing system for testing and troubleshooting new and failed circuit card assemblies. Specifically, circuit card assemblies that are part of a guided missile and launcher test set are tested using a board testing system (BTS), the preferred embodiment, to isolate faults or to verify final assembly. The BTS is used for testing and troubleshooting a wide variety of circuit card assemblies at the end of final assembly and upon their return as a failed item from the field. The BTS is designed to rapidly isolate faults in failed circuit card assemblies that have been returned to a maintenance facility by providing an improved means of fault isolation. The BTS is designed to aid in the production of circuit card assemblies by providing an improved means of rapidly verifying the proper operation of circuit boards after final assembly.

Abstract: A method to perform an operation check test of a phase control circuit of a clock distribution circuit is disclosed that includes shifting one of the phases of the first differential signals and the second differential signals with reference to the other of the phases; obtaining an output data signal of the differential DFF to which the first differential signals and the second differential signals are input, one of the phases being shifted by the shifting; and comparing first values of the plural output data signals with first expected data values, the first values of the plural output data signals being obtained by performing the shifting and the obtaining repeatedly until phase differences of the first differential signals and the second differential signals reach one cycle of the first differential signals and the second differential signals.

Abstract: An improved method for photon transfer curve (PTC) testing in an image sensor is described. A cost and time savings is achieved by reducing the number of frames necessary for measurements to two that are generated by illuminating a first plurality of pixel rows at a first intensity level m1, a second plurality of pixel rows at a second intensity level t2, and so forth up to an nth plurality of pixel rows illuminated at an nth intensity level mn where mn>m2>m1. The resulting image has “n” regions each with a different brightness. The highest intensity level essentially saturates the pixels in the nth region. In one example, a four row exposure and five intensity levels are employed in the illuminator sequence. An intelligent light source is pre-programmable with illumination intensity settings and is synchronized to the image sensor using HSYNC and VSYNC signals, for example.

Abstract: A microprocessor testing circuit includes a sensor selection circuit to select a sensor measuring a characteristic of a microprocessor. An offset circuit artificially drives a signal from the selected sensor out of a predetermined range to invoke a fault operation in the microprocessor.

Abstract: Methods and devices to measure voltage margins of electromechanical devices are disclosed. The voltage margins are determined based on responses to test voltages which cause the devices to change states. State changes of the devices are detected by monitoring integrated current or charge used to drive the devices with the test voltages.

Abstract: A method for detecting high impedance faults, including: receiving an input waveform from a circuit; computing a root mean square of the input waveform; fitting a regression line to the root mean squares; computing a deviation between the regression line and the root mean squares; determining whether the deviations are above a threshold; and outputting a value indicating that a fault has occurred in the circuit when the deviation is above the threshold and outputting a value indicating that a fault did not occur in the circuit when the deviation is below the threshold.

Abstract: An apparatus and a computer-implemented method performed by a computerized device, comprising: generating a collection of test data for testing one or more domains, wherein the test data is useful for post-silicon verification of hardware devices; selecting a subset of the collection of test data in accordance with a hardware device to be tested and at least one of the domains to be tested with respect to the hardware device; and indexing the subset of the collection of test data to obtain an indexed collection.

Abstract: A semiconductor device and the like that can determine the performance of a semiconductor integrated circuit with higher accuracy even when test environment fluctuates. The semiconductor device detects degradation of the semiconductor integrated circuit, including measurement unit that measures temperature and voltage, decision unit that judges whether the test is executed within an allowable test timing in the detection target circuit portion at each test operation frequency and decides a maximum test operation frequency and calculation unit that converts a maximum test operation frequency into that at a standard temperature and voltage and calculates a degradation amount. The semiconductor integrated circuit has a monitor block circuit that monitors the values for the measurement unit to measure temperature and voltage. The measurement unit has estimation unit that estimates temperature and voltage of a detection target circuit portion based on the monitored values.