Abstract: In general, according to one embodiment, a semiconductor circuit test method is disclosed. The method can generate a basic format of a test pattern and store the basic format in a test device. The basic format includes at least one parameter and a test program for testing a test target semiconductor circuit. The method can set a predetermined value for the parameter to generate the test pattern including the test program and the parameter set to the predetermined value and supply the test pattern to the test target semiconductor circuit. The method can have store the test program in a first address of a storing module in the test target semiconductor circuit and store the parameter set to the predetermined value in a second address of the storing module. In addition, the method can execute the test program stored in the first address while referring to the parameter stored in the second address.

Abstract: A cost-effective system architecture and apparatus for programmable automatic power supply testing. The system utilizes board level interface between various system testing modules and an Automatic Test Controller (ATC). The ATC receives coded test requests from the software on an industrial PC and control the various testing modules inside ATC to execute the tests. Test results were sent back to the PC and saved in a result file. A single industrial PC can control two or more ATC's and test two or more power supply units simultaneously. The ATC based test system is lower cost than the conventional Automatic Test Equipment which uses device level interface and standardized test devices.

Abstract: An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

Abstract: A device that supports an operator in checking an operation of an electronic circuit mounted on a board includes the following units. A waveform obtainment unit obtains a measured waveform as a signal waveform of a voltage or current measured by the operator bringing a probe into contact with the board. A similarity calculation unit calculates a similarity between the measured waveform and each of simulated signal waveforms which are signal waveforms of a voltage or current at respective nodes on the electronic circuit and are obtained by simulating the operation of the electronic circuit. A position determination unit determines, based on node information indicating positions of the nodes, a node position on the electronic circuit which corresponds to a simulated signal waveform having a maximum similarity. A notification unit notifies the operator of the node position determined on the electronic circuit.

Abstract: A translation and loopback test for input/output ports is described. In one example, a method includes receiving a test packet on an output of a high speed processor link, looping the test packet back to an input of the high speed processor link, and detecting the receipt of the looped back test packet to test operation of the high speed link.

Abstract: A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.

Abstract: A visual dynamic monitoring system for operating states of a protective relay system, which is applied to a computer based relay includes: collecting information of a voltage input circuit & a current input circuit and internal hardware & software of protection relay, as well as a tripping and closing circuit, to obtain real-time informations completely reflecting operating states of the protective relay system; analytically calculating the real-time information mentioned above according to the designed protection principle, forming logical relations having a time sequential characteristic among the real-time information with a result by the analytically calculating; and dynamically displaying the operating states of the protective relay system, so as to providing a supporting data for implementing an evaluation of the operating states of the protective relay system.

Abstract: Upper to lower assembly analog position sensors in a dual scanning system measure alignment offsets. A controller uses error signals from the position sensors to calculate actuator error profiles that are used in the next scan in the same direction, with different error profiles being used for forward and reverse scans. Since the alignment error profiles are repeatable for a given set of scanner conditions, the actuator controller anticipates what the error signal will be before each scanning assembly reaches a given position. An optimized error correction can be calculated based on the error profiles and actuator bandwidth without concerns regarding feedback loop speed, overshoot, and unstable control oscillations. An actuation system driven from error profiles can correct for alignment offsets by actively changing belt tensions at the offsetting drive pulleys and/or changing the position of sensor assemblies relative to the drive belt systems.

Abstract: A method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC) layout, that includes, identifying failing observation points in an IC layout, determining the failing observation points proximity geometry in the IC circuit layout, determining if a proximity criteria for the failing observation points is met, and identifying faults associated with the failing observation points that meet the proximity criteria; and including the identified faults in a fault candidate set.

Abstract: A noise suppression method for a capacitance-to-voltage converter varies a sequence of sensing signal edges during a plurality capacitance measurements to produce a number of noise responses. The sensing signal edges are varied in a repetitive rising and falling edge pattern for each sequence. Three or more such sequences can be used, and the sequence with the highest noise is eliminated and the others are averaged. The noise suppression method can be implemented during calibration and then used for a number of normal acquisitions. The noise suppression method can be applied to capacitance-to-voltage converters having monitoring and integration phases.

Abstract: Methods and devices to measure voltage margins of electromechanical devices are disclosed. The voltage margins are determined based on responses to test voltages which cause the devices to change states. State changes of the devices are detected by monitoring integrated current or charge used to drive the devices with the test voltages.

Abstract: A flex circuit may have test structures and antenna structures. The test structures may include test capacitors and transmission lines. The performance of the test structures may be measured using test equipment. Pass/fail criteria may be applied to the flex circuit based on the measured values. If the flex circuit is a failing circuit, flex circuit manufacturing settings may be adjusted. The performance of a radio-frequency (RF) cable may also be measured using the test equipment. Sample portions of the RF cable may be obtained and measured. Pass/fail criteria may be applied to the RF cable based on measured cable loss values. If the RF cable is a failing cable, RF cable manufacturing settings may be adjusted. Antenna structures associated with passing flex circuits and RF cable segments associated with passing sample RF cable segments may be incorporated into a wireless device during production device assembly.

Abstract: Electrical power system sensor devices, electrical power system monitoring methods, and electrical power system monitoring systems are disclosed according to some aspects of the description. In one aspect, an electrical power system sensor device includes sensor circuitry configured to monitor a characteristic of electrical energy which is conducted using an electrical conductor of an electrical power system, an attachment assembly configured to position the sensor circuitry with respect to the electrical conductor wherein the sensor circuitry monitors the characteristic of the electrical energy which is conducted within the electrical conductor of the electrical power system, and wherein the sensor circuitry is electrically isolated from the electrical conductor of the electrical power system.

Abstract: Embodiments provide systems, devices, methods, and machine-readable medium for automated debugging of a design under test in a verification environment as part of electronic design automation. Embodiments may automatically identify inputs that are relevant to a bug for a device under test. A failing test run may be taken and rerun several times with small changes in the inputs. If the test is passing, the mutated inputs may be important to reproduce the bug and may be marked as “suspicious”. The result of this process may be a list of suspicious inputs and a shorter and simpler test that still fails. The shorter test may be rerun and fields of the inputs recorded. New tests may be created with mutated fields. Mutated fields that result in passing tests may be considered suspicious fields. Suspicious inputs and fields may be presented to a user as part of an electronic design process.

Abstract: On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.

Abstract: A method for conducting IDDQ tests for a device having a plurality of test sites is disclosed. The method includes identifying voltage ranges for each of the plurality of test sites, closing a switch in each of a plurality of voltage drop setup circuits, and setting each of the plurality of test sites to one of a plurality of logic states. Each of the plurality of voltage drop setup circuits includes a resistor parallelly coupled to the switch. One terminal of each voltage drop setup circuit is coupled to a voltage source and the other terminal of each voltage drop setup circuit is coupled to respective tester channels of each of the plurality of test sites. After opening the switch in each of the plurality of voltage drop setup circuits, the voltage drop across the resistor in each voltage drop setup circuit is measured.

Abstract: Provided is a test apparatus for testing at least one device under test, including: a test module that includes a plurality of test sections, the plurality of test sections testing the device under test by exchanging signals with the device under test; and a plurality of test control sections that control the plurality of test sections, where the test module includes the plurality of test sections; a setting storage section that stores setting as to which of the plurality of test control sections should be associated with each of the plurality of test sections; and an interface section that is connected to the plurality of test sections, provides an access request issued from one of the plurality of test control sections and directed to the test module, to a test section associated with the test control section, and is able to set, independently for each of the plurality of test sections, which of the plurality of test control sections should control the test section.

Abstract: A magnetic field sensor includes a diagnostic circuit that allows a self-test of most of or all of, the circuitry of the magnetic field sensor, including a self-test of a magnetic field sensing element used within the magnetic field sensor. The magnetic field sensor can generate a diagnostic magnetic field to which the magnetic field sensor is responsive.

Abstract: A probe circuit is provided in an electronic device that includes a circuit which is under test and outputs a response signal corresponding to an input signal in synchronization with an operation clock. The probe circuit includes a sampling clock supplying section that outputs a sampling clock having a predetermined frequency, and a sampling section that outputs, outside the electronic device, a probe output signal of which frequency is lower than a frequency of the response signal and which corresponds to a sampling result obtained by sampling the response signal using the sampling clock. The response signal has a prescribed signal pattern repeated with a predetermined recurrence period, and the sampling clock supplying section outputs the sampling clock of which relative phase with respect to the signal pattern sequentially changes in each recurrence period.

Abstract: A method of grouping clock domains includes: separating a plurality of test clocks into a plurality of domain groups by adding to each respective one of the plurality of domain groups those test clocks that originate from a same clock source and have a unique clock divider ratio; sorting the domain groups in decreasing order of size; and creating a plurality of parts by adding the respective one of the plurality of domain groups to a first one of the plurality of parts in which already present test clocks have a different clock source, and creating a new part and adding the respective one of the plurality of domain groups to the new part when test clocks present in the respective one of the plurality of domain groups originate from a respective same clock source and have a different clock divider ratio as test clocks present in all previously-created parts.

Abstract: A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.

Abstract: A method of forming a compact model for an electrical device includes obtaining shape information for the device and obtaining nominal information for the device. The method also includes merging the shape information and the nominal information to form composite data, and fitting the compact model to the composite data.

Abstract: A method is provided for monitoring and/or analysis of electrical machines during operation. An electrical machine has at least one generator with a shaft, an exciter system and drive device that drives the shaft. In this case, a first signal, which describes a voltage across a rotor winding, and a second signal, which describes a current flowing through the rotor winding, are measured simultaneously. The two signals are supplied to an analysis unit. The signals are split into individual frequency components in the analysis unit. The impedance of the rotor winding is then determined in order to identify fault states in the electrical machine.

Abstract: A testing circuit (100) in an integrated circuit (102) indirectly measures a voltage at a node of other circuitry (104) in the integrated circuit. The testing circuit includes a transistor (120) having a control electrode (121), a first conducting electrode (122) coupled to a first pad (150), a second conducting electrode (123) coupled to a terminal of a power supply, and one or more switches (131 and 133) for selectively coupling the control electrode to one of the node and a second pad (140). A method includes determining a relationship between drain current and gate voltage of the transistor when the control electrode is coupled to the second pad. A voltage at the node is determined by relating the current through the first conducting electrode of the transistor when control electrode is coupled to the node.

Abstract: An integrated circuit die comprises an electronic circuit and one or more output ports for outputting signals from the die via an external impedance, to a load, external from the die. The output port is connected to the electronic circuit. The die is further provided with an on-die sampling oscilloscope circuit connected to the output port, for measuring a waveform of the outputted signals.

Abstract: Methods of diagnostic test pattern generation for small delay defects are based on identification and activation of long paths passing through diagnosis suspects. The long paths are determined according to some criteria such as path delay values calculated with SDF (Standard Delay Format) timing information and the number of logic gates on a path. In some embodiments of the invention, the long paths are the longest paths passing through a diagnosis suspect and reaching a corresponding failing observation point selected from the failure log, and N longest paths are identified for each of such pairs.

Abstract: A test system that provides an output signal for analysis without requiring the test hardware to be idle during a settling interval. The test system includes a preprocessor that identifies the near-DC drift that occurs in the output signal and then adjusts the output signal to remove the near-DC drift. A set of values representing the near-DC drift at each of multiple times during the acquisition of a signal for analysis may be computed and used to model a settling profile of the signal by fitting a curve to the set of values. The model of the settling profile may then be subtracted from samples representing the output signal to provide an adjusted signal for further analysis.

Abstract: Techniques and mechanisms are provided to monitor signals including critical signals at the endpoints, or leaves, of one or more signal trees in an integrated circuit device. Sensors or layers of sensors may be configured in fault detection circuitry to monitor signals and compare them to static or dynamically varying values. The fault detection circuits may include OR-gate daisy chains that output a fault detection signal to control circuitry if any signal at a particular leaf deviates from an expected signal. Fault detection circuits may also be configured to identify instances where two or more or N or more signals deviate from an expected signal. Mechanisms may also be provided to assure the reliability of fault detection circuitry itself.

Abstract: Disclosed are a testing system and method incorporating a test signal generator for generating a test signal with multiple tones uniformly distributed across a wideband having a specific bandwidth. This test signal is generated based on user-specified test signal parameter(s) (e.g., using an orthogonal frequency-division multiplexing (OFDM) spread spectrum technique) and processed (e.g., converted from digital to analog or shifted to a different wideband having the same bandwidth), as necessary, so that it is suitable for application to a specific device under test and so that the tones account for the full range of frequencies with the wideband operation of that device under test. After it is applied to the device under test, the resulting output signal is captured, processed (e.g., converted back to digital or shifted back to the initial wideband), as necessary, and analyzed in order to determine the frequency responses associated with each of the tones.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: A telemetry system for use in a combustion turbine engine (10) having a compressor (12), a combustor and a turbine (16) that includes a sensor (50, 74) in connection with a turbine blade (18) or vane (22). A telemetry transmitter circuit (210) may be affixed to the turbine blade (18) with a first connecting material (52, 152) deposited on the turbine blade (18) for routing electronic data signals from the sensor (50, 74) to the telemetry transmitter circuit (210), the electronic data signals indicative of a condition of the turbine blade (18). An induction power system for powering the telemetry transmitter circuit (210) may include a rotating data antenna (202) affixed to the turbine blade (18) with a second connecting material (140) deposited on the turbine blade (18) for routing electronic data signals from the telemetry transmitter circuit (210) to the rotating data antenna (202).

Abstract: Various exemplary embodiments relate to an integrated circuit device that includes a plurality of input/output pins, device circuitry, a first testing protocol interface connected to the device circuitry and to the plurality of input/output pins, and a second testing protocol interface connected to the device circuitry and to the same plurality of input/output pins as the first testing protocol interface. The first testing protocol interface is configured to test the device circuitry with a first testing protocol, and the second testing protocol interface is configured to test the device circuitry with a second testing protocol.

Abstract: To reduce the cost and/or space occupied by diagnostic circuitry in a module of a programmable logic controller with multiple outputs, a multiplexer connects the same diagnostic circuitry to the different outputs. The outputs are sequentially tested with the same circuitry. To limit stress on an output driver, an overload condition may be tested while the driver is off. A different source of power is applied to the output, and the results of the application are measured for shorting to ground.

Abstract: A processing system for use in an electronic device is disclosed. The processing system includes a memory unit, an application processor connected to the memory unit, and a baseband processor connected to the memory unit and the application processor. The memory unit is configured for storing information of the electronic device. The application processor is configured for handling applications of the electronic device. The baseband processor is configured for providing communication capabilities for the electronic device. The application processor includes a temperature detector configured for detecting the temperature of the application processor. When the sensed temperature of the application processor is higher than a predetermined temperature, the baseband processor is instructed by the application processor to share workload of the application processor.

Abstract: Additional circuitry is included in an input cell design structure for an integrated circuit to detect and report transitions on an input that was expected to be stable, and to store that event for later analysis. Two or more modified input cells may have their error indications daisy-chained together to minimize additional routing. The storage elements may be included in a scan chain to allow for isolation of which input had the unexpected transition.

Abstract: An integrated circuit configured to perform hybrid built in self test (BiST) of analog-to-digital converters (ADCs) is described. The integrated circuit includes an ADC. The integrated circuit also includes a BiST controller that controls the hybrid BiST. The integrated circuit further includes a ramp generator that provides a voltage ramp to the ADC. The integrated circuit also includes a first multiplexer that switches an input for the ADC between the voltage ramp and a voltage reference signal. The integrated circuit further includes feedback circuitry for the ramp generator that maintains a constant ramp slope for the ramp generator. The integrated circuit also includes an interval counter that provides a timing reference.

Abstract: A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips.

Abstract: A moving light test system allows connecting moving lights to an interface board and conveying the lights and orienting and testing the lights while they are attached to the board. The lights can be mechanically and electrically connected to the board, and once connected, can be tested in multiple ways without reconfiguring or removing the lights. The board has a connector that can be plugged in at various locations, and the board can also be handled by mechanical devices. In this way, once the light is connected to the board, it does not need to be re-handled. In addition, lights can be tested in different orientations.

Abstract: A system for generating calibration information usable for wafer inspection, the system including: (I) a displacement analysis module, configured to: (a) calculate a displacement for each target out of multiple targets selected in multiple scanned frames which are included in a scanned area of the wafer, the calculating based on a correlation of: (i) an image associated with the respective target which was obtained during a scanning of the wafer, and (ii) design data corresponding to the image; and (b) determining a displacement for each of the multiple scanned frames, the determining based on the displacements calculated for multiple targets in the respective scanned frame; and (II) a subsequent processing module, configured to generate calibration information including the displacements determined for the multiple scanned frames, and a target database that includes target image and location information of each target of a group of database targets.

Abstract: Methods, systems, and products maintain reflective maintenance records for a network. Test results are mirrored from different testing applications to a centralized testing database. The test results are associated to circuit identifiers. A work order is received that identifies trouble associated with a customer. A circuit identifier associated with the customer is retrieved and, prior to performing a test of a circuit to resolve the trouble, the centralized testing database is queried for the circuit identifier. A test result associated with the circuit identifier is retrieved and the work order is updated with the test result.

Abstract: A system and method for monitoring batteries is disclosed. There is provided a plurality of sensors each adapted to communicate with one of the batteries, and to provide information concerning a characteristic of the battery in response to application of a stimulus to the battery. A controller that communicates with the sensors is also provided. In one embodiment, the sensor includes the battery.

Abstract: Stacked IC devices (or 3D semiconductor devices) have two or more semiconductor devices stacked so they occupy less space than two or more conventionally arranged semiconductor devices. Access to test infrastructures of stacked ICs is provided, regardless of configuration, while using a reduced number of interface pins. A master test controller is provided in a base die and at least one slave test controller is provided in another die. The master test controller is coupled to a test data control (TDC) bus and is configured to broadcast test instructions, test data, and an ID of a slave test controller. The slave test controller is also coupled to the TDC bus, is configured to recognize the broadcast test instructions and test data addressed to the slave test controller, and responds to the instructions when the instructions are addressed to the slave test controller.

Abstract: A device under test (DUT) may be tested using a radio-frequency test station. The DUT may include at least one antenna, wireless communications circuitry associated with the antenna, and other peripheral components such as a camera module, a display module, and audio circuitry. The test station may include a shielded enclosure in which the DUT is placed during testing. The DUT need not be electrically wired to any test equipment. The DUT may be configured to operate in self test mode. The DUT may be configured to obtain baseline noise floor measurements while all the peripheral components are deactivated and may be configured to obtain elevated noise floor measurements while selectively activating desired subsets of the peripheral components. The difference between the elevated and baseline noise floor measurements may be computed to determine whether at least some of the peripheral components negatively impact the antenna performance by an excessive amount.

Abstract: A method and apparatus for providing clock fault detection is presented. A first clock of a plurality of clocks on a printed circuit board (PCB) is designated as a reference clock. A reference clock counter is in communication with the reference clock, counting cycles of the reference clock. A counter is provided for each other clock of the plurality of clocks, each counter counting cycles of a respective clock. The reference clock counter and each of the counters are started at a same time. When the reference clock counter reaches a maximum count value the value of each of the counters is stored and a determination is made whether the stored values are expected values.

Abstract: A device for testing an electrical component is provided, having a simulation device for generating a simulation signal, a testing device for connecting the electrical component, at least two connecting devices, and a selection device for selecting the connecting device, wherein the simulation device and the testing device can be connected in an electrically conducting manner to at least one of the connecting devices by the selection device and the individual connecting devices differ from one another in at least one electrical property. Thus, a device for testing an electrical component is provided with which in a simple manner the testing accuracy can be increased by minimizing the signal corruption due to a parasitic property of the connecting device.

Abstract: Exemplary systems, methods and computer-readable mediums can assign, from the circuit, at least two scan cells as at least two interface registers, and generate at least one bidirectional scan path between the at least two interface registers of the at least one portion of the circuit. The at least two interface registers can be disposed in neighboring positions, and the assigning can include a partitioning procedure that can iteratively merge the scan cells of the at least one portion of the circuit into a plurality of regions.

Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

Abstract: There is provided a circuit with control function including a circuit to be controlled so as to be operated only if a predetermined environment meets a specific condition and being arranged to detect, in any predetermined environment, whether or not the circuit with control function is normally operated, and a test method thereof. The circuit with control function includes a controller (microcomputer) for operating the circuit to be controlled (a heater) only if a predetermined environment (ambient temperature) detected by a sensor (a first temperature sensor) meets a specific condition (0° or below).

Abstract: A method and an arrangement are provided for identifying parameters of an induction machine when the induction machine is connected to the output phases of a voltage source inverter and the induction machine is in standstill state. The method includes providing a DC magnetization current (idc—magn) to the induction machine with the inverter, controlling the power semiconductors of the inverter to an off-state, controlling all the output phases of the inverter to the same potential to provide a zero voltage vector, measuring the stator current (isd) during the zero voltage vector, and determining parameters of the induction machine from the stator current (isd) measured during the zero voltage vector.

Abstract: A system for implementing a chip lockout protection scheme for an IC device includes an on-chip password register that stores a password externally input by a user; an on-chip security block that generates a chip unlock signal, depending on whether the externally input password matches a correct password; an on-chip false data generator; an input protection scheme configured to gate the external data inputs to functional chip circuitry upon entry of the correct password; and an output protection scheme in communication configured to steer true chip data to external outputs of the IC device upon entry of the correct password, and to steer false data generated by the false data generator to the external outputs upon entry of an incorrect password. The false generated by the false data generator is deterministic and based upon external data inputs, thereby obfuscating whether or not the correct password has been entered.