Abstract: A system for minimizing interactions with at least an input mechanism includes at least a management server communicatively coupled to at least a user endpoint device, at least one storage device, and at least one processor. The user endpoint device has at least a display, an input mechanism, and a transmitter mechanism. The storage device is configured to store data based on content displayed on the display, interactions with the input mechanism, and content available for viewing. The processor is configured to use software to process the data such that a layout configuration of content data is prepared for display. The layout configuration is derived from at least the interactions with the input mechanism and the layout configuration is designed to minimize additional user interactions with the input mechanism to select the prepared content data.

Abstract: Provided is a method for determining the urgency for repairing a diagnostic condition in a vehicle. Upon determining the repair urgency, a driver may decide to continue driving (in the case of a “low” urgency determination), or cease driving (in the case of a “high” urgency determination). The urgency status may also enable a driver to shop around for the repair (in the event of a “low” urgency status), or to seek immediate assistance (in the event of a “high” urgency status).

Abstract: A method for testing using an automated test equipment is presented. The method comprises transmitting instructions for performing an automated test from a system controller to a tester processor, wherein the instructions comprise parameters for a descriptor module. The method also comprises programming a reconfigurable circuit for implementing the descriptor module onto an instantiated FPGA block coupled to the tester processor. Further, the method comprises interpreting the parameters from the descriptor module using the reconfigurable circuit, wherein the parameters control execution of a plurality of test operations on a DUT coupled to the instantiated FPGA block. Additionally, the method comprises constructing at least one packet in accordance with the parameters, wherein each one of the at least one packet comprises a command for executing a test operation on the DUT. Finally, the method comprises performing a handshake with the DUT to route the at least one packet to the DUT.

Abstract: A method for performing tests using automated test equipment (ATE) is presented. The method comprises obtaining a protocol selection for programming a programmable tester module using a graphical user interface (GUI). It further comprises accessing a configuration file associated with a protocol from a remote computer through a network. Subsequently, it comprises configuring a programmable tester module with a communication protocol for application to at least one device under test (DUT) using the configuration file. Finally, it comprises transmitting instructions to the programmable tester module for executing a program flow, wherein the program flow comprises a sequence of tests for testing the at least one DUT, and receiving results for those tests from the programmable tester module.

Abstract: Automated test equipment (ATE) capable of performing a test of semiconductor devices is presented. The ATE comprises a computer system comprising a system controller communicatively coupled to a tester processor. The system controller is operable to transmit instructions to the processor and the processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a plurality of FPGA components communicatively coupled to the processor via a bus. Each of the FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the processor for testing one of the DUTs. Additionally, the tester processor is configured to operate in one of several functional modes, wherein the functional modes are configured to allocate functionality for generating commands and data between the processor and the FPGA components.

Abstract: Automated test equipment capable of performing a high-speed test of semiconductor devices is presented. The automated test equipment comprises a system controller for controlling a test program, wherein the system controller is coupled to a bus. The tester system further comprises a plurality of modules also coupled to the bus, where each module is operable to test a plurality of DUTs. Each of the modules comprises a tester processor coupled to the bus and a plurality of configurable blocks communicatively coupled to the tester processor. Each of the configurable blocks is operable to communicate with an associated DUT and further operable to be programmed with a communication protocol for communicating test data to and from said associated device under test.

Abstract: Testing systems and methods are operable to perform diagnostic testing of a remote electronic device under test (DUT). An exemplary embodiment establishes a communication link between a diagnostic test device and the electronic DUT, receives a plurality of diagnostic commands from the electronic DUT, each of the plurality of diagnostic commands defined by at least one device diagnostic instruction (DDI) and a corresponding DDI description; generates a diagnostics script based upon selection of at least one of the diagnostic commands, wherein the generated diagnostics script includes at least one return device diagnostic instruction (RDDI) corresponding to the selected at least one diagnostic command; and transmits the at least one RDDI from the diagnostic test device to the DUT.

Abstract: In one embodiment, provided is a protocol specific circuit for simulating a functional operational environment into which a device-under-test is placed for functional testing. The protocol specific circuit includes a protocol aware circuit constructed to receive a non-deterministic signal communicated by a device-under-test and to control a transfer of the test stimulus signal to the device-under-test in response to the a non-deterministic signal.

Abstract: For generating a destination image (a left-eye image) from an original image and a height map thereof, the height of the height map of the original image is compared with the height of the height map of the destination image, and if a pixel of the original image is higher, the pixel of the original image is copied to a pixel of the destination image. After the pixel of the original image is copied to the pixel of the destination image, the height of the pixel of the original image is decremented. The pixel of the original image is copied in the rightward direction to pixels of the destination image until the height of the pixel of the original image becomes 0 or until a height of the pixel of the destination image becomes lower than that of the pixel of the original image. The same processes are performed on each pixel of the original image, and thereby the left-eye image is generated.

Abstract: A tester on a device under test to test component circuitry of the device under test, the tester comprising: logic configured with firmware to implement test circuitry comprising: protocol generators that are configurable to generate protocols; pattern generators that are configurable to provide test patterns that are drivable according to one or more of the protocols; and a system controller to select, in response to a program input, a test pattern and a protocol with which to test the component circuitry.

Abstract: A computing system connects to a server that comprises a plurality of power supplies. The computing system sends a power on command to one or more alternating current (AC) relays which are connected to the power supplies. Each of the one or more AC relays powers on the corresponding power supply according to the power on command. The server starts if the all the power supplies are powered on. The computing system sends a power off command to each predefined AC relay to power off the power supply corresponding each predefined AC relay in sequence. An execution unit of the server tests application programs of the server when each power supply corresponding to the predefined AC relay has been powered off. A result of testing the server denotes if the server is abnormal when the power supply has been powered off.

Abstract: A system and method for checking a ground via of control chips of a printed circuit board (PCB) provides a graphical user interface (GUI) displaying a layout of the PCB. The control chip has a plurality of ground pins. The computer searches for signal path routing of each ground pin and ground vias along each signal path routing of each ground pin. If there are any ground vias having the same absolute coordinates, the computer determines that the ground vias are shared by more than one ground pin.

Abstract: The disclosure provides a voltage testing device and a method. The voltage testing method includes following steps. The computer sets initial setting parameters for an oscillograph and a signal producer. The signal producer sends an initial pulse signal to an input terminal of a memory. The computer receives initial testing parameters of an output terminal of the memory and the initial voltage value of the input terminal sent by the oscillograph, and sends a current voltage offset and a current voltage undulating value to the control unit. The computer sends a current voltage value to the signal producer. The signal producer sends a current pulse signal to the input terminal. The oscillograph obtaining voltage values of the input and output terminals, produces two voltage waves, and sends the two voltage waves and the voltage values to the computer. The computer displays the two voltage waves and the voltage values.

Abstract: A tool to aid a test engineer in creating a concurrent test plan. The tool may quickly map test system resources to specific pins to satisfy the requirements of a concurrent test. The tool may project test time when such a mapping is possible. When a mapping is not possible, the tool may inform its user, including making suggestions of additional resources that could allow the test system to perform the test or suggestions for other variations in input parameters that would allow a mapping. The tool employs an assignment process in which groups of associated pins are identified, along with associated resource requirements for each group. Groups of test system resources that collectively fulfill a higher level requirement are identified and the assignment is made by mapping resource sets to resource groups, using ordering and matching heuristics to reduce processing time.

Abstract: Three dimensional integrated circuits including semiconductive organic materials are described. In some embodiments, the three dimensional integrated circuits include one or more electronic components that include a semiconductive region formed of one or more semiconductive organic materials. The electronic components of the three dimensional integrated circuits may also include insulating regions formed from organic insulating materials, and conductive regions form from conductive materials. The three dimensional integrated circuits may be formed by an additive manufacturing process such as three dimensional printing. Apparatus and methods for producing and testing three dimensional integrated circuits are also described.

Abstract: This disclosure relates to the field of current transformers, for testing the excitation characteristic of a current transformer is disclosed. The method comprise applying alternately positive and negative DC voltages across terminals of secondary winding of a CT to be tested and acquiring a secondary current; constructing a mathematical model of the relationship between the secondary current and a root mean square (rms) equivalent voltage at rated frequency of the CT from the relationship between a magnetic flux of a secondary winding iron-core of the CT and the rms equivalent voltage; and generating an excitation characteristic curve according to the mathematical model. The method and apparatus of the embodiments may test CTs requiring lower testing voltage as well as CTs with knee-point up to tens of kV by supplying a relatively low voltage and power, which makes the embodiments widely applicable.

Abstract: The present invention discloses an algorithm integrating system and an integrating method thereof. The algorithm integrating system comprises a receiving module, an analyzing module, and a processing module. The receiving module receives at least one test algorithm. The analyzing module is connected to the receiving module and analyzes the at least one test algorithm to obtain at least one basic element from the at least one test algorithm. The processing module is connected to the analyzing module and screen out the at least one non-duplicate basic element based on the at least one basic element. Then, the processing module integrates the at least one non-duplicate basic element and generates a testing module.

Abstract: An approach is presented for testing a change (i.e., configuration change) in a configuration of a computing environment. A user identifier (ID) of a user is received from an administrative user having an administrative user ID. First configurable attributes of the user ID are determined. A temporary simulation user ID (TSID) having second configurable attributes is generated so that the values of respective first and second configurable attributes are identical. The configuration change is received. The configuration change is associated with the TSID and with no other user ID. Based on the configuration change being associated with the TSID and with no other user ID, a simulation is performed by tracking data record modifications made by the TSID and based on the configuration change. The user ID and administrative user ID are unaffected by the configuration change. After completing the simulation, the data record modifications are undone.

Abstract: Environments for testing are deployed. A library of different topology groupings is provided. An interface is presented to a user for receiving environment definitions. Elements from the library of different topology groupings are automatically provided to the user for creating a test environment according to the received environment definitions. The platform delivers fully configured instantaneous topology deployments of all flavors for product development and testing efforts. The topology deployment service platform is used to create reliable topologies of varying layers of complexity, varying machine providers, different roles, different product builds, integration with partners and varying product configurations. The ability to launch and create multiple test and development environments trivially in an automated reliable fashion allows complicated customer scenarios and configurations to be deployed.

Abstract: A lightweight radio/CD player for vehicular application is virtually “fastenerless” and includes a case and frontal interface formed of polymer based material that is molded to provide details to accept audio devices such as playback mechanisms (if desired) and radio receivers, as well as the circuit boards required for electrical control and display. The case and frontal interface are of composite structure, including an insert molded electrically conductive wire mesh screen that has been pre-formed to contour with the molding operation. The wire mesh provides EMC, RFI, BCI and ESD shielding and grounding of the circuit boards via exposed wire mesh pads and adjacent ground clips. The PCB architecture is bifurcated into a first board carrying common circuit components in a surface mount configuration suitable for high volume production, and a second board carrying application specific circuit components in a wave soldered stick mount configuration.

Abstract: A system for use in automated test equipment. In one embodiment, the system includes a configurable integrated circuit (IC) programmable to provide test patterns for use in automated test equipment. The configurable IC includes a configurable interface core that is programmable to provide functionality of one or more protocol based interfaces for a device under test (DUT) and is programmable to interface with the DUT. The system also includes a connection configurable to couple the configurable IC to the DUT.

Abstract: A super I/O module for controlling at least one I/O port of a computer system is provided. The super I/O module includes a controller, a signal detector and a selector. The controller supports functions corresponding to the I/O port. The signal detector receives an input signal from the I/O port, and detects whether the input signal has an identification code. When detecting that the input signal has the identification code, the signal detector generates a selection signal according to the identification code. The selector receives the selection signal and selectively provides the input signal to the controller or a function circuit of the computer system according to the selection signal.

Abstract: A testable integrated circuit chip (80, 100) includes a functional circuit (80) having modules (IP.i), a storage circuit (110) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller (140, 150) coupled with said storage circuit (110) and with said functional circuit modules (IP.i), said test controller (140, 150) operable to dynamically schedule and trigger the tests in those sets, whereby promoting concurrent execution of tests in said functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed.

Abstract: A built-off test (BOT) device includes a signal processing block, an output selection block and a signal control block. The signal processing block duplicates a test signal to apply a plurality of duplicated test signals to each of a plurality of devices under test (DUTs) through each of corresponding channels, and the signal processing block provides a plurality of decision signals based upon a plurality of test result signals received from each of the DUTs. The output selection block merges the decision signals as a final decision signal or sequentially outputs the decision signals as the final decision signal, in response to an output mode selection signal. The signal control block provides the test signal to the signal processing block or provides the final decision signal externally, in response to a first switching control signal.

Abstract: Embodiments of the invention provide a system and method to measure and represent the measured value of a limit in terms of another measurement, such as clock values or cycles of the system. The system can include, for example, a test and measurement instrument such as an oscilloscope. In another embodiment of the present invention, slew rate de-rated values may be automatically determined through the use of configurable lookup tables.

Abstract: A computer implemented system for testing electronic equipment where a plurality of types of systems can be tested using a single test specification.

Abstract: An embodiment of a test system is provided. The system includes an electronic device to be tested and a network connection device. The electronic device to be tested includes a central processing unit (CPU) and a first universal serial bus (USB) interface. The network connection device includes a LAN module coupled to a remote server via a LAN port, and a second USB interface. When the second USB interface of the network connection device is coupled to the first USB interface of the electronic device to be tested, the CPU of the electronic device to be tested obtains a specific program from the remote server via the LAN port and the LAN module of the network connection device according to a preboot execution environment (PXE) code from the network connection device.

Abstract: A safe operating region of a complex integrated circuit may be determined by selecting an operating point for the integrated circuit (IC) at a first voltage and first frequency. A test program is executed by a central processing unit (CPU) comprised within the IC to test a portion of the IC. Communication activity between the IC and a host system is recorded to form a data log while the test program is being executed. A crash is detected by storing and examining the data log periodically, and assuming that the test program has crashed when any one of a predetermined set of crash conditions is detected during examination of the data log. The operating point may be iteratively changed and execution of the test program repeated while continuing to check for a crash until a crash is detected.

Abstract: A device under test is divided into multiple test domains, and test conditions for each of the multiple test domains are defined separately, so that each test domain has its own test pattern, timing data, and other test conditions. Each test domain can start and stop independently, and run at different speeds. Further, triggers are used to specify how the tests executed in the different test domains interact and communicate with one another. Any test domain can generate or wait for a trigger from any other test domain. A test domain can wait for a trigger from a test domain in a CPU.

Abstract: A system and method for providing an efficient test case generator is disclosed. A test case project is established upon request from a user, via a user interface, to test an item. The test case project includes a plurality of fields and corresponding designated values to be tested. A first set of identified fields of the plurality are received, wherein the first set includes two or more fields identified by the user as having a dependent relationship with at least one another. A first relational field cluster for the first set of related fields and their values is created. A test case generation technique is performed on the first relational field cluster to compute all relevant test conditions for the first relation field cluster. Results of the computed test conditions for the first relational field cluster are displayed to the user via the user interface.

Abstract: A method and associated system are provided for testing components of a vehicle entertainment system, comprising: interconnecting, via a network, a server computer comprising media content, and a plurality of user computers comprising software and hardware via which the user can interact with the media content; loading a test agent component onto a first of the user computers; loading a first scenario file comprising a series of user entry events that emulate user entry actions via a user interface device of the first user computer; executing the user entry events of the first scenario file by the test agent to generate system events that would normally be generated by a user operating the first user computer to interact with media server; and responding to the first user computer, by the server computer, to the system events.

Abstract: Methods and apparatuses to generate test patterns for detecting faults in an integrated circuit (IC) are described. During operation, the system receives a netlist and a layout for the IC. The system then generates a set of faults associated with the netlist to model a set of defects associated with the IC. Next, the system determines a set of likelihoods of occurrence for the set of faults based at least on a portion of the layout associated with each fault in the set of faults. The system subsequently generates a set of test patterns to target the set of faults, wherein the set of test patterns are generated based at least on the set of likelihoods of occurrence associated with the set of faults.

Abstract: An automation process verifies that a test bed includes a set of devices specified by at least one script which are to be executed by the automation process on the test bed. The test bed is locked and the set of devices is allocated to the automation process. Performance data collection and logging for the set of devices is started and the at least one script is executed on the set of devices. After executing the at least one script, the set of devices is de-allocated and the test bed is unlocked. A notification is generated indicating that the at least one script has been executed.

Abstract: A serial data link measurement and simulation system for use on a test and measurement instrument presents on a display device a main menu having elements representing a measurement circuit, a simulation circuit and a transmitter. The main menu includes processing flow lines pointing from the measurement circuit to the transmitter and from the transmitter to the simulation circuit. The main menu includes a source input to the measurement circuit and one or more test points from which waveforms may be obtained. The simulation circuit includes a receiver. The measurement and simulation circuits are defined by a user, and the transmitter is common to both circuits so all aspects of the serial data link system are tied together.

Abstract: There is provided a system for testing an electronic device in a test arrangement. The test arrangement includes a data interface and a user interface that is configured to output user outputs comprising image and/or audio information. The exemplary system comprises an automation unit configured to be connected via a data connection to the data interface. The user outputs are provided as output via the data interface and can be transmitted via the data connection to the automation unit. The automation unit is configured to carry out an evaluation of the user outputs.

Abstract: Analyzing the performance of multi-threaded applications. An analysis and visualization of thread executions is performed on a graphical timeline using samples of thread execution. This allows users to understand when their application threads are executing, what they were executing, the degree of concurrency in thread execution, and the order in which work is performed in their application. The visualizations and analysis also allow users to sample thread execution contexts using a graphical user interface, as well as the generation of execution profile reports that may be filtered for a specific time range of execution and a subset of the threads running in the application.

Abstract: The present invention relates to a system and a method for creating hardware and/or software test sequences and in particular, to such a system and method in which modular building blocks are used to create, sequence and schedule a large scale testing sequence using a matrix like platform.

Abstract: An electromagnetic compatibility (EMC) testing system includes a layout information obtaining module, a script loading module, a script executing module, and a report generating module. The layout information obtaining module obtains layout information of a printed circuit board. The script loading module loads an EMC testing script which includes EMC rules. The script executing module executes the EMC testing script to determine whether the layout information of the printed circuit board complies with the EMC rules. The report generating module generates an EMC report describing whether the layout information of the printed circuit board complies with the EMC rules.

Abstract: Systems and method are provided for testing an infrastructure. The infrastructure may include one or more computers connected by a network. Moreover, each of the computers may include an agent. In one embodiment, the method includes receiving, at a controller, a test request to perform at least one of a plurality of predetermined tests, the predetermined test including one or more parameters associated with performing the predetermined test and one or more expected results from performing the predetermined test. The method further includes determining whether the predetermined test is available at one of the computers. The method also includes sending, by the controller, the predetermined test to one of the computers based on the results of the determining step, such that the agent at the computer performs the predetermined test sent by the controller. Furthermore, the method includes receiving, at the controller, one or more results of the predetermined test performed by the agent at the computer.

Abstract: Systems and methods for an optical transceiver module to perform one or more diagnostic self-tests without the assistance of a host computing system. The optical transceiver module includes at least one processor, a persistent memory and a system memory. The persistent memory, which is coupled to the at least one processor, contains microcode. The microcode is loaded from the persistent memory to the system memory and executed by the at least one processor. The executed microcode causes the optical transceiver module to perform one or more diagnostic self-tests. The diagnostic result data of the one or more diagnostic self-tests is then stored in the persistent memory and is formatted for analysis. The formatted data may then be analyzed to ascertain the response of the optical transceiver to changes in its test environment.

Abstract: There are provided a method and system for testing software for an industrial machine with continuous test values reflecting actual environmental factors, using a simulator before the software for the industrial machine is embedded into an actual industrial machine. A method for testing software for an industrial machine, the method comprising the steps of: coding a program for a diagram through which the industrial machine is driven; compiling the program into an instruction with which the industrial machine is driven; downloading the compiled program onto a simulator for implementing a programming interface provided by the industrial machine; executing the compiled program in the simulator: generating a first data for testing the compiled program: transmitting the first test data to the simulator having the downloaded program from a testing tool; and outputting a result data obtained after executing the program having the transmitted first test data and then transmitting the result data to the testing tool.

Abstract: Disclosed herein are exemplary methods, apparatus, and systems for generating test sequences that can be used to evaluate high-speed circuit pathways. The disclosed methods, apparatus, and systems can be used, for example, in a printed circuit board or integrated circuit design flow to analyze signal integrity or other electrical behavior. For example, in one exemplary embodiment, a sequence of code words to be input on a circuit channel is determined in a nonrandom manner. In this embodiment, the sequence of code words complies with a transmission code (for example, the 8b10b transmission code) and is designed to cause the output voltage of the channel to be reduced during a time period in which the channel outputs a logic high value.

Abstract: A method for testing electronic devices that are correspondingly connected to test units includes generating control signals for the electronic devices that are connected to one or more test units selected from the test units. A control unit adds ID codes corresponding to the selected test units to the control signals, and wirelessly transmits the control signals with the ID codes to all of the test units. Each of the test units compares the ID codes added to the control signals with its own stored ID code. When the ID code added to a control signal is in accordance with the ID code stored in one of the test units, the test unit controls the electronic device connected thereto to be turned on and off according to the control signal.

Abstract: The invention relates to a measuring device having at least one first assembly and at least one second assembly. The first assembly and the second assembly each comprise an intermediate frequency interface or a complex baseband interface. The intermediate frequency interfaces or baseband interfaces are designed as serial digital interfaces.

Abstract: A cold boot test system and method can control an electronic device to perform a cold boot process to test whether the electronic device is operable. The method sets time parameters for a test period of the cold boot process, drives a data communication interface of a computer to generate a period control signal according to the time parameters, and sends the period control signal to a controller via the data communication interface. The method further transfers the period control signal to the electronic device by controlling a power switch to switch on and switch off, controls the electronic device to execute the cold boot process to generate test information correspondingly. In addition, the method obtains the test information from the electronic device, and displays the test information on a display screen of the computer upon the condition that the cold boot process is abnormal.

Abstract: In a method for testing device descriptions for field devices of automation technology, a finite state machine is produced from a device description to serve as a basis for a test script. For testing the device description, the test script is executed, with data being sent to and received from the device description. In such case, it is tested whether desired values set in the test script agree with actual values delivered e.g. from the field device.

Abstract: In order to shorten testing time, provided is a test apparatus that tests a device under test, comprising one or more test modules that each include a plurality of testing sections testing the device under test by exchanging signals with the device under test; and a control apparatus that controls operation of the testing sections. The control apparatus executes in parallel a plurality of test programs for testing the device under test, to control in parallel the operation of the testing sections assigned respectively to the test programs, and the testing sections test the device under test by exchanging signals in parallel with the device under test.

Abstract: In order to efficiently test a plurality of types of devices under test, provided is a test apparatus that tests a device under test, comprising one or more test modules that each include a plurality of testing sections testing the device under test by exchanging signals with the device under test; and a plurality of control apparatuses that control operation of the testing sections. In each of the one or more test modules, the plurality of testing sections are each allocated to one of the plurality of control apparatuses, and each of the control apparatuses is capable of executing a test program managed by a different user, and controls operation of the testing sections allocated thereto.

Abstract: Systems and methods provide acceleration of automatic test pattern generation in a multi-core computing environment via multi-level parameter value optimization for a parameter set with speculative scheduling. The methods described herein use multi-core based parallel runs to parallelize sequential execution, speculative software execution to explore possible parameter sets, and terminate/prune runs when the optimum parameter value is found at a previous level. The present invention evaluates the design prior to the implementation of the compression IP so that it can define the configuration of DFT and ATPG to maximize the results of compression as measured by test data volume and test application time.

Abstract: In one embodiment, a protocol aware circuit for automatic test equipment, which includes a protocol generation circuit constructed to retrieve protocol unique data and format the protocol unique data with a selected protocol definition corresponding to a device under test for testing the device under test. The protocol generation circuit may be constructed to retrieve the selected protocol definition from a protocol definition table.