Abstract: Techniques are disclosed for integrating complexity analysis with procedure authoring (design and/or documentation). By way of example, a technique for authoring a procedure associated with a computing system operation based on a complexity analysis associated with the operation and the computing system implementing the operation comprises the following steps/operations. A procedure associated with a computing system operation is generated, wherein the generated procedure represents a new procedure or an edited existing procedure. A structured representation of the generated procedure is extracted from the generated procedure. The structured representation of the generated procedure is analyzed to produce complexity analysis results, wherein at least a portion of the complexity analysis results are fed back to a procedure author for use in selectively altering the generated procedure.

Abstract: Testing systems and methods are operable to perform diagnostic testing of a remote electronic device under test (DUT). An exemplary embodiment establishes a communication link between a diagnostic test device and the electronic DUT, receives a plurality of diagnostic commands from the electronic DUT, each of the plurality of diagnostic commands defined by at least one device diagnostic instruction (DDI) and a corresponding DDI description; generates a diagnostics script based upon selection of at least one of the diagnostic commands, wherein the generated diagnostics script includes at least one return device diagnostic instruction (RDDI) corresponding to the selected at least one diagnostic command; and transmits the at least one RDDI from the diagnostic test device to the DUT.

Abstract: In an embodiment, a test method is implemented to test an integrated circuit that includes at least one processor. The method may include programming a memory to which the integrated circuit is coupled during testing with one or more test programs. The integrated circuit may be booted, and the processor may execute the test programs from the memory. In one embodiment, the memory may also store a control program that may manage the execution of the tests. In an embodiment, the control program may also implement a protocol to communicate with the ATE to perform the testing. The protocol may be implemented over a set of general purpose input/output (I/O) pins, for example. Using the protocol and test vectors on the ATE, the tests may be selected and executed, and test results may be reported.

Abstract: A simulator is partitioned into a functional component and a behavior prediction component and the components are executed in parallel. The execution path of the functional component is used to drive the behavior prediction component and the behavior prediction component changes the execution path of the functional component.

Abstract: A method of testing an electrical circuit includes applying test vectors to a circuit, detecting thermal changes in portions of the circuit during application of the test vectors, and identifying unexpected activity corresponding to the thermal changes. The method supplements standard testing techniques to provide a new method of assessing operation of fabricated integrated circuits and programmed field programmable gate arrays.

Abstract: Test equipment includes a memory to which a test plan that includes a plurality of sub-test plans is loaded and a system controller that, when the test equipment actually examines a device-under-test (DUT), loads the test plan to the memory by the unit of the sub-test plan and supplies a test signal to the DUT by interpreting the loaded test plan.

Abstract: A method for optimizing the performance of a media acceleration engine which includes providing input data to a replica of a media acceleration engine wherein the input data including a complete set of media streams, processing the input data via the replica of the media acceleration engine to provide replica output data, providing a subset of the complete set of media streams to a design of the media acceleration engine, simulating the operation of the design of the media acceleration engine using the subset of the complete set of media streams to provide design output data, comparing the replica output data with respective design output data, and comparing the performance of the media acceleration engine when replica output data matches corresponding design output data, is disclosed.

Abstract: A system and method for enhanced diagnostic fault detection and isolation is provided, wherein COTS/MOTS subsystems of a system under test are evaluated in a hierarchical manner providing improved test coverage and a reduction in ambiguity group size. The enhanced diagnostic fault detection and isolation method may proceed from automatic built-in-test to initiated built-in-test and finally to manual tests. At each stage of the testing, results may be evaluated to determine which, if any, components need replacing. The diagnostic system may report the results of testing in a fault log and/or a look-up table structure. The systems and methods of the present invention are suited to testing systems that incorporate COTS or MOTS subsystem components, and for use with an interactive electronic technical manual (IETM). Further, the diagnostic system is adaptable to a variety of subsystem interface protocols.

Abstract: In one embodiment, a protocol aware circuit for automatic test equipment, which includes a protocol generation circuit constructed to retrieve protocol unique data and format the protocol unique data with a selected protocol definition corresponding to a device under test for testing the device under test. The protocol generation circuit may be constructed to retrieve the selected protocol definition from a protocol definition table.

Abstract: One embodiment of the present invention provides systems and techniques to extract assume properties from a constrained random test-bench. During operation, the system can receive a constrained random test-bench for verifying the design-under-test (DUT), wherein the constrained random test-bench includes a statement which assigns a random value to a random variable according to a constraint. Next, the system can modify the constrained random test-bench by replacing the statement with another statement which assigns a free input variable's value to the random variable. The system can also add a statement to the constrained random test-bench that toggles a marker variable to localize the scope of the statement. The system can then generate an assume property which models the constraint on the free input variable. The assume property can then be used by a formal property verification tool to verify the DUT.

Abstract: Embodiments of the present invention provide a method for generating write and read commands used to test hardware device models. The method is able to generate multiple write commands to a location without having to generate intervening read commands to validate the data. In addition, the method enables read commands to be generated in a different sequence from the sequence of generated write commands, having different sizes than the sizes of the write commands, and that maximize the amount of data read (verified) and minimize the amount of unnecessary reads (re-verification).

Abstract: A method of verifying a digital design is disclosed. The method comprises generating a reference model for a first digital design and creating an operational model for a second digital design, wherein the first digital design and the second digital design are intended to have a same logical function. A plurality of testcase types are then created by constraining one or more internal signals, and one or more test scripts representing the plurality of testcase types are produced. The method also includes verifying the second digital design with a testing simulation program by comparing results of the test scripts from the operational model and the reference model.

Abstract: Some demonstrative embodiments of the invention may include, for example, devices, systems and methods of performing functional verification of a hardware design. In some demonstrative embodiments, a test generator may include a transaction generator to automatically generate a plurality of manipulated transactions by manipulating one or more test case transactions resulting from a constraint-satisfaction-problem.

Abstract: An approach is provided to manage test transactors that interface with components of a hardware design. A first set of transactors is launched with the first set sending stimuli to various components that correspond to the first set of transactors. A manager receives signals when transactors of the first set have completed at which point a second set of transactors is identified that are dependent upon the first set transactors that completed. The second set of transactors is launched by the manager. The manager further facilitates transmission of data used by the various transactors. Transactors generate and provide stimuli to various components included in a hardware design, such as a System-on-a-Chip (SoC). Results from the hardware design are passed to the transactors which, in turn, pass the results back to the manager. In this manner, results from one transactor may be made available as input to another transactor.

Abstract: A semiconductor chip includes a plurality of pads; input/output circuits connected with the plurality of pads, respectively; a product data storage section configured to store a product data; and a setting section configured to set to an active state, each of the input circuits which is connected to one of the plurality of pads used for input to an internal circuit, and each of the output circuits which is connected to one of the plurality of pads used for output from the internal circuit, and set remaining input/output circuits to an inactive state, based on the product data.

Abstract: A manufacturing test and programming system (100) is presented including providing a PCB tester (108), providing an in-system programmer (102) electrically attached to the PCB tester (108), mounting a device under test (114) having a programmable device (116) attached thereon and programming the programmable device (116) with the in-system programmer (102).

Abstract: Low power design is a critical concern and metric for integrated circuits. During scan based manufacturing test, electric power dissipation becomes even more critical as the chip may not have been designed to tolerate excessive switching during scan test. Excessive electric power dissipation during scan test can result in excessive voltage variations, reduced noise margins and other signal integrity issues which could invalidate the test or may lead to premature chip failure. Power dissipation during test is minimized by selecting particular values for the unused care-bits in values of the test vectors on a probabilistic basis to minimize switching, while preserving test vector quality.

Abstract: A testing device for portable electronic devices includes a processor storing test programs corresponding to various portable electronic devices, a control module connected to the processor, and a testing apparatus connected to the control module and connecting to tested portable electronic devices. The processor directs the control module and the testing apparatus to test portable electronic devices according to predetermined test programs in a main control mode, and the control module cooperates with the testing apparatus to test portable electronic devices and directs the processor to select test programs according to the tested portable electronic device in a subsidiary control mode.

Abstract: An exemplary method includes parsing data representative of an automated test case into at least one transaction defined in accordance with a global test language, translating the transaction into at least one command specific to an automated test tool, and providing the command to the automated test tool for execution. In certain examples, the method further includes parsing the data representative of the automated test case into at least one other transaction defined in accordance with the global test language, translating the other transaction into at least one other command specific to another automated test tool, and providing other command to the other automated test tool for execution.

Abstract: A method is provided to test working condition of LED indicators on hard disk drives connected to a computer. The method calls an API function from an operating system of the computer to create a main thread, and creates a sub thread for each of the hard disk drives connected to the computer using the main thread. The method further activates an LED indicator on each of the hard disk drives by interchanging data between the hard disk drive and the computer according to the sub thread. In addition, the method determines whether the LED indicator is workable by checking a working state of the LED indicator on each of the hard disk drive drives, and generates a working condition report for the LED indicator on each of the hard disk drives by integrating the determination results.

Abstract: The invention relates to a measuring device having at least one first assembly and at least one second assembly. The first assembly and the second assembly each comprise an intermediate frequency interface or a complex baseband interface. The intermediate frequency interfaces or baseband interfaces are designed as serial digital interfaces.

Abstract: A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially through the chain between a chain input for loading values and a chain output for unloading values, and a first circuit element includes a retention element for saving values during power variations related to the IC. The method further includes: saving a value from the data sequence in the retention element; and accessing the retention element for verifying an accuracy of the saved value from the data sequence.

Abstract: A recording medium recording thereon a program for a test apparatus including test modules that test devices under test is provided. The program includes: a common function provision program which is executed on a controller for controlling the test apparatus and provides a function common to each type of the test modules; and a plug-in processing program which is executed on the controller and plugs-in an individual function provision program for providing a function appropriate for the type of each of the test modules.

Abstract: A technique for determining the timing location and/or jitter of a signal edge includes computing differences between pairs of adjacent samples of the signal edge to yield difference values. First and second statistical moments are computed directly from the difference values, and mean edge location and standard deviation are computed from the first and second moments.

Abstract: A method of processing data includes providing input data by a measurement device, converting the input data into output data provided in a unified data format, wherein the unified data format is a unique data format which is independent of individual formats of various measurement devices, wherein the unique data format is a relational data format, and the relational data format is a format in which data items are grouped to data item groups being logically linked to one another, and further processing the output data.

Abstract: Systems and methodologies are provided for load testing a server wherein user characteristics are adjusted dynamically during the testing period of the server, based upon weightings defined in a user profile. Such dynamic adjustment enables a distribution of user characteristics as a percentage of total requests, (e.g. a per iteration model). The user characteristics can include type of user activities on a web page (e.g. search, browse, check out), browser features (e.g. browser type, browser version) net work connections, various client/server hard ware/software configurations and the like.

Abstract: A system and method for online configuration of a measurement system. The user may access a computer over a network and specify a desired task, e.g., a measurement task, and receive programs and/or configuration information which are usable to configure the user's measurement system hardware (and/or software) to perform the desired task. Additionally, if the user does not have the hardware required to perform the task, the required hardware may be sent to the user, along with programs and/or configuration information. The hardware may be reconfigurable hardware, such as an FPGA or a processor/memory based device. In one embodiment, the required hardware may be pre-configured to perform the task before being sent to the user. In another embodiment, the system and method may provide a graphical program in response to receiving the user's task specification, where the graphical program may be usable by the measurement system to perform the task.

Abstract: A method for determining a loading plan for a testing system includes determining demand quotas for a plurality of devices to be processed through the testing system. Each demand quota specifies a number of required devices and an associated performance specification. A bin classification distribution for devices processed through the testing system is estimated. Each device has an associated product type. Each bin classification indicates a performance grade of the associated devices. A number of devices matching each performance specification exiting the testing system is estimated based on the bin classification distribution. A device loading plan specifying a count of devices for each of a plurality of the product types to be dispatched to the testing system to provide the estimated number of devices matching each performance specification exiting the testing system to substantially meet the demand quota associated with each performance specification is determined.

Abstract: A method for identifying potentially defective integrated circuit chips and excluding them from future testing as wafers move through a manufacturing line The method includes data-collecting steps, tagging the chips on wafers identified as potentially bad chips based on information collected as the wafer moves down the fabrication line, evaluating test cost savings by eliminating any further tests on the tagged chips preferably using a test cost database. Considering all the future tests to be preformed, the tagged chips are skipped if it is determined that the test cost saving is significant. Tagging bad chips is based on various criteria and models which are dynamically adjusted by performing the wafer final test on samples of the tagged chips and feeding-back the final test results. The dynamic adaptive adjustment method preferably includes a feedback loop or iterative process to evaluate financial tradeoffs when assessing the profit of salvaging chips against the additional test costs.

Abstract: A system for testing a banking transactions server. The system includes a storage medium storing a plurality a simulated banking transactions. The system also includes a script engine executing on a processor. The system also includes a plurality of templates useable by the script engine. The script engine tests a banking transactions server by transmitting a series of simulated banking transactions to a message queue on the banking transactions server. There is also a method including storing a plurality a simulated banking transactions in a storage medium. The method also includes executing a script engine on a processor. The method also includes testing a banking transactions server by transmitting a series of simulated banking transactions to a message queue on the banking transactions server.

Abstract: In order to easily and efficiently carry out various characteristic evaluations of optical fibers which have been laid down, a table file which is for carrying out association of optical fibers serving as measuring objects with measured data when the optical fibers have been measured, based on optical fiber management information provided in advance of undertaking a cable laying/maintenance construction, such as various types of information on the optical fibers serving as measuring objects, and information on a construction site, and the like, is created at an external terminal. An OTDR measures the optical fibers serving as measuring objects based on the table file created at the external terminal, and stores measured result data in which the measured optical fibers and measured data of the optical fibers have been associated with one another, and edited result data expressing edited contents when the table file and the measured result data have been edited.

Abstract: System and method for configuring a client system, e.g., a measurement system. First input is received from a client system over a network requesting access to a plurality of configuration diagrams comprising respective solutions to respective tasks. At least a subset of the plurality of configuration diagrams is displayed on a display device of the client system for viewing by a user. Second input is received from the client system selecting one of the displayed configuration diagrams indicating a solution for a task to be performed by the client system. The solution is provided to the client system over the network, and may include the selected configuration diagram and/or pricing information for proposed products. The configuration diagrams are stored in a configuration diagram database. The stored configuration diagrams may be pre-defined solutions for pre-defined tasks, generated in response to received user requirements, and/or received from client systems and/or vendors.

Abstract: A method for predicting local concentrations of short-lived microparticles having an unstable composition in a room simply and in a short time is provided. The method for predicting the concentration distribution of microparticles includes the steps of determining a flow field in a room, determining the age-of-air distribution in the room on the basis of the flow field in the room, and converting the age of air into the concentration of the microparticles.

Abstract: A testing circuit for a semiconductor device having a test mode in which the information about built-in memory cannot be read after conducting a test on a semiconductor device, and cutting a pad formed in a scribe area is provided. The scribe PAD and the scribe ROM are formed in the cutting area of a wafer. Upon power-up of a chip a, the power-on reset circuit transmits a reset signal to the mode register. After setting the initial resister value to “00”, a mode switch signal is input from the mode switch terminal, the scribe ROM is activated, and the test mode is set. In this process, a Manchester coded signal is provided from the scribe PAD, decoded by a clock of dividing frequency provided from the clock dividing circuit, the value of the register in the test mode in the mode register is set, and external reset is asserted or negated.

Abstract: A system for validating two-way continuity of a customer premises equipment (CPE) unit in a hybrid fiber coax (HFC) cable network. A two-way client uses a two-way query interface to acquire information indicative of the two-way operational status of a subscriber CPE units from a two-way validation server and to display the information graphically.

Abstract: A system and method is disclosed for testing emulation boards in a hardware emulation environment. In one embodiment, test files can be maintained that identify a list of test commands. Such a list can be easily changed without recompiling. In another embodiment, the list of commands can be read by a first server. The commands can be passed (e.g., sequentially) to a second server associated with one or more emulator boards. The second server can ensure that the commands are executed on the specified emulator boards for testing the emulator boards. In yet another embodiment, a user can request a series of tests to be executed. The tests can be included in a list of test names. Each test name can correspond to a list of test commands associated with the test name. Thus, a first server can read a test name, read a file of test commands associated with the test name and pass the test commands to a second server to ensure the test commands are executed.

Abstract: A graphical user interface (GUI) that configures a test for a circuit. More particularly, the circuit includes a built-in-self-test (BIST) compatible device and has a test configuration. The device has an associated value. Moreover, the circuit, the device, and the associated value are defined in a circuit definition. The GUI includes a GUI object representing the circuit, a GUI object representing the BIST compatible device, and a GUI object representing the associated value. Furthermore, at least one of the GUI objects is configured to allow a modification to the GUI object and to reconfigure the test configuration in response to the GUI object modification. Also, the GUI object is further configured to modify itself to reflect a modification of the circuit definition. More particularly, the device may be an interconnect built-in self-test (IBIST) compatible device having registers, ports and lanes of the ports.

Abstract: Various implementations of the invention provide methods and apparatuses for generating a test sequence for a driver and channel combination, wherein the driver is non-linear. In various implementations of the invention, a test sequence is generated that produces the worst or near worst error rate of the channel. With various implementations of the invention, voltage waves at the driver and impulse response waves of the channel are generated. In various implementations of the invention, the driver voltage waves and impulse response waves are simulated responses of the driver and channel to a digital signal input. With further implementations of the invention, receiver voltage waves are generated by combining the impulse response wave and the driver voltage waves. Subsequently, a test sequence is selected based upon the combined receiver voltage wave.

Abstract: Embodiments of the invention provide a method of testing/adjusting magnetic disk devices, in which the method allows the tests/adjustments to be conducted by solving problems due to the data sizes and characteristics of test/adjustment programs. After assembly of a magnetic disk device, setup of various parameters, magnetic disk defect registration, and other test/adjustment steps are executed. Execution of the test/adjustment programs does not require a special test apparatus since they are executed in the magnetic disk device to be tested. In addition, the test/adjustment programs are formed up of multiple phases, and each phase is sequentially executed. Adoption of this program structure keeps the tests/adjustments clear from restrictions due to the data sizes and characteristics of the test/adjustment programs.

Abstract: A test services provider is an object that is arranged to provide a standardized interface for calling test harness provided functionality. The test services provider is not tied to a specific test harness, and provides a standard interface such that both test harness functionality and test cases can be written without beforehand knowledge of the other. In operation, the test harness registers the test services that provides with the test service provider, and the test cases retrieve the registered test services from the test harness as needed. Accordingly, the test case does not have to query the test harness itself for the object that provides the desired test harness functionality, but rather uses a standardized interface provided by the test services provider to retrieve the desired test services.

Abstract: A test system for a circuit board , wherein the circuit board has a plurality of cores such that at least one of the plurality of cores is adapted to use a test protocol independent of a communication fabric used in the circuit board. A system-on-chip (SOC) with an embedded test protocol architecture, the SOC comprising at least one embedded core, a communication fabric that connects at least one embedded core, at least one test server; and at least one test client connected to said at least one embedded core and connected to the communication fabric.

Abstract: A method for providing data assurance includes receiving selected input data to perform data assurance thereon, and receiving selected parameters for the data assurance. Data assurance modules are provided that translate the input data and the parameters and that derive a workflow for the data assurance based on the translated input data and the parameters. The workflow is executed to provide the data assurance on the input data.

Abstract: An aspect of the present invention enables burn-in tests to reduce variations due to process spread in fabricated integrated circuits (IC). Fabricated ICs are classified into multiple categories based on performance characteristics (e.g., operational speed) indicative of the extent of process spread in the ICs. The ICs are subjected to burn-in tests, with the severity of stress parameters applied during a burn-in test being proportional to the performance characteristics. As a result, process spread exhibited by the ICs (post burn-in) is reduced.

Abstract: A circuit board diagnostic operating center (10) including a large flat panel display (18) used for displaying the test system assets (instruments 12) and the circuit card assembly (CCA) schematic diagram, a small flat panel display (20) to display ancillary information, a computer (24) that executes the system application program and provides the means to communicate with automated test equipment. The diagnostic operating center may contain industry standard programmable equipment and instrumentation, or may contain independent instrumentation, or a combination. Physical CCA signal to operating center instrumentation interconnections are accomplished via a cross-point matrix (16). A graphical user interface (GUI) in combination with diagnostic operating center software and hardware provides an interactive means to visually create and store test sequences by capturing the technician's diagnostic methodology.

Abstract: In a transaction-based verification environment for complex semiconductor devices, enhanced verification efficiency may be achieved by providing a transaction to machine code translator and an appropriate interface that enables access of the translated machine code instruction by a CPU under test. In this manner, transaction-based test environments may have a high degree of re-usability and may be used for verification on block level and system level.

Abstract: A circuit has a first memory for modifiable storage of information, the information being modifiable by an ambient parameter of the circuit, which ambient parameter acts on the first memory. The first memory includes a test memory area for storing test information. The circuit also includes a second memory for unmodifiable storage of reference information and a detection circuit. The test information and reference information is supplied to the detection circuit. The detection circuit then detects whether a modification of the originally stored test information has been brought about by an ambient parameter acting on the first memory.

Abstract: Indications of user inputs with respect to a diagnostic image displayed on a display monitor are received to identify defective locations of the display monitor. Information is collected based on the received user inputs that identify defective locations of the display monitor.

Abstract: A system and method for online configuration of a measurement system. The user may access a server over a network and specify a desired task, e.g., a measurement task, and receive programs and/or configuration information which are usable to configure the user's measurement system hardware (and/or software) to perform the desired task. Additionally, if the user does not have the hardware required to perform the task, the required hardware may be sent to the user, along with programs and/or configuration information. The hardware may be reconfigurable hardware, such as an FPGA or a processor/memory based device. In one embodiment, the required hardware may be pre-configured to perform the task before being sent to the user. In another embodiment, the system and method may provide a graphical program in response to receiving the user's task specification, where the graphical program may be usable by the measurement system to perform the task.

Abstract: A test apparatus for testing an electronic device by providing test signals to the electronic device and comparing multiple output signals with respective anticipated values is disclosed, the test apparatus including: a reference timing detecting unit for detecting that one of the output signals has changed; a setting unit for setting beforehand a minimum time from changing of the output signal to changing of another output signal; an acquisition unit for acquiring the value of the latter output signal at a timing at which the minimum time has elapsed from detection of change of the former output signal; and a determination unit for determining the electronic device to be defective in the event that the value of the latter output signal thus acquired does not match the value which the latter output signal should assume following elapsing of the minimum time.

Abstract: The test equipment includes a memory to which a test plan consisting of a plurality of sub-test plans is loaded; and a controller that loads the test plan to the memory by the unit of the sub-test plan and supplies a test signal to the DUT by interpreting the loaded test plan.