Abstract: Various exemplary embodiments relate to an integrated circuit device that includes a plurality of input/output pins, device circuitry, a first testing protocol interface connected to the device circuitry and to the plurality of input/output pins, and a second testing protocol interface connected to the device circuitry and to the same plurality of input/output pins as the first testing protocol interface. The first testing protocol interface is configured to test the device circuitry with a first testing protocol, and the second testing protocol interface is configured to test the device circuitry with a second testing protocol.

Abstract: Aspects of the invention provide for reducing power consumption during manufacturing testing of an IC. In one embodiment, aspects of the invention include a method for reducing power consumption during a manufacturing test of an integrated circuit (IC), the method including: providing a plurality of domains, each domain associated with a clock phase; grouping, based on each domain, a first plurality of scan chains into a first test group; grouping, based on each domain, a second plurality of scan chains into a second test group, wherein the grouping of the first test group and of the second test group includes determining which domains can be tested simultaneously; and performing the manufacturing test of the IC.

Abstract: A method, apparatus, and computer program product to implement integrated documentation and functional application testing are provided. An integrated test engine drives both functional application testing and documentation testing for the application. The integrated test engine uses documentation instructions, which are embedded with metadata and represent how to automate each step in the documentation and the expected results, and runs a series of tests that ensure that the application works as expected and that the documentation accurately reflects how the application works.

Abstract: A device provides a time domain reflectometry (TDR) or a vector network analyzer (VNA) test signal to a via test area provided on a printed circuit board (PCB), where the via test area includes vias and via stubs formed in the vias. The device also receives a reflected signal from each via in the via test area of the PCB, and compares the reflected signal from each via to a minimum impedance threshold. The device further provides, for display, an indication of passing for the PCB, when the reflected signals from the vias are greater than the minimum impedance threshold.

Abstract: A system and method generates a test file of a print circuit board (PCB). The system and method loads trace information of the PCB into a storage system of a test computer, searches the storage system for the trace information matching keywords received and selects traces to test from the searched results. The system and method further acquires length and test points of each selected trace, and sets test parameters of each test item. In addition, the system and method generates a test file of the PCB according to the test parameters, the length, and the test points of each selected trace.

Abstract: A preboot execution environment (PXE) test device includes a microprocessor, one or more indicators, a network interface, a power connector, and a storage device. The network interface connects the PXE test device with a computer. The power connector connects an external power source to supply a voltage to the PXE test device. The storage device stores a boot loader, an embedded operating system, and one or more programs. The microprocessor executes the boot loader and the embedded operating system to start the PXE test device. The one or more indicators indicate a power supply status and a starting status of the PXE test device. The microprocessor further executes the one or more programs to remotely boot the computer for test PXE of a network card in the computer.

Abstract: A method and system for data centric heap profiling is disclosed. In one embodiment, a method, implemented in a computing device, for data centric heap profiling includes generating a type table for data structure types in source code using a compiler of the computing device. The method also includes identifying each heap allocation site and a corresponding data structure type in the source code using the compiler. The method further includes generating a data centric view of a heap o fan application compiled from the source code based on the each heap allocation site and the corresponding data structure type using a debugger of the computing device when a snapshot of the heap is requested during an execution of the application.

Abstract: A device and a method. The device includes: (i) a processor, connected to the receiver, (ii) an interface adapted to receive a test vector and to output a test response, the test vector includes a first group of signals that include idle signals and at least one information frame and a second group of signals that include timing signals and data signals; and (iii) a receiver, connected to the interface. The receiver is adapted to receive the first group of signals and filter out the idle signals and at least one instruction frame delimiters to provide at least one instruction. The device is adapted to send the at least one instruction to at least one instruction buffer. The processor is adapted to execute at least one instruction stored in the at least one instruction buffer and to respond to the second group of signals such as to provide test responses.

Abstract: Techniques for configuring a test system that enable simple specification of a degree of concurrency in testing separate functional portions of a semiconductor device. For a test flow with multiple sub-flows; the pins accessed in connection with each sub-flow may define a flow domain. Site regions, each associated with a flow domain, may be defined. Tester sites may be associated with each of these flow domain specific site regions and independently operating resources may be assigned to these tester sites. A second portion of the defined site regions may be associated with tester sites, but resources assigned to these site regions may be accessed from multiple flow domains. Test blocks, even if not developed for concurrent execution, may be executed concurrently using resources in the flow domain specific site regions. Flexibility is provided to share resources through the use of the second portion of the site regions.

Abstract: Methods, apparatus, and computer readable media for designing a custom test system are described. Examples of the invention can relate to a method of generating test system software for a semiconductor test system. In some examples, a method can include obtaining a configuration of the semiconductor test system, the configuration including a description of a device under test (DUT) and a description of test hardware; and generating an application programming interface (API) specific to the configuration of the semiconductor test system, the API being generated based on the description of the DUT and the description of the test hardware, the API providing a programming interface between the test system software and the test hardware to facilitate testing of the DUT.

Abstract: Configuring at least one radio frequency (RF) instrument according to a plurality of RF measurement configurations for performing a plurality of tests on a device under test (DUT). A list of RF measurement configurations may be stored in a computer memory. The list of RF measurement configurations comprises a plurality of parameters for configuring operation of the at least one instrument. Information regarding the list of RF measurement configurations (e.g., a data stream) may be provided to the at least one RF instrument. The at least one RF instrument may perform the plurality of tests on the DUT, including the at least one RF instrument configuring itself according to the RF measurement configurations based on processing of the information. Configuring enables the at least one RF instrument to perform the plurality of tests on the DUT in a deterministic manner.

Abstract: There is disclosed a system and method for network test conflict checking. The method may be performed by a network testing system and may be implemented as software. The method may include receiving user selected test features and user selected hardware for a network test. When receiving user selected features, incompatible features are made unselectable by reference to a feature database. A compatibility check is performed by referring to a hardware database and a feature database. Suggestive corrective changes may be provided to a user or automatically made to the selected features and/or selected hardware. The network test is written to hardware when the compatibility test is successful.

Abstract: An automatic measuring method for measuring connecting lines includes the steps of: S1, loading setting parameters and measuring regulations corresponding to the connecting lines into an automatic measuring apparatus; S2, receiving triggering signals to start measuring; and S3, automatically controlling measuring signals according to the setting parameters to measure multiple pairs of leads of the connecting lines one by one, and then determining whether the quality of the connecting lines is in compliance with standard regulations or not. Besides, an automatic measuring apparatus corresponding to the method is provided as well. The automatic measuring method and the apparatus are suitable for meeting the requirements of product measuring in mass production due to short time and high efficiency.

Abstract: A field device interface module includes a connector, a plurality of terminals, a protocol interface module, a controller and a power supply module. The connector is configured to operably couple to a computer. The terminals are operably coupleable to a field device. The protocol interface module is coupled to the plurality of terminals and configured to generate signals in accordance with a process communication protocol. A power supply module is coupled to the plurality of terminals. The controller is coupled to the protocol interface module and to the power supply module and is configured to measure a voltage across the plurality of terminals and selectively cause the power supply module to provide power to the field device.

Abstract: A testing apparatus includes a test controller configured to output a plurality of chip selection signals for selecting chips to be tested from among a plurality of chips, a plurality of first control signals for controlling supply of a power supply voltage to the chips selected by the chip selection signals, and a plurality of second control signals for controlling receiving of test voltages output from the chips supplied with the power supply voltage, and a probe card including one or more test blocks each having a plurality of signal transmitters configured to respectively transfer the power supply voltage to the corresponding chips in response to the different first control signals and respectively apply the test voltages output from the corresponding chips to the test controller in response to the different second control signals.

Abstract: A second computing device determines whether or not a conflict occurs wherein at least two of a plurality of first computing devices set different request values to an input point to which a request value is to be set, based on the request value stored in the request value buffer. When it is determined by the second computing device that a conflict occurs wherein one of the plurality of first computing devices is about to set a request value different from a request value that is set to that input point by another first computing device, the one of the first computing devices stops setting the request value. This prevents any increase in the test pattern count due to parallel processing.

Abstract: A remote server in electronic communication with a data center for testing one or more different types of electronic devices and method automatically tests one or more electronic devices. The data center stores a plurality of test programs correspondingly designed to test different types of electronic device. The remote server download one or more specified test programs corresponding to the electronic devices from the data center according to an identification code of each electronic device. The remote server tests the electronic devices by running the corresponding test programs.

Abstract: During manufacturing, devices under test may be tested at test stations. Test cables may be used to couple the test stations to the devices under test. To ensure that cables have been assembled properly, a test system may be used to convey test data through the cables. Status indictors in the cables can be activated using the test data. The test system may include a test board for performing loop-back tests. During testing, test data may be transmitted through the cable to the test board. The test board may convert the test data from a first format such as a Universal Serial Bus format to a second format such as a Universal Asynchronous Receiver Transmitter format. Test signals that have been received by the test board may be sent back to the cable to direct the cable to activate the status indicators.

Abstract: According to some embodiments, characterization data can be loaded onto a programmable device. The characterization data can be configured to cause the programmable device to perform one or more functions if executed on the programmable device. It can then be determined whether or not loading the characterization data onto the programmable device caused the programmable device to be successfully programmed. An indication can be transmitted for receipt by an external device, the indication indicating whether or not the programmable device was successfully programmed.

Abstract: In a system in which a plurality of modules have different operational rates and a common clock controlling data delivery to the modules, the rate at which data is delivered to the system can be maximized using a return clock signal to prevent the loss of synchronization of the modules. A clocking error signal may be produced when the clock signal makes a transition to a logic state that may cause loss of synchronization between the modules.

Abstract: A method for testing a characteristic impedance of a signal path routing of a printed circuit board (PCB) controls the test device to test a characteristic impedance of the signal path routing of the PCB to get test data of the signal path routing of the PCB. The method further analyzes the test data of the signal path routing of the PCB get analysis results, generate a test report for storing the test data of each signal path routing of the PCB and the analysis results if all signal path routings of the PCB have been tested.

Abstract: A method and associated system are provided for testing components of a vehicle entertainment system, comprising: interconnecting, via a network, a server computer comprising media content, and a plurality of user computers comprising software and hardware via which the user can interact with the media content; loading a test agent component onto a first of the user computers; loading a first scenario file comprising a series of user entry events that emulate user entry actions via a user interface device of the first user computer; executing the user entry events of the first scenario file by the test agent to generate system events that would normally be generated by a user operating the first user computer to interact with media server; and responding to the first user computer, by the server computer, to the system events.

Abstract: A system and method are provided for testing a vehicle entertainment (IFE) system, comprising: functionally replicating each of a plurality of IFE components selected from the group consisting of an aircraft interface unit, a content server unit, a network distribution unit, and a seat unit with a corresponding simulator unit model that simulates functions of the respective IFE component; providing each simulator unit model on a simulator server having a processor, the simulator server connecting to an IFE network that also connects at least one of actual or simulated seat units to at least one of actual or simulated content servers; providing a test controller that controls each simulator unit model; transmitting scenario information containing operation instructions to the simulator unit model; and executing the scenario information by the simulator unit model to perform operations corresponding to the operation instructions that cause the simulator unit model to communicate over the IFE network.

Abstract: An improved method is provided for identifying a cause of a performance problem experienced by an application in a computing environment. To help a user find and isolate the problem quicker, the method proposes a unified performance analysis report that presents the most likely indicators of the source of the performance problem. The report presents performance metrics for the software services used by the application and charts the metric values over time since it is often the change in a metric that indicates a problem. Each metric chart should also include an indicator for the state of service for the application. This will help the user correlate metrics from multiple sources to the time period in which the application experienced a problem.

Abstract: System and method for configuring a client system, e.g., a measurement system. First input is received from a client system over a network requesting access to a plurality of configuration diagrams comprising respective solutions to respective tasks. At least a subset of the plurality of configuration diagrams is displayed on a display device of the client system for viewing by a user. Second input is received from the client system selecting one of the displayed configuration diagrams indicating a solution for a task to be performed by the client system. The solution is provided to the client system over the network, and may include the selected configuration diagram and/or pricing information for proposed products. The configuration diagrams are stored in a configuration diagram database. The stored configuration diagrams may be pre-defined solutions for pre-defined tasks, generated in response to received user requirements, and/or received from client systems and/or vendors.

Abstract: A testing module for generating an analog testing signal for a device under test includes a control circuit, a core circuit, and a connector. The core circuit is coupled to the control circuit, and arranged to generate the analog testing signal under control of the control circuit. The connector is coupled to the core circuit, and arranged to receive the analog testing signal generated from the core circuit and output the received analog testing signal. In addition, a testing method for generating an analog testing signal for a device under test includes: generating the analog testing signal by utilizing a testing module with a connector; and outputting the analog testing signal through the connector.

Abstract: A platform specific test for computing hardware and method using same, wherein the method supplies a plurality of test procedures, and provides a computing device to be evaluated, where the computing device comprises (M) physical objects. The method identifies, for each value of (i), an (i)th physical object disposed in the computing device. The method then determines, for each value of (i), if the plurality of test procedures comprises one or more test procedures associated with the (i)th physical object. If, for each value of (i), the plurality of test procedures comprises one or more (i)th test procedures associated with the (i)th physical object, then the method adds, as one or more (i)th test procedures, the one or more test procedures associated with the (i)th physical object to a test algorithm, and saves that test algorithm.

Abstract: An Analog/mixed signal automatic test system includes a software architecture that creates a virtual composite instruments through novel software dynamic allocation of low level resources. These virtual composite instruments provide backwards and forwards compatibility to a variety of automatic test equipment, known or available on the market. The virtual composite instruments are free from the normal constraints imposed by hardware implementations. Creation of the virtual composite instruments allows a single piece of automatic test equipment system to emulate many implementations of automatic test equipment, providing higher utilization, and therefore a lower cost test solution for device manufacturers. The test instruments are preferably object controls and are preferably instantiated and controlled by the test system server. This allows multiple users to control the tester simultaneously across, for example, the Internet.

Abstract: Configuring at least one radio frequency (RF) instrument according to a plurality of RF measurement configurations for performing a plurality of tests on a device under test (DUT). A list of RF measurement configurations may be stored in a computer memory. The list of RF measurement configurations comprises a plurality of parameters for configuring operation of the at least one instrument. Information regarding the list of RF measurement configurations (e.g., a data stream) may be provided to the at least one RF instrument. The at least one RF instrument may perform the plurality of tests on the DUT, including the at least one RF instrument configuring itself according to the RF measurement configurations based on processing of the information. Configuring enables the at least one RF instrument to perform the plurality of tests on the DUT in a deterministic manner.

Abstract: A method of testing an electronics module (11) for an underwater well installation, comprises the steps of: providing a test equipment (7) comprising a processor (8) and a Local Area Network (LAN) switch (9), such that the processor (8) may communicate with the switch (9); providing an electronics module (11) comprising a data acquisition means (12) and a second LAN switch (10), such that the data acquisition means (12) may communicate with the second switch (10); passing test data from the processor (8) to the data acquisition means (12) via the first and second LAN switches (9, 10); and monitoring the response of the electronics module (11) in response to the test data.

Abstract: A computerized wagering game system includes a gaming module comprising a processor and gaming code which is operable when executed on the processor to conduct a wagering game on which monetary value can be wagered, and a service module. The service module is operable to electronically provide service documentation to a wagering game service technician via a user interface of the computerized wagering game system.

Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

Abstract: A method of wafer-level testing of a register programmable integrated circuit may be provided. The method may comprise transforming a microcode instruction and related data from an initializing processor format into tester format data, and applying the tester format data to the integrated circuit on a wafer.

Abstract: A semiconductor integrated circuit includes a plurality of shift registers to which test patterns are supplied, a pseudorandom number generator configured to generate, based on the test patterns supplied to the shift registers, pseudorandom numbers utilized as masking information corresponding to output responses of the shift registers, a masking information inverter configured to invert, on receiving a first control signal, the masking information corresponding to the output responses of the shift registers indicated by the first control signal, and an initial value storage configured to store initial values of the pseudorandom numbers. In the semiconductor integrated circuit, the pseudorandom numbers generated by the pseudorandom number generator are, on receiving a second control signal, initialized with the initial values of the pseudorandom numbers stored in the initial value storage.

Abstract: A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially through the chain between a chain input for loading values and a chain output for unloading values, and a first circuit element includes a retention element for saving values during power variations related to the IC. The method further includes: saving a value from the data sequence in the retention element; and accessing the retention element for verifying an accuracy of the saved value from the data sequence.

Abstract: A computing system connects to a server that comprises a plurality of power supplies. The computing system sends a power on command to one or more alternating current (AC) relays which are connected to the power supplies. Each of the one or more AC relays powers on the corresponding power supply according to the power on command The server starts if the all the power supplies are powered on. The computing system sends a power off command to each predefined AC relay to power off the power supply corresponding each predefined AC relay in sequence. An execution unit of the server tests application programs of the server when each power supply corresponding to the predefined AC relay has been powered off. A result of testing the server denotes if the server is abnormal when the power supply has been powered off.

Abstract: In one embodiment, a protocol aware circuit for automatic test equipment, which includes a protocol generation circuit constructed to retrieve protocol unique data and format the protocol unique data with a selected protocol definition corresponding to a device under test for testing the device under test. The protocol generation circuit may be constructed to retrieve the selected protocol definition from a protocol definition table.

Abstract: Exemplary method, computer-accessible medium, test architecture, and system can be provided for a partial-scan test of at least one integrated circuit. For example, it is possible to obtain a plurality of test cubes using a first combinational automatic test pattern generation (ATPG) and identify at least one flip-flop of the integrated circuit using the test cubes to convert to a non-scan flip-flop and facilitate the partial-scan test to utilize the cubes without a utilization of a sequential ATPG or a second combinational ATPG.

Abstract: Methods and apparatuses are described for determining a small subset of tests that provides substantially the same coverage as the set of tests. During operation, a system (e.g., a computer system) can determine a set of tests by, for each object in a set of objects, selecting up to a pre-determined number of tests that provide test coverage for the object. Next, the system can determine a subset of tests by iteratively performing a loop, which can comprise: selecting a test in the set of tests; removing, from the set of objects, one or more objects that are covered by the selected test; and optionally removing, from the set of tests, one or more tests that do not cover any objects in the remaining set of objects. The system can terminate the loop after a termination condition is met and report the selected tests as the subset of tests.

Abstract: Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.

Abstract: Various embodiments of a system and method for performing a measurement application are described herein. The system may include a host computer having a processor, and a measurement device having a programmable hardware element. The programmable hardware element may be configured to perform a loop to acquire measurement data from a physical system. The host computer may be configured to perform another loop to read the measurement data from the programmable hardware element and use the measurement data in a measurement and control algorithm. The host computer may be further configured to perform a synchronization algorithm to keep the measurement data acquisition loop performed by the programmable hardware element synchronized with the measurement and control loop performed by the host computer.

Abstract: A method and apparatus is disclosed that guides a user through a sequence of steps that will allow the user to complete a predefined task using the flow meter. The steps include: selecting a predefined task, displaying a sequence of steps that directs the user through a process for using the Coriolis flow meter to complete the predefined task, and operating the Coriolis flow meter in response to the sequence of steps to complete the predefined task.

Abstract: A non-volatile memory device may be integrated in a chip of semiconductor material. The memory device may include circuitry for receiving a measure instruction for obtaining a numerical measure value of a selected one among a plurality of predefined memory operations of the memory device. The memory device may also include circuitry for enabling the execution of the selected memory operation in response to the measure instruction. The execution of the selected memory operation may generate a corresponding result. The memory device may further include circuitry for providing at least one time signal, different from the corresponding result, relating to the execution of each memory operation, and circuitry for determining the measure value according to the at least one time signal of the selected memory operation.

Abstract: System and method for performing a multiple tests on each of one or more units, where each of the tests requires a respective resource of a plurality of resources. A first test is performed on a unit using a first resource. During performance of the first test, a search is made for a second test, requiring a second resource, where the second resource is not currently being used. If the second test is found, the second test is performed on the unit, or a second unit, using the second resource, substantially concurrently with at least a portion of the first test being performed on the unit. Performing a test includes locking the respective resource to exclude use by other tests, including acquiring the resource, and unlocking the resource upon completion of the test, including releasing the resource for use in performing the respective test on another of the units.

Abstract: A testable integrated circuit chip (80, 100) includes a functional circuit (80) having modules (IP.i), a storage circuit (110) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller (140, 150) coupled with said storage circuit (110) and with said functional circuit modules (IP.i), said test controller (140, 150) operable to dynamically schedule and trigger the tests in those sets, whereby promoting concurrent execution of tests in said functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed.

Abstract: In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose computing device, statistical timing information relating to the integrated circuit chip and a logic circuit of the integrated circuit chip and generating, by a processor of the general purpose computing device, the set of test patterns in accordance with the statistical timing information while simultaneously selecting a set of paths on which to test the set of test patterns.

Abstract: A system for use in automated test equipment. In one embodiment, the system includes a configurable integrated circuit (IC) programmable to provide test patterns for use in automated test equipment. The configurable IC includes a configurable interface core that is programmable to provide functionality of one or more protocol based interfaces for a device under test (DUT) and is programmable to interface with the DUT. The system also includes a connection configurable to couple the configurable IC to the DUT.

Abstract: Embodiments of the present disclosure provide a method that includes producing an integrated circuit device configured to include a system on a chip (SOC) and accessing test code within the SOC during the producing. The method further includes self-testing the integrated circuit device with the test code.

Abstract: A first and second test templates are combined to a combination test template. The combination test template may be configured to execute the first and second test templates in combination, and based upon a definition. The combination test template may execute tests in sequential order, concurrently, a combination thereof or the like. The first test template may be configured to be executed by a single-core machine and may be transformed to a multi-core test template that is configured to be executed on a multi-core machine in parallel to other tests. By utilizing the disclosed subject matter, a reduction in overhead of executing the first and second test templates may be achieved; a predetermined interleaving may be performed and a user may control the manner in which the combination test template is executing the first and second test templates. Additionally, reuse of pre-silicon test templates in post-silicon stage may be achieved.

Abstract: System and method for generating information regarding the functionality of a system. Input specifying at least a portion of functionality of a system may be received, e.g., from a user via a graphical user interface (GUI), and may specify one or more components of the system at a component level. The input may specify one or more components of the system, e.g., software component(s), hardware device(s), function(s) of the system, etc. Information, e.g., help information and/or documentation, describing one or more aspects of the functionality of the system may be automatically generated based on the input. The descriptions of the aspects may include information regarding the synergistic/combinatorial interactions of the components at a system level, e.g., via calculation or derivation from data retrieved from various sources regarding the components of the system. The information may be automatically stored and/or automatically displayed in the GUI substantially in real-time.