Abstract: IDDQ testing of CMOS devices. An embodiment of a method includes applying a test pattern of inputs to a device, the device including one or more CMOS (Complementary Metal-Oxide Semiconductor) transistors, and obtaining current measurements for the device, each of the current measurements being a measurement of a current after applying an input of the test pattern to the device. A filter function is applied to the current measurements, applying the filter function including separating defect current values from the current measurements. The method further includes determining whether a defect is present in the device based at least in part on a comparison of the defect current values with a threshold value.

Abstract: Methods and apparatus are provided for managing test procedures for a hardware-in-the-loop (HIL) simulation environment. The apparatus comprises an input interface for receiving input from a user, a first processor coupled to the input interface and in operable communication with the HIL simulation environment. The first processor is configured to generate a test sequence comprising a plurality of test procedure references based on input from the user, wherein each test procedure reference corresponds to a test procedure that comprises instructions for issuing commands to, and receiving data from, the HIL simulation environment, and sequentially execute each referenced test procedure within the generated test sequence in cooperation with the HIL simulation environment, in response to a command from the user.

Abstract: A system and method for updating a compensation value of a measurement machine provides a host computer to generate an authorization code document according to an ID input by a user and encrypts the authorization code document. A client computer decrypts the authorization code document, and obtains an authorization code, the input ID, and a valid date of the authorization code. If the input ID is the same as an ID of the measurement machine, and the authorization code has not expired, the compensation of the measurement machine can be updated by the client computer using the authorization code.

Abstract: A reference point-designating section 18b designates two reference points on a measurement object. A reference curve-calculating section 18c calculates a reference curve calculated by approximating an outline of the measurement object based on the reference points. A loss-composing point-calculating section 18d calculates loss-composing points constituting a loss outline formed on the measurement object based on the reference points and the reference curve. A loss size-calculating section 18f measures loss size based on the loss-composing points. Designating two reference points enables loss size measurement, thereby reducing complex operation and improving operability.

Abstract: In one embodiment, a protocol aware circuit for automatic test equipment, which includes a protocol generation circuit constructed to retrieve protocol unique data and format the protocol unique data with a selected protocol definition corresponding to a device under test for testing the device under test. The protocol generation circuit may be constructed to retrieve the selected protocol definition from a protocol definition table.

Abstract: An exemplary system includes a High-Definition Multimedia Interface (“HDMI”) analyzer and an HDMI router-switch having one or more input ports connected to one or more HDMI source devices and output ports connected to the HDMI analyzer and one or more HDMI sink devices. The HDMI router-switch is configured to establish and disestablish HDMI connections between the HDMI source devices and the HDMI analyzer and HDMI sink devices. The system further includes a control subsystem configured to control the HDMI analyzer, the HDMI router-switch, the HDMI source devices, and the HDMI sink devices, wherein the control subsystem is configured to direct one or more of the HDMI analyzer, the HDMI router-switch, the HDMI source devices, and the HDMI sink devices to perform one or more operations to execute one or more automated HDMI test routines. Corresponding methods and systems are also disclosed.

Abstract: A computer implemented system for testing electronic equipment where a plurality of types of systems can be tested using a single test specification.

Abstract: The testing method of the present invention for testing a plurality of devices under test connected to a test module includes (a) determining combinations of devices under test that can theoretically be measured simultaneously from among the combinations of the plurality of devices under test based on at least the connection relationship between the test module and the plurality of devices under test. The testing method further includes (b) testing the plurality of devices under test by sequentially selecting the combinations of devices under test to be actually measured simultaneously from the combinations determined in (a).

Abstract: Disclosed embodiments relate to an electronic device including a processor and a machine-readable storage medium, which may include instructions for testing an electronic device, including instructions for executing an executable and instructions for signaling the executable to initiate a test on an electronic device. The machine-readable storage medium may also comprise instructions for receiving information from the executable about the test before the booting of an operating system on the electronic device and before the executable finishes executing.

Abstract: In one of many possible embodiments, an exemplary system includes a test management subsystem configured to provide a user portal to a user of a circuit provided by a service provider, the user portal including a tool enabling the user to select a signal loop for testing at least a section of the circuit, the signal loop being selected from a plurality of signal loop options. The system also includes a network management subsystem communicatively coupled to the test management subsystem, the network management subsystem being configured to receive data representative of the selection from the test management subsystem and instruct, based on the selection, a network device along the circuit to execute a loop-back mode. In certain embodiments, the selected signal loop defines a test pattern signal flow for testing a subsection of the circuit.

Abstract: An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

Abstract: A method may include receiving a first set of parameters associated with a test environment, the test environment including a test system for testing a network, receiving a test objective, conducting a first test case based on the received first set of parameters and the test objective, automatically determining, by the test system, whether the test objective has been satisfied based on a first test result associated with the first test case, and automatically adapting, by the test system, a second test case based on the first test result when it is determined that the test objective has not been satisfied.

Abstract: In an embodiment, a test method is implemented to test an integrated circuit that includes at least one processor. The method may include programming a memory to which the integrated circuit is coupled during testing with one or more test programs. The integrated circuit may be booted, and the processor may execute the test programs from the memory. In one embodiment, the memory may also store a control program that may manage the execution of the tests. In an embodiment, the control program may also implement a protocol to communicate with the ATE to perform the testing. The protocol may be implemented over a set of general purpose input/output (I/O) pins, for example. Using the protocol and test vectors on the ATE, the tests may be selected and executed, and test results may be reported.

Abstract: An automatic testing system includes an equipment group and an electronic device. The equipment group includes plural equipments. The electronic device includes an input unit, a storage unit, a controller, an output unit and an integrated transmission interface. The input unit is used for inputting an instruction. The controller is electrically connected with the input unit and the storage unit for accessing the storage unit according to the instruction, thereby controlling and activating an automatic testing process and issuing a test command. The output unit is connected with the controller. The interface has a first terminal connected with the controller and a second terminal connected with the equipment group for integrating and transmitting the test command to at least one of the equipments of the equipment group, thereby allowing the equipment to perform the automatic testing process.

Abstract: The present invention discloses an algorithm integrating system and an integrating method thereof. The algorithm integrating system comprises a receiving module, an analyzing module, and a processing module. The receiving module receives at least one test algorithm. The analyzing module is connected to the receiving module and analyzes the at least one test algorithm to obtain at least one basic element from the at least one test algorithm. The processing module is connected to the analyzing module and screen out the at least one non-duplicate basic element based on the at least one basic element. Then, the processing module integrates the at least one non-duplicate basic element and generates a testing module.

Abstract: There is disclosed a system and method for network test conflict checking. The method may be performed by a network testing system and may be implemented as software. The method may include receiving user selected test features and user selected hardware for a network test. When receiving user selected features, incompatible features are made unselectable by reference to a feature database. A compatibility check is performed by referring to a hardware database and a feature database. Suggestive corrective changes may be provided to a user or automatically made to the selected features and/or selected hardware. The network test is written to hardware when the compatibility test is successful.

Abstract: Disclosed is provided an apparatus and a method for operating a macro command and inputting a macro command, wherein the apparatus including a storing unit storing control signals received from a control device for selecting of a menu item of a host device, a creating unit creating the macro command combined with the control signals, and an executing unit reading the macro command and executing functions corresponding to the respective menu item of the host device according to a combination sequence of the control signals included in the read macro command.

Abstract: Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

Abstract: A semiconductor integrated circuit includes a self-test circuit, wherein, when a operation mode of the self-test circuit has been switched from a low-speed operation mode to a high-speed operation mode, processing is performed in the high-speed operation mode during a given time period, and the processing result is invalidated based on a control signal.

Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

Abstract: A cold boot test system and method can control an electronic device to perform a cold boot process to test whether the electronic device is operable. The method sets time parameters for a test period of the cold boot process, drives a data communication interface of a computer to generate a period control signal according to the time parameters, and sends the period control signal to a controller via the data communication interface. The method further transfers the period control signal to the electronic device by controlling a power switch to switch on and switch off, controls the electronic device to execute the cold boot process to generate test information correspondingly. In addition, the method obtains the test information from the electronic device, and displays the test information on a display screen of the computer upon the condition that the cold boot process is abnormal.

Abstract: A test circuit connected between a test target circuit and a plurality of external terminals includes N first holding circuits to hold respectively N unit patterns produced by dividing an internal signal pattern to be input to or output from the test target circuit by N, where N is a natural number of two or greater, and a control circuit to make the internal signal pattern held in the N first holding circuits be changed selectively on a unit pattern basis based on a value of an identification signal assigned to each of the unit patterns beforehand, or to make the internal signal pattern held in the N first holding circuits be output selectively on a unit pattern basis based on the values of the identification signal.

Abstract: A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect distribution extraction unit, a delay fault-layout element information extraction unit, and a weighting unit. The delay fault test quality calculation apparatus further includes a delay fault test quality calculation unit which calculates the delay fault test quality on the basis of delay design information of the semiconductor integrated circuit, detection information of the test pattern to test the semiconductor integrated circuit, execution conditions of the test, a physical defect distribution extracts the defect distribution extraction unit, and a weights adds the weighting unit.

Abstract: Detecting an anomaly is disclosed. An indication that a computer system monitoring instrument is desired to provide as output a subset of the output data that it would produce if it were to remain on throughout a relevant period with no limit being placed on its output at any point during the relevant period is received. The instrument is configured to provide as output only the desired subset.

Abstract: A computer terminal retrieves pin data related to respective pins of a plurality of Field Programmable Gate Array that are mounted on a board. The computer terminal retrieves setting data related to a connection check. Upon retrieving the pin data and the setting data, the computer terminal assigns, as data for the connection check to all the pins that can output data, unique data that is unique to each pin. The computer terminal generates input pin data and output pin data containing the unique data, stores therein the input pin data and the output pin data, and generates checking circuits that check connections between output pins and input pins. The computer terminal generates checking data based on the checking circuits.

Abstract: Systems and methods provide acceleration of automatic test pattern generation in a multi-core computing environment via multi-level parameter value optimization for a parameter set with speculative scheduling. The methods described herein use multi-core based parallel runs to parallelize sequential execution, speculative software execution to explore possible parameter sets, and terminate/prune runs when the optimum parameter value is found at a previous level. The present invention evaluates the design prior to the implementation of the compression IP so that it can define the configuration of DFT and ATPG to maximize the results of compression as measured by test data volume and test application time.

Abstract: One embodiment of the present application includes a microcontroller (30) that has an embedded memory (46), a programmable processor (32), and a test interface (34). The memory (46) is accessible through the test interface (34). In response to resetting this microcontroller (30), a counter is started and the test interface (34) is initially set to a disabled state while an initiation program is executed. The test interface (34) is changed to an enabled state—such that access to the embedded memory (46) is permitted through it—when the counter reaches a predefined value unless the microcontroller (30) executes programming code before the predefined value is reached to provide the disabled state during subsequent microcontroller (30) operation.

Abstract: Provided is a test apparatus that tests a device under test, including a pattern list storage section that stores a plurality of pattern lists that each designate, in a prescribed order, the test patterns to be output by the device under test, and a pattern list processing section that (i) sequentially outputs the test patterns by sequentially executing the pattern lists according to test results of the device under test and, (ii) when transitioning from a current pattern list to a subsequent pattern list, repeatedly outputs a prescribed idle pattern until execution of the subsequent pattern list is begun.

Abstract: A system and method for online configuration of a measurement system. The user may access a server over a network and specify a desired task, e.g., a measurement task, and receive programs and/or configuration information which are usable to configure the user's measurement system hardware (and/or software) to perform the desired task. Additionally, if the user does not have the hardware required to perform the task, the required hardware may be sent to the user, along with programs and/or configuration information. The hardware may be reconfigurable hardware, such as an FPGA or a processor/memory based device. In one embodiment, the required hardware may be pre-configured to perform the task before being sent to the user. In another embodiment, the system and method may provide a graphical program in response to receiving the user's task specification, where the graphical program may be usable by the measurement system to perform the task.

Abstract: A method for testing a dynamic random access memory (DRAM) includes copying a test program from the DRAM to a random access memory (RAM). Start and end physical addresses of the DRAM are respectively stored in first and second registers. First test data is written to the start physical address, and second test data is read from the start physical address. The method further includes determining whether the second test data is the same as the first test data. A fixed value is added to the start physical address to obtain a next start physical address if the second test data is the same as the first test data. The method further includes determining whether the next start physical address is less than the end physical address. A test success result is returned if the next start physical address is not less than the end physical address.

Abstract: A system and method for using a single test case to test each sector within multiple congruence classes is presented. A test case generator builds a test case for accessing each sector within a congruence class. Since a congruence class spans multiple congruence pages, the test case generator builds the test case over multiple congruence pages in order for the test case to test the entire congruence class. During design verification and validation, a test case executor modifies a congruence class identifier (e.g., patches a base register), which forces the test case to test a specific congruence class. By incrementing the congruence class identifier after each execution of the test case, the test case executor is able to test each congruence class in the cache using a single test case.

Abstract: A method and apparatus for data analysis according to various aspects of the present invention is configured to automatically select one or more outlier identification algorithms for identifying statistical outliers in test data for components.

Abstract: A method and system for automatically verifying the quality of multimedia rendering are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of directing a command intended for a first driver to both the first driver and a second driver in parallel as the multimedia application issues the command and in response to a condition indicative of having available data to compare, comparing a first output generated by a first processing unit associated with the first driver and a second output generated by a second processing unit associated with the second driver.

Abstract: An error assessment method for a test stimulus signal of an analog to digital converter is disclosed. The method provides random uniform-distribution test signals for an analog to digital converter (ADC), derives the piecewise linearity relationship between the input signals and the output signals of the ADC and thus develops an error assessment method for a test stimulus signal of the ADC. The method is able to reduce the computational complexity but still accurate and effective, and thereby provides correct information of the test stimulus signals for testing the ADC to improve its correctness.

Abstract: A method includes determining at least a first characteristic of a device during a first test insertion and storing the first characteristic. The device is identified during a second test insertion. The first characteristic is retrieved responsive to the identification of the device. A test program for the second insertion is configured based on the first characteristic. The configured test program is executed to test the device during the second test insertion.

Abstract: A multi-function, intelligent, distributed analysis test tool (MFDAT) suitable for performing maintenance on complex, 5 sophisticated electronic systems. MFDAT replaces ordinary test instruments such as spectrum analyzers, oscilloscopes, power meters, frequency counters and digital multimeters with modular virtual test instruments that perform the identical functions but use a single display and human interface. Setup 10 information stored internally allows automatic selection and set up the instruments for a particular test. MFDAT provides a “virtual” system to the technician whereby when a second system under test is unavailable, a previous good reading stored by MFDAT is available for comparison. MFOAT provides 15 three operating modes that allow the operator to develop, modify, or refine test procedures, use the embedded test instruments as they would use standard instruments, or to step through predefined test procedures.

Abstract: A method for monitoring a burn-in procedure of an electronic device is performed by a host computer, an external storage device, and a display device. The external storage device stores the burn-in procedure and a monitor procedure. The host computer copies the monitor procedure to the at least one electronic device and activates the monitor procedure. The monitor procedure activates the burn-in procedure for the electronic device and determines a state of the burn-in procedure. The monitor procedure then outputs a monitor result corresponding to the state of the burn-in procedure into the display device. The display device displays the monitor result.

Abstract: An electronic apparatus testing method is provided. The method includes the step of: reading a product ID of the electronic apparatus when the electronic apparatus is connected to a control apparatus; determining the device type ID from the product ID, wherein the product ID comprises basic information of the electronic apparatus, determining the script files of the functions of the electronic apparatus in the testing table according to the device type ID; obtaining the script files from a data storage and running the script files to test functions of the electronic apparatuses, sending a control instruction to the corresponding measuring device of the function to control the measuring device test the function during the process of running the script files; and displaying test results through a display of the control apparatus.

Abstract: An approach is provided to manage test transactors that interface with components of a hardware design. A first set of transactors is launched with the first set of transactors sending stimuli to various components that correspond to the first set of transactors. A manager receives signals when transactors of the first set have completed at which point a second set of transactors is identified that are dependent upon the first set transactors that completed. The second set of transactors is launched by the manager. The manager further facilitates transmission of data used by the various transactors. Transactors generate and provide stimuli to various components included in a hardware design, such as a System-on-a-Chip (SoC). Results from the hardware design are passed to the transactors which, in turn, pass the results back to the manager. In this manner, results from one transactor may be made available as input to another transactor.

Abstract: A first and second test templates are combined to a combination test template. The combination test template may be configured to execute the first and second test templates in combination, and based upon a definition. The combination test template may execute tests in sequential order, concurrently, a combination thereof or the like. The first test template may be configured to be executed by a single-core machine and may be transformed to a multi-core test template that is configured to be executed on a multi-core machine in parallel to other tests. By utilizing the disclosed subject matter, a reduction in overhead of executing the first and second test templates may be achieved; a predetermined interleaving may be performed and a user may control the manner in which the combination test template is executing the first and second test templates. Additionally, reuse of pre-silicon test templates in post-silicon stage may be achieved.

Abstract: A semiconductor integrated circuit having a test circuit for collecting test data at any time based on interaction with an external source is provided. A communication circuit receives a data frame that is transferred to a data buffer. Data portions are transferred to a test unit of a test circuit. A counter starts a count operation based on a system clock when count information is transferred. If one of the data portions indicates the transferred data is test data, and another portion indicates a data collection specification command, the test unit outputs decoded address data to interact with a circuit-under-test when the counter completes the count operation based on another portion of the frame. A data buffer is supplied with the address data to facilitate storage of the data transferred from the circuit-under-test.

Abstract: A method and apparatus is disclosed that guides a user through a sequence of steps that will allow the user to complete a predefined task using the flow meter. The steps include: selecting a predefined task, displaying a sequence of steps that directs the user through a process for using the Coriolis flow meter to complete the predefined task, and operating the Coriolis flow meter in response to the sequence of steps to complete the predefined task.

Abstract: A system installs an application by identifying a file set indicating files accessed during operation of the application. The system identifies a set of available storage areas that are accessible to a computerized device, and that are capable of storing files in the file set. The system identifies a performance metric associated with each of the storage areas in the set of available storage areas, and positions files from the file set into at least one storage area of the set of available storage areas. The files are positioned based on the performance metrics associated with the one storage area.

Abstract: A multi-function, intelligent, distributed analysis test tool (MFDAT) suitable for performing maintenance on complex, sophisticated electronic systems. MFDAT replaces ordinary test instruments such as spectrum analyzers, oscilloscopes, power meters, frequency counters and digital multimeters with modular virtual test instruments that perform the identical functions but use a single display and human interface. Setup information stored internally allows automatic selection and set up the instruments for a particular test. MFDAT provides a “virtual” system to the technician whereby when a second system under test is unavailable, a previous good reading stored by MFDAT is available for comparison. MFDAT provides three operating modes that allow the operator to develop, modify, or refine test procedures, use the embedded test instruments as they would use standard instruments, or to step through predefined test procedures.

Abstract: A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions to all the instructions. The technique is easily integrated into existing test generation systems and is applicable to both uni- and multi-processing systems.

Abstract: A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions to all the instructions. The technique is easily integrated into existing test generation systems and is applicable to both uni- and multi-processing systems.

Abstract: There is presented a system and method for characterizing an integrated circuit (IC) for comparison with a pre-defined system-level characteristic related to an aspect of IC operation, wherein a test procedure on the IC that invokes this aspect is executed, while at least one operational bottleneck is invoked to constrain operation of the IC to exhibit a system-level operation thereof related to the aspect. Data generated via the test procedure in response to the bottleneck is collected and the system-level operation exhibited thereby is compared for consistency with the pre-defined system-level characteristic.

Abstract: A system and method generates a test file of a print circuit board (PCB). The system and method loads trace information of the PCB into a storage system of a test computer, searches the storage system for the trace information matching keywords received and selects traces to test from the searched results. The system and method further acquires length and test points of each selected trace, and sets test parameters of each test item. In addition, the system and method generates a test file of the PCB according to the test parameters, the length, and the test points of each selected trace.

Abstract: System and method for carrying out a process on an integrated circuit. The method includes reading a data key including subkeys, determining a process parameter set using a parameter directory in a manner dependent on the data key read in, and setting the parameters required for the process in accordance with the process parameter set determined. The parameter directory includes rule keys each having subkeys, which are each assigned predeterminable values from a plurality of values, and at least one subkey is assigned a wildcard, and a plurality of process parameter sets each respectively assigned at least one rule key. The step of determining a parameter set includes comparing the data key read in with the rule keys stored in the parameter directory, determining the rule key(s) whose subkeys match those of the data key read in, and outputting the process parameter set(s) assigned to the rule key(s) determined.

Abstract: A diagnostic test sequence optimizer includes a diagnostic test selector that determines a group of diagnostic test procedures related to a specific symptom and vehicle type from a pool of diagnostic procedures. A failure mode analyzer then selects one or more factors that can affect resolution of a vehicle operational problem and performs a failure mode analysis to quantify a comparative utility of the individual tests, and a factor weighter assigns a weight to each of the factors. A vehicle receiver receives information regarding the history of the test subject vehicle, and a sequence optimizer places the diagnostic test procedures in an optimized sequence in accordance with the comparative utilities of the individual diagnostic procedures, user preferences and a Failure Mode and Effects Analysis compiled by the manufacturer of the vehicle.