Abstract: The invention relates to a device that is used to analyse the structure of a material. The inventive device comprises: probe elements (5) which are used to (i) emit a wave, in the material, with emission delay laws that correspond to several simultaneous deviations and (ii) receive, on the different probe elements (5), signals from the refraction of said wave by the material; detection channels, each detection channel being connected to a probe element (5), in order to collect the refraction signals and to transmit same to data processing means (4); and delay circuits that apply a delay on each detection channel according to the reception delay laws which are predetermined and which correspond to the different deviations of the wave emitted. The invention also relates to an analysis method which can be used, in particular, on said device.

Abstract: An apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. Each time value from the set of time values is uniquely associated with a detected edge transition from the input signal. The memory is coupled to the edge detector. The memory is configured to receive from the edge detector the set of time values. The memory is configured to store the set of time values. The pulse-input engine is coupled to the memory. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of the time values stored in the memory.

Abstract: An apparatus and method of determining remaining capacity in a battery, including the following steps: detecting the presence of a battery within one of a plurality of specified terminals; automatically initiating a timed pulse load test on the battery upon detection in a terminal; continuously passing current from the battery through a specified resistive load for the terminal; measuring a voltage of the battery while under the resistive load; comparing the measured voltage to a discharge voltage profile of the battery; and, computing the measured voltage as a percent of remaining battery capacity.

Abstract: A system and method for analyzing order components present in a physical signal X acquired from a physical system. Measurement information for the physical signal X may be received, where the measurement information includes information indicating a plurality of order components of the physical signal X. Time frequency plot information visually indicating order components of the physical signal X may be displayed. User input selecting one or more of the visually indicated order components may be received. A time domain signal may be created based on the one or more selected order components and may then be presented to a user on a presentation device. Presenting the time domain signal on the presentation device may enable the user to analyze the physical signal X or the physical system. Where the physical system includes one or more rotating elements, the method may enable order components of the signal to be analyzed even when no rotation speed information (e.g.

Abstract: A method of measuring the PLL lock time includes deriving the PLL frequency-settling function by demodulation and envelope extraction in the time domain. The PLL lock time can then be calculated from this function. Using this PLL lock time measurement method provides for very good frequency and time accuracy. Also, since for demodulation, the settled signal is used for multiplication, ATE synchronization is not required. Furthermore, since all the processing is done in the time domain, calculation times are reduced, making the process suitable for ATE environments.

Abstract: A method and apparatus for calibrating a data path of a digital circuit uses an even bit pseudo-random calibration pattern. A portion of the pattern is captured in a capture period and used to predict a next arriving portion of the calibration pattern. The next arriving portion of the calibration pattern is captured and then compared to the predicted pattern in a compare period, and the result of the comparison is used to relatively time data arriving in the data path to a clocking signal which clocks in the data. The time duration of the compare period may be varied to ensure that all possible bits of the calibration pattern are used in the calibration procedure.

Abstract: A method and system for determining and compensating for phase and time errors in an optical receiver. The method and system includes use of a measurement and reference signal; deriving phase and time errors; and providing compensation values to the optical receiver. The operating frequency and/or other operating parameters associated with phase and time errors are determined and recorded to allow for proper compensation to the optical receiver.

Abstract: A system for monitoring conditions relating to the status of items such as perishable food products stored in enclosed spaces has a number of sensors mounted in the spaces. Tables maintained by the system hold a description of the spaces to be monitored and the location and identity of the sensors within each space. The values detected by each sensor are periodically recorded and tested against benchmark values established for the stored items adjacent to the sensor. Values outside of the benchmark values create an alarm condition, and a set of alarm messages are displayed on a display unit. The alarm messages include suggested corrective actions. The user has the opportunity to signal to the system the corrective actions taken, and the system stores a record of these corrective actions in association with the corrective actions and the alarm condition.

Abstract: The invention relates to a method for overload-free driving of an actuator, in which an activation counter is incremented or decremented each time an activation request signal occurs, in which, depending on each occurrence of an activation request signal, a drive signal for the actuator is generated if the counter reading of the activation counter is less than or greater than a predetermined maximum or minimum counter reading, in which the counter reading is in each case decremented or incremented if the time since the last generation of a drive signal or since the deactivation of the drive signal is greater than or equal to a predetermined or predeterminable interval time or if the time since the last decrementing of the activation counter is greater than or equal to the interval time.

Abstract: An apparatus for measuring static phase error in a delay locked loop includes a first test stage and a second test stage. The first test stage receives a reference clock, a chip clock, and a control signal. In parallel with the first test stage, the second test stage receives the reference clock, the chip clock, and a complement of the control signal. Dependent on the control signal, the first test stage outputs a first test signal, and, dependent on the complement of the control signal, the second test stage outputs a second test signal. The first test signal and the second test signal are used to generate a set of static phase error measurements dependent on values of the control signal and the complement of the control signal. By averaging the set of static phase error measurements, a static phase error is measured for the delay locked loop.

Abstract: A system that allows an end user to optimize the performance of a logic analyzer quickly and easily is disclosed. A visual display allowing a user to see a data valid window and relative sample positions is provided. Direct graphical manipulation of the sample position allows for quick and accurate setting of sample positions. The present invention provides a graphical user interface generally comprised of the following components: a stable and transitioning data display; bus/signal labels; sample position time scale; an information icon; a timestamp icon; a graphical representation of suggested and selected sample position; a text display of selected sample position; and a legend. The present invention sets up the logic analyzer to correctly sample data from high speed, low margin systems. It measures data signals from the device under test relative to the user's state clock and automatically suggests the sampling position offset for each channel of the analyzer.

Abstract: A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and multiplexor pairs, selectively employable to apply an aggregate amount of time delay to a data signal. The detection circuit includes circuit elements to detect a critical reference time distance between a reference point of a data signal and at least a selected edge of a clock signal being smaller than a desired threshold. The control circuit includes circuit elements to dynamically control the aggregate amount of time delay applied by the delay circuit based at least in part on the detection of the detection circuit. In one application, m units of the data transmission error reduction circuit are correspondingly employed to reduce data transmission errors on m high speed parallel data signals of a data interface.

Abstract: The performance of a plasma processing apparatus which is disassembled, transferred, and reassembled is evaluated. The plasma processing apparatus has a plasma processing chamber having an electrode for exciting a plasma, a radiofrequency generator connected to the electrode, and an impedance matching circuit for performing the impedance matching between the plasma processing chamber and the radiofrequency generator. The performance of the apparatus is evaluated whether or not three times the first series resonant frequency of the plasma processing chamber is larger than the power frequency supplied to the plasma processing chamber.

Abstract: A system and method are described for configuring and collecting performance counter information of a computer system. The method includes providing one or more performance objects, each object containing a predetermined set of events. A user is allowed to select the entire set or a subset of events to be monitored during a collection session from the predetermined set of events contained in the performance objects. The performance counters associated with the subset of events selected are programmed to increment in response to an occurrence of a respective event. The data stored in each of the performance counters associated with the subset of events selected is periodically read during the collection session.

Abstract: An eye diagram analyzer equips each SUT data and clock signal input channel with individually variable delays in their respective paths. For a range of signal delay of n-many SUT clock cycles, the SUT clock signal delay might be set at about n/2. For each data channel there is specified a point in time relative to an instance of the delayed clock signal (data signal delay) and a voltage threshold. The specified combination (data signal delay, threshold and which channel) is a location on an eye diagram, although the trace may or may not ever go through that location. A counter counts the number of SUT clock cycles used as instances of the reference for the eye diagram, and another counter counts the number of times the specified combination of conditions was met (“hits”).

Abstract: An apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. Each time value from the set of time values is uniquely associated with a detected edge transition from the input signal. The memory is coupled to the edge detector. The memory is configured to receive from the edge detector the set of time values. The memory is configured to store the set of time values. The pulse-input engine is coupled to the memory. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of time values stored in the memory.

Abstract: Delay induced apparent amplitude desensitization in a data signal channel and its accompanying worm-like distortion in an Eye Diagram Analyzer is avoided by altering the measurement to avoid the need for any substantial delay in the path of the data channel threshold comparison signals. In a first technique, only enough delay will be inserted in the data channels to produce the relative adjustments needed to compensate for skew between the data channels, as determined by a calibration operation, and it is these de-skewed, but otherwise un-delayed, data threshold comparison signals that are, in rapid succession, clocked into the latches whose difference registers a hit at a given (time, voltage) pair. The clock path delay is then varied from a minimal value to a sufficiently large value capable of spanning a desired the number of eye diagram cycles.

Abstract: A stream of pulses related to rotation rate drives an interrupt to store first timer values of a first timer and to set a second timer to run from zero. At predetermined fixed time intervals, second timer values of the second timer are stored. The stored first timer values are sampled to determine a first rate related to the input stream. The stored second timer values are sampled to determine a second rate. The first and second rates are selectively used as a final rotation rate related to the input stream.

Abstract: Once an eye diagram measurement is begun and there is an eye diagram displayed, different on-screen measurement tools may be used singly, or in combination. Each measurement involves indicating with cursors and line segments regions of the eye diagram that are of interest, and a parameter or parameters associated with each measurement tool in use is reported in a (usually) separate area of the display. An Eye Limits measurement allows the specification of a point within an eye diagram, whereupon it finds and reports the eye diagram coordinates first encountered along horizontal and vertical lines extended from the selected point (i.e., “eye opening” size). The coordinates of the point itself are also reported. A Four Point Box measurement allows the construction on the eye diagram of a rectangle having sides parallel to the coordinate axes of the eye diagram.

Abstract: Embodiments of the invention generally provide for a computer-based notification method, apparatus and article of manufacture. In one embodiment, an alert/notification includes displaying one or more animated graphical objects in response to a user-specified event, where attributes of the animated graphical objects are user-defined.

Abstract: An intergrated circuit constructed for easy debug and emulation includes a function clock circuit and an operation circuit operating in synchronism with a function clock. A trace trigger circuit triggers trace operation upon detection of a predetermined condition within the operation circuit. A FIFO buffer receives the trace data which is exported via a trace port. The integrated circuit includes an oscillator clock circuit which may be synchronized with the function clock or a reference clock. The trace trigger circuit and the FIFO input operate on the function clock. The FIFO output and the trace port operate on the oscillator clock. Thus the trace may operate all on the function clock or be split between the function clock and the reference clock. Accordingly, the trace export can operate at a frequency independent of the operation circuit.

Abstract: An output circuit for outputting data with reduced simultaneous switching output skew includes N counts of output buffers and a comparator. The N counts of output buffers receive N counts of bit signals, respectively. At least one of the output buffers includes a delay unit for processing one of the bit signals into a delayed bit signal with an adjustable delay period in response to a delay signal, a pull-up unit electrically connected to the delay unit and a source voltage, and selectively enabled to output the delayed bit signal as a high level, and a pull-down unit electrically connected to the delay unit and a ground voltage, and selectively enabled to output the delayed bit signal as a low level. The comparator is electrically connected to the N counts of output buffers, compares the N counts of bit signals sampled at a first time spot and a second time spot, and generates the delay signal according to the comparing result.

Abstract: To report the time distribution of a succession of specified events such as occurrences of particular data elements in telecommunications equipment, the method comprises an initialization of a sampling quantity consisting of a positive integer and several successive iterations of a scheme comprising the following steps: detection of a number of events equal to the sampling quantity and metering of a sampling time taken to detect said number of events; quantization of the sampling time metered in the previous step so as to output coding data representing a quantized value of the metered sampling time; and updating of the sampling quantity as a function of parameters including the quantized value of this sampling time.

Abstract: A clock skew measuring apparatus for measuring a clock skew between a plurality of clock signals to be measured in a device under test, includes: a clock signal selecting element for receiving clock signals and outputting them by selecting one of the clock signals one by one; and a clock skew estimator for receiving a reference signal input to the device under test and the clock signals to be measured selected by the clock signal selecting element one by one and for obtaining the clock skew between the clock signals to be measured.

Abstract: A continuous automatic calibration system and apparatus using a delta-sigma modulation technique. A first time duration is set. The first time duration is a length of time in terms of clock counts for a calibration procedure. Then, a second time duration occurring during the first time duration is measured. The second time duration is a length of time in terms of clock counts that a counter is operational. A multiplying factor is determined by dividing the first time duration by the second time duration.

Abstract: A clock signal xc(t) that has been converted into a digital signal is transformed into a complex analytic signal zc(t), and an instantaneous phase &THgr; of the zc(t) is estimated. A linear phase is removed from the &THgr; to obtain a phase noise waveform &Dgr;&phgr;(t). The &Dgr;&phgr;(t) is sampled at a timing close to a zero crossing timing of the xc(t) to extract the &Dgr;&phgr;(t) sample. A root-mean-square value &sgr;t of the &Dgr;&phgr;(t) samples is obtained, and a differential waveform of the extracted &Dgr;&phgr;(t) samples is also obtained to obtain a period jitter Jp. Then a root-mean-square value &sgr;p of the Jp is obtained to calculate a correlation coefficient &rgr;tt=1−(&sgr;p2/(2&sgr;t2)). If necessary, an SNRt=&rgr;tt2/(1−&rgr;tt2) is obtained. The &rgr;tt and/or the SNRt is defined as a quality measure of a clock signal.

Abstract: A method and apparatus for removing glitches, interference or noise from a clock signal are provided by the present invention. In accordance with the invention, a glitch-ridden clock signal is monitored to determine when a transition in the glitch ridden clock signal occurs. When a transition occurs, a counter is initiated in accordance with a second high-speed clock signal. The value of this counter is compared to a compare value. The compare value is selected to approximately equal the expected period of the glitch-ridden clock signal. If the counter value equals the compare value, it is assumed that the transition was a valid transition and the transition is carried through and output as a glitch-free clock signal. However, if a transition occurs before the count value equals the counter compare value, it is assumed that the transition is invalid and no transition is carried to the glitch-free clock output.

Abstract: A method, computer program, and system for intrinsic timescale decomposition, filtering, and automated analysis of signals of arbitrary origin or timescale including receiving an input signal into a processor, determining a baseline segment and a monotonic residual segment with strictly negative minimum and strictly positive maximum wherein said segments defined on a time interval comprising the interval between two successive extrema of the input signal and wherein the input signal on that interval is the sum of the baseline and residual segments, and producing a baseline output signal and a residual output signal wherein the baseline signal is obtained from the baseline segment and the residual signal is obtained from the residual segment such that the sum of the baseline and residual signals is equal to the input signal thereby forming a decomposition of the input signal.

Abstract: A method and apparatus for characterizing frequency response of a device under test (DUT) is disclosed. A repeated base bit pattern is received, the base bit pattern including a first transition from a 0-bit to a 1-bit. Then, using bit error rate distribution, multivalue voltage along the first transition is determined. Finally, the multivalued voltages are converted into frequency domain using fast Fourier transform. The apparatus includes a processor and storage with instructions for the processor to perform these operations. Using the present inventive technique, the frequency response of the DUT can be determined using an error performance analyzer such as a BERT.

Abstract: A method for generating manipulated variables for the direct-axis and cross voltage, respectively, to represent the flux-forming current ID and torque-forming current IQ in field-oriented control of asynchronous machines, taking into account the stator voltage drop and steady-state internal voltage. The steady-state internal voltage is calculated on the basis of reference variables of the currents.

Abstract: A remote control receiving circuit for receiving a remote control signal from a transmitter includes a header interrupt generation circuit 160 that outputs a header interrupt signal S160 when detecting the header of the signal, a data interrupt generation circuit 170 that outputs a data interrupt signal S170 when the header has been detected and the predetermined data receiving is completed, and a switch 111 that selects the header interrupt signal S160 or data interrupt signal S170 in accordance with an instruction of the CPU 190. A CPU 190 has one interrupt port 191 for receiving the interrupt signal selected by the switch 111, and performs control in accordance with the received interrupt signal. Therefore, a remote control receiving system can reduces the codes, processing power, and resources of the CPU, which are used to implement the remote control signal receiving function, and reduce the cost of the entire system.

Abstract: A measurement system and method for determining a revolution rate of a rotating gear is described. Such a rotating gear can be, for example, a turbine or compressor. The described measurement system and method, for example, can perform highly accurate measurements and can be a fault tolerant system providing high reliability. In one embodiment, an apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of time values stored in the memory.

Abstract: A method and device are provided for controlling the status of an internal memory of a recorder for data carriers for compensating for differences in speed between a data processing/transmitting device and the recorder. At least in the working phase of the recorder, the time is measured, the number of issued record commands is counted, and between checks and/or after a check of the status of the internal memory, an actual status is determined after a predetermined or predeterminable time or time intervals since the last check, recording speed, amount of internal memory, and number of record commands issued.

Abstract: A method and system for performing sequence time domain reflectometry over a communication channel to determine the location of line anomalies in the communication channel is disclosed. In one embodiment, the system generates a sequence signal and transmits the sequence signal over an optical channel. The system receives one or more reflection signals over the optical channel and performs reflection signal processing on the reflection signal. In one embodiment, the optical reflection is transformed to an electrical signal and correlated with the original sequence signal to generate a correlated signal. The time between the start of the reflection signal and a subsequent point of correlation and the rate of propagation reveals a line anomaly location. In one or more embodiments sequence signal time domain reflectometry occurs during data transmission.

Abstract: A clock-synchronizing apparatus and method of devices with different clocks are disclosed. Between a first device operated with a first clock and a second device operated with a second clock faster than the first clock, an operation latency of the second device refers to the first clock, control signals that controls the second device are generated at the second clock speed according to the operation latency, and an enable interval of the control signals has a clock period of the first clock. Accordingly, since the first device and the second device can transmit and receive a data to and from each other while being operated by using their own clock, an access latency for the first device to access the second device can be reduced and a transmission band width between the two devices can be effectively used.

Abstract: A method and circuit for verifying the burst-mode operation and the frequency characterization of a self-timed sequential circuit 2 in burst mode by detecting and measuring an output 15 of the self-timed sequential circuit 2.

Abstract: A timing recovery circuit comprises a data-driven phase detector and a digital loop filter. The data-driven phase detector is operably coupled to determine at least a phase difference between an input signal and a feedback clock signal to produce a difference signal. Determining the phase difference can comprise digitally determining a timing difference between the input signal and the feedback clock signal, digitally determining a transition of the input signal to produce a transition detect signal, and digitally updating the timing difference based on the transition detect signal and the feedback clock signal. The timing difference can be digitally updated by pre-filtering the timing difference BY TAKING EVERY N TRANSITON OR AVERAGE OF EVERY N TRANSITIONS at a digital pre-filter, based on a pre-filter clock signal produced from the transition detect signal and the feedback clock signal, to produce the difference signal.

Abstract: The present invention is directed to a method for measuring unidirectional transmission properties, such as packet delay (Dnetwork), delay-time fluctuations (tjitter), and results derivable therefrom, in a telecommunications network (10), such as the Internet, an intranet, or the like. In the telecommunications network, a plurality of switching devices (12 through 22) and other devices (34, 36, 38) are interconnected via transmission lines (24). Between at least two measuring computers (26, 28), test packets are transmitted from the first measuring computer (26) via a measurement path (32) to the second measuring computer (28). The first measuring computer (26) records the departure time (t1) of the outgoing test packet. This clock time is transmitted along with the test packet. The second measuring computer (28) records the arrival time (t2) of the test packet.

Abstract: A method of storing and outputting a count for an imaging device. The method includes storing the count in a memory storage device. A continuous active signal is detected from an input, the input including continuous active signals and continuous steady-state signals. Also, a count request is receivable from a remote device. The count in the memory storage device is incremented when the continuous active signal from the input is detected. Finally, the count is outputting to the remote device.

Abstract: A method and apparatus for determining the location of an impedance mismatch in a digital communication circuit (22) generate (20) at least quasi-random data, transmit the data along the circuit (22) from a transmitting end of the circuit (22), recover (24) reflections from impedance mismatches in the circuit (22) adjacent the transmitting end of the circuit (22), correlate the reflections with the data to generate a correlation result, identify a reflection peak in the result, and multiply the propagation velocity of the data through the circuit (22) by a time delay to the reflection peak.

Abstract: A method and system for performing sequence time domain reflectometry over a communication channel to determine the location of line anomalies in the communication channel is disclosed. In one embodiment, the system generates a sequence signal and transmits the sequence signal over an optical channel. The system receives one or more reflection signals over the optical channel and performs reflection signal processing on the reflection signal. In one embodiment, the optical reflection is transformed to an electrical signal and correlated with the original sequence signal to generate a correlated signal. The time between the start of the reflection signal and a subsequent point of correlation and the rate of propagation reveals a line anomaly location. A circulator, beam splitter, or any other similar device may direct the reflection signal to the apparatus configured to perform reflection signal processing.

Abstract: An end-to-end network management package that allows a user to model and analyze a network infrastructure. A user is able to pinpoint spots on the OTDR trace and locate them in real-time on a geographical representation of the network.

Abstract: A frequency domain analysis system incorporated into time domain measurement instrument has duration and resolution controls that respectively adjust the acquisition time intervals of a waveform record in seconds and adjusts the number of digital data samples over a specified duration. The duration of the acquisition waveform may be controlled using the duration control adjustment, a sample rate adjustment and a record length adjustment. The resolution controls concurrently adjusts the sample rate and the record length of the acquisition waveform while maintaining the duration constant. A movable and variable length frequency spectrum gate is applied to the digital data samples of the acquired waveform. A window filter is applied to the digital data samples within the gated region a spectrum analysis generator generates frequency domain values over the gates waveform record.

Abstract: A fault current detection system is provided. The detection system detects a fault current generated on a conductive path supplying power to an electric device and prevents the fault current from being supplied to the electric device. In particular, the detection system contains a detector, a switch, and a controller. The detector detects a fault current generated on the conductive path and outputs a corresponding detection signal. The controller inputs the detection signal and determines predetermined characteristics of the fault current based on said detection signal. Then, the controller identifies the fault current as a first type of fault current based on the predetermined characteristics and sets a trigger current to a first trigger current value when the fault current is identified as the first type of fault current.

Abstract: An analog signal is digitized by an analog-to-digital (A/D) converter clocked by a periodically jittery clock signal. Elements of the digital data sequence (vector) output of the A/D converter are sorted into a set of smaller vectors according to clock signal jitter phase and each of the smaller vectors is then separately subjected to Fourier transform and time shift functions. The resulting vectors are then processed to produce an output vector representing the frequency spectrum of the analog signal.

Abstract: An apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. Each time value from the set of time values is uniquely associated with a detected edge transition from the input signal. The memory is coupled to the edge detector. The memory is configured to receive from the edge detector the set of time values. The memory is configured to store the set of time values. The pulse-input engine is coupled to the memory. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of time values stored in the memory.

Abstract: A circuit and a method for measuring rising or falling time of high-speed data are disclosed. The circuit includes a comparator and a storage circuit. The comparator receives the high-speed data via a first port and a reference signal via a second port, compares a level of the high-speed data with a level of the reference signal in response to an enable signal, and outputs the compared result as a signal. A reference signal generator generates the reference signal. An enable signal generator generates the enable signal. The storage circuit receives and stores the signal and measures the rising or falling time of the high-speed data.

Abstract: A built-in auto-tuning system of a motor control system provides an auto-tuning of the motor control system. The built-in tuning system generates and applies a random noise test signal to the controller. In response to the test signals, the tuning system obtains response data such as the gains and phases over a wide range of operating frequencies. Based on the received data, the tuning system generates an open-loop Bode plot of the control system. The tuning system then calculates the phase and gain margins of the control system. The calculated gain and phase margins are compared with a set of predetermined values by the tuning system to automatically adjust the compensation parameters of the motor control system for a stable operation.

Abstract: A method of measuring the PLL lock time includes deriving the PLL frequency-settling function by demodulation and envelope extraction in the time domain. The PLL lock time can then be calculated from this function. Using this PLL lock time measurement method provides for very good frequency and time accuracy. Also, since for demodulation, the settled signal is used for multiplication, ATE synchronization is not required. Furthermore, since all the processing is done in the time domain, calculation times are reduced, making the process suitable for ATE environments.

Abstract: A device for calculating a time gap between successive transitions of an incident signal includes an input stage which detects and selects transitions of an incident signal and calculates the time gap between each selected transition and an edge of a sampling clock signal. An assemblage of at least three blocks is also included. Each of the blocks includes a storage cell and a counter regulated by the sampling clock signal. In response to each selected current transition, a checking circuit or processor initializes the counter of the first block of the assemblage and stores in the cell of the first block the value of the time gap corresponding to the selected current transition. The contents of a block of the assemblage may then be transferred into a next block. The time interval between two successive selected transitions is determined based upon the counter values and the time gaps.