Abstract: A system may include a PWM (Pulse Width Modulator) configured to generate a PWM signal, a signal modifier configured to generate a modified PWM signal that includes a sampling activation signal having a different frequency than the PWM signal, fan drive circuitry configured to provide power to a fan in response to the modified PWM signal; and a sampling unit configured to sample a fan tachometer signal in response to an indication that the fan is currently powered.

Abstract: A system and method for determining signal consistency (e.g., in a video signal processing system) are disclosed. Various aspects of the present invention may, for example, include receiving a first and second signal, each of which includes respective first and second sub-signals. A receiving module may, for example, effect such receiving. The first and second signals may be synchronized according to, at least in part, aspects of their respective first sub-signals. A signal synchronization module may, for example, effect such synchronization. Relative timing between the respective second sub-signals of the first and second synchronized signals may be determined. A timing differential module may, for example, effect such a determination. Various aspects of the present invention may generate a signal indicative of signal consistency based, at least in part, on the determination of relative timing between the respective second sub-signals. An output module may, for example, effect such a signal generation.

Abstract: A method and apparatus for converting skew in a received signal to a low frequency voltage. A signal is received at a destination node from an original signal from a source node. A unity time-voltage sawtooth ramp signal is created at the destination node. The amplitude of the unity time-voltage sawtooth ramp signal is a value in voltage proportional to a pulse width value of the original signal. The unity time-voltage sawtooth ramp signal starts just before the start of the received signal. A skew time is measured from the start of the unity time-voltage sawtooth ramp signal to a threshold level on an edge of the received signal. The measured skew time is correlated to a voltage level on the unity time-voltage sawtooth ramp. The measured skew time for each edge is converted into a pulse where the voltage level of each pulse being proportional to the measured skew.

Abstract: A method and apparatus for processing anomalous trigger event conditions to provide anomalous trigger event rate measurements. The apparatus operates to identify one or more trigger events in at least one input signal IN, determine the number of events during a period of time (e.g. events per second) and provide a visual representation of this determination to a user via a display device. The visual representation may comprise an alphanumeric display, a waveform, a graphic image proximate a waveform and the like.

Abstract: An exposure apparatus includes a motion control system, the motion control system including a structure, a plurality of actuators to apply forces to the structure, respectively, and a plurality of sensors to sense motion states of the structure, respectively. The apparatus includes a pseudo-random signal generator to generate a plurality of pseudo-random signals and to apply the plurality of pseudo-random signals to the plurality of actuators, the plurality of pseudo-random signals being equal in number to a number of degrees of freedom of the motion control system, a storage unit to store a first plurality of time-series data obtained by the plurality of sensors with a second plurality of time-series data corresponding to the plurality of pseudo-random signals, and a characteristic deriving unit to derive a characteristic of the motion control system based on the first and second plurality of time-series data.

Abstract: A system and method that utilizes direct sequence spread spectrum signal (DSSS) encoding to enable testing of a live wire, wherein an original data signal is modified and then transmitted along the wire, and a reflected signal is collected and analyzed using correlation techniques to determine characteristics of the live wire, including the location of a fault.

Abstract: Memory circuits are calibrated by adjusting memory circuit output parameters based on data eye measurements. Data eye patterns of memory circuit outputs are measured by the memory controller for different settings of the memory circuit output parameters. Memory circuit output parameters can be adjusted to settings that correspond to widest average data eye widths, highest average data eye heights, or other suitable criteria.

Abstract: Systems and methods for midstream determination of varying available bandwidth for streaming content between two network entities are described. During content streaming, a client requests a server to surge the content transmission rate. One or more bandwidth measurements are taken during the surge to determine if the increased transmission rate can be adequately managed. If the increased transmission rate can be adequately managed, the client may request the server to transmit remaining content at a transmission rate that is not greater than the increased, or surged, transmission rate. In a multi-bitrate file scenario, the surge rate may be higher than the rate of the fastest useable stream. In such a case, the fastest useable stream is selected. If the increased transmission rate is not suitable for future transmission, then the rate may remain at the original transmission rate.

Abstract: A method for autocalibrating a plurality of phase-delayed clock signal edges within a reference clock period includes measuring delay spacing between the plurality of clock signal edges, calculating programmed delay spacing, calculating ideal signal edges from the programmed delay spacing and adjusting the clock signal edges to match the respective ideal signal edges. A plurality of calibrated clock signal edges is produced that are selectively available to a user.

Abstract: A method and system characterize jitter of an applied signal. The characterization includes acquiring a set of pseudo-randomly timed samples at a designated position on the signal, assigning a jitter value to each of the pseudo-randomly timed samples in the acquired set, and selecting a frequency from an array of frequencies based on a correlation of the assigned jitter values with the frequencies in the array. The periodic jitter associated with the signal is designated to have the frequency within the array of frequencies that has the highest correlation to the assigned jitter values.

Abstract: A system for determining a signal running time between a position measuring system and an evaluation unit. The system includes a position measuring system that has a graduation connected to a moving element, a scanning unit that scans the graduation, wherein scanning of the graduation generates signals representative of a position of the moving element and a transceiver means for generating serial data that is transmitted along a data line connected to the transceiver. The system further includes an evaluation unit connected to the data line, the evaluation unit having means for determining a signal running time between the position measuring system and the evaluation unit.

Abstract: A device for calculating the steady state behavior of a controller includes an amount generating unit for generating the amount of deviation of the regulator, a first threshold value calculation unit that detects whether the amount of deviation of the regulator has fallen below a first threshold value and then starts a lag time delay unit, and a second threshold value calculation unit that detects whether the amount of deviation of the regulator has fallen below a second threshold value. A signal transmission unit transmits a ready message signal when the lag time delay unit has reached a predetermined lag time and the second threshold value calculation unit has detected that the amount of deviation of the regulator has fallen below the second threshold value.

Abstract: Methods and circuits for measuring clock phase uniformity of multi-phase clock set, including by generating at least one DC phase difference signal such that the DC phase difference signal is, or the DC phase difference signals are, indicative of the phase difference between the clocks of each of multiple pairs of clocks of the clock set, and methods and circuitry for generating such DC phase difference signals. Preferably, multiplexer circuitry asserts to DC signal generation circuitry any selected one of a number of pairs of clocks of the clock set, and the DC signal generation circuitry includes logic (for generating a binary signal in response to each clock pair) and a low pass filter for generating a DC phase difference signal in response to the binary signal. Other aspects are receivers and transmitters that include circuitry for generating at least one DC phase difference signal, and systems including at least one such transmitter (or receiver) and a link (e.g.

Abstract: A semiconductor device including a first signal path for guiding an input signal from a first pad to an input terminal of a macro cell; a second signal path for guiding a clock from a second pad to a clock input terminal of the macro cell; a third signal path for guiding an output signal from a signal output terminal of the macro cell to a third pad; and a fourth signal path for receiving the clock from the first signal path and guiding the clock to a fourth pad. It is possible to eliminate wiring delay by measuring the time from when the input signal and the clock are supplied by the first and second pads until the output signal is output by the third pad, and the time from when the clock is supplied to the second path until it is output by the fourth pad.

Abstract: A method for calibrating a delay element is described herein. In some embodiments, the method may include generating a clock signal with a clock edge, generating a reference signal with a reference edge using an adjustable delay line to delay the clock signal, and delaying a selected one of the clock signal and the reference signal through an array delay line having an array delay element with an array delay. In some embodiments, the method may further include adjusting the adjustable delay line to obtain a first adjustable delay so that the clock and reference edges are aligned on one side of the array delay element, adjusting the adjustable delay line to obtain a second adjustable delay so that the clock and reference edges are aligned on the other side of the array delay element, and ascertaining a delay difference between the first and the second adjustable delays to determine a value of the array delay provided by the array delay element.

Abstract: A method generating wander noise includes predefining frequency, amplitude and phase values for each of a plurality of tones for various predefined frequency profiles. A digital noise signal having a particular profile can then be generated by a summation of a plurality of tones based on the predefined frequency, amplitude and phase values for each of the plurality of tones for the selected profile. The wander noise signal is then generated from the digital noise signal.

Abstract: A technique for implementing an extended bit timer with a time processing unit (TPU), without using the channel hardware of the TPU includes a number of steps. A timer of the TPU is periodically read to determine the value of the timer. A counter is incremented when rollover of the timer has occurred and a coherency flag is de-asserted after the timer transitions through a first count. The coherency flag is asserted after the value of the timer transitions through a third count and the value of the timer is combined with the value of the counter to provide a current count. When the coherency flag is asserted and the value of the timer is equal to or between the first and second counts, the current count is adjusted.

Abstract: The present invention provides for determining gate speed parameters in a circuit. A first delay is selected. A second delay is selected, wherein the second delay is longer than the first delay. A clock signal is delayed as a function of the first delay. The clock signal is combined with the first delayed clock signal. A first pulse signal is produced from combining the clock signal with the first delayed clock signal. A clock signal is delayed as a function of the second delay. The clock signal is combined with the first delayed clock signal. A second pulse signal is produced from combining the clock signal with the second delayed clock signal. The first delayed clock signal is integrated. The second delayed clock signal is integrated. The first delayed integrated clock signal is compared with the second delayed integrated clock signal. When the first delayed integrated clock signal is greater than the second integrated clock signal, the gate delay is determined.

Abstract: A time-series model learning unit reads in time-series data sequentially, learns the parameters of a time-series model and stores the parameters in a storage device. A loss function calculating unit reads in sequentially from storage each item of the input time-series data one at a time and calculates values of a loss function. A complexity calculating unit sums the loss values to sequentially calculate complexity as fitting error resulting when a time-series model is fit to the input data. Complexity is stored. A change-point searching unit reads in complexity regarding time-series data before and after change-point candidates from storage with respect to all change-point candidates, compares the sum of the complexities with complexity regarding all time-series data in a case where a change point is assumed to be absent, calculates the change-point score based upon the difference between the compared values, and detects and outputs the change point.

Abstract: A pulse width measuring device is disclosed that calculates the pulse width of a signal to be measured, based on a count value and a count clock signal. In the pulse width measuring device, the counter circuit has a plurality of bits that are divided into an exponent and a significand. The control unit of the pulse width measuring device includes: an exponent storing unit that stores an exponent setting value that represents the number of bits of the exponent of the counter circuit; and a decoder unit that generates a count value setting signal for rewriting the count value of the counter circuit, based on the exponent setting value stored in the exponent storing unit, when the count value overflows in the counter circuit, the decoder unit then outputting the count value setting signal to the counter circuit.

Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed in one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

Abstract: A method for monitoring the performance of a test apparatus (1) for testing a batch of integrated circuits. The apparatus 1 comprises a test site 2 in which the integrated circuits are sequentially tested, and a microprocessor (4) for carrying out the appropriate tests on the integrated circuits. A first ROM (5) stores a computer programme for controlling the operation of the microprocessor (4) for carrying out the tests, and a first RAM (10) stores a computer programme for controlling the operation of the microprocessor (4) for monitoring the performance of the test apparatus (1). In particular, the computer programme stored in the first RAM (10) operates the microprocessor (4) for computing the test time period for each integrated circuit tested, and also for computing the intervening time periods between each integrated circuit tested. The intervening time periods between the respective test time periods are classified as either first or second category delays or index time periods.

Abstract: In one representative embodiment, multiple ensembles of samples of a periodic or cylcostationary signal are processed in a time aligned manner. The sampling rate of the processing system is adjusted so that an integer number of sampling intervals equals the period of the signal. A cyclic counter is programmed to reset according to the integer number. Also, the cyclic counter may be initialized according to an external trigger. During operation, the cyclic counter is incremented when each sample is received. Continuous operation of the cyclic counter with the capturing of samples enables precise time alignment between ensembles of samples. Specifically, the beginning of a discrete ensemble is identified by a reset of the cyclic counter. Because each ensemble is time aligned, further processing (e.g., coherent averaging) may occur without post-processing to time-shift each sample to achieve the time alignment.

Abstract: A method includes steps of: (a) receiving as input a waveform of a transient signal as a function of time for an aggressor net; (b) finding a peak value of the waveform and a corresponding peak time of the waveform propagated from the aggressor net to a victim net; (c) defining a selected time interval within the waveform at the victim net that includes the peak value and excludes features of the waveform not associated with the peak value wherein the selected time interval begins at a first time and ends at a second time; (d) calculating a weighted value of a function of the waveform at the first time and the second time; (e) calculating a local average value of the waveform as a function of the peak value and the weighted value; and (f) generating as output the local average value of the waveform.

Abstract: A system and method for testing the jitter tolerance and signal attenuation tolerance of an optoelectronic device is disclosed. The system includes a generation circuit, delay circuit and comparison circuitry. A first sequence of bits is generated, delayed, and sent to the optoelectronic device. The optoelectronic device receives the bits and retransmits them as a second sequence to the comparison circuitry, which compares the two bit sequences to determine a bit error rate. The bit error rate is then used to determine the jitter tolerance and, in an alternate embodiment, the signal attenuation tolerance of the optoelectronic device being tested.

Abstract: A method compensates for phase differences between sampled values of first and second AC waveforms. The method employs a phase angle compensation factor and sequentially samples a plurality of values of each of the waveforms. For a positive compensation factor, second sampled values are adjusted to correspond with first sampled values by employing, for a corresponding second sampled value, a preceding second sampled value plus the product of: (i) the compensation factor and (ii) the difference between the corresponding second sampled value and the preceding second sampled value. Alternatively, for a negative compensation factor, the second sampled values are adjusted by employing, for the corresponding second sampled value, the preceding second sampled value minus the product of: (i) the sum of one plus the compensation factor and (ii) the difference between the preceding second sampled value and the second sampled value preceding the preceding second sampled value.

Abstract: The present invention provides an apparatus and a method for determining a pulse position for a signal encoded by a pulse modulation. The signal being receivable as at least a first component (PCS) and a second component (DCS). A first storage unit (102) stores at least one symbol of the first component (PCS) and a second storage unit (104) at least one symbol of the second component (DCS). A determination unit (118) comprises a probability table (110), which in case that the first and second components (PCS, DCS) are received is addressed with the at least one symbol of the first component (PCS) and the at least one symbol of the second component (DCS). Thereby, the probability table (110) provides a value that is defined as the pulse position (DDS).

Abstract: A circuit and method for generating a delayed event following a trigger pulse occurring at a random time between clock pulses is disclosed. The circuit includes a clock circuit, a voltage converter, an analog-to-digital converter circuit, a memory storage circuit, and a summing circuit. The method includes representing the time between the triggering pulse and a subsequent clock pulse as a voltage, converting the voltage to a stored digital value, and defining a desired delay time by adding a first time determined by counting a predetermined number of clock cycles to a second time determined by converting the stored digital value first to an analog value and then to a time value.

Abstract: A system and technique for detecting a device that requires power is implemented with a power detection station. The power detection system includes a detector having an output and a return which are coupled together by the device when the device requires power. The detector includes a word generator for generating test pulses for transmission to the device via the detector output, and a comparator for comparing the detector output with the detector return. The power detection station has a wide variety of applications, including by way of example, a switch or hub.

Abstract: A digital protection and control device is so configured that at least parts of a digital data merging unit coupled to sensor units by a transmission medium, a protection and control unit, a communication unit for component control devices coupled to component control devices by a transmission medium, and a process bus communication unit are coupled by a parallel transmission medium, and at least a part of data exchange is based on a multimaster mode. Transmission based on the multimaster mode enables each unit to transmit/receive data independently and enables the reduction in unbalanced communication load. As a result, such a risk can be reduced that time responsiveness of operation is lowered as the entire digital protection and control device due to unbalanced concentration of data bus processing in a particular unit.

Abstract: Multi-phase clock time stamping for improving time stamp resolution is provided. One of many possible embodiments is a method for generating a time stamp having an improved time resolution for an event signal. Briefly described, one such method comprises the steps of: receiving an event signal for which a time stamp is to be generated; generating a first pulse signal having a pulse width defined by the event signal and a first clock signal; generating a second pulse signal having a pulse width defined by the event signal and a second clock signal; and determining which of the first pulse signal and the second pulse signal is to be used for generating the time stamp for the event signal.

Abstract: A method and system for performing sequence time domain reflectometry over a communication channel to determine the location of line anomalies in the communication channel is disclosed. In one embodiment, the system generates a sequence signal and transmits the sequence signal over an optical channel. The system receives one or more reflection signals over the optical channel and performs reflection signal processing on the reflection signal. In one embodiment, the optical reflection is transformed to an electrical signal and correlated with the original sequence signal to generate a correlated signal. The time between the start of the reflection signal and a subsequent point of correlation and the rate of propagation reveals a line anomaly location. In one or more embodiments sequence signal time domain reflectometry occurs during data transmission.

Abstract: A power management architecture for an electrical power distribution system, or portion thereof, is disclosed. The architecture includes multiple intelligent electronic devices (“IED's”) distributed throughout the power distribution system to manage the flow and consumption of power from the system using real time communications. Power management application software and/or hardware components operate on the IED's and the back-end servers and inter-operate via the network to implement a power management application. The architecture provides a scalable and cost effective framework of hardware and software upon which such power management applications can operate to manage the distribution and consumption of electrical power by one or more utilities/suppliers and/or customers which provide and utilize the power distribution system.

Abstract: Systems and methods for testing bit processing capacities of electronic devices and for reducing or eliminating jitter that compromises the ability of electronic devices to perform this task. Embodiments include circuitry and a methodology for locating and employing a data signal delay—in conjunction with a latch—to reduce or eliminate jitter from serial encoded data generated by a serializer/deserializer. The data signal delay ensures that the latch latches a state of the serial encoded data at a position within a data signal cycle of minimum jitter.

Abstract: A method and system for performing sequence time domain reflectometry to determine the location of line anomalies in a communication channel is disclosed. In one embodiment, the system generates a sequence signal and transmits the sequence signal over a channel that is the subject of the sequence time domain reflectometry analysis. The system monitors for and receives one or more reflections, collectively a reflection signal, and presents the reflection signal to a reflection processing module. In one embodiment, the reflection signal is correlated with the original sequence signal to generate a correlated signal. The system may perform signal analysis on the correlated signal to determine a time value between the start of the reflection signal and the subsequent points of correlation. Based on the time value and the rate of propagation of the signals through the channel, the reflection processing module determines a distance to a line anomaly.

Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response, and the second response for determining performance characteristics associated with the first transmission line.

Abstract: A self-calibrating sigma-delta converter (SCADC) functions in a calibration mode and in an operational mode. In the calibration mode, a test circuit of the SCADC generates test signals that are periodic rectangular voltage waveforms. Each test signal has a dc component with a precise voltage amplitude, as well as harmonic components. A low-pass filter of a sigma-delta converter (SDC) within the SCADC filters out the harmonic components. A digital calibration processing circuit within the SCADC uses the precise voltage amplitudes to generate digital correction factors that compensate for dc offset error, gain error and INL error of the SDC. In the operational mode, the SDC receives an analog operational signal and outputs an operational digital data stream. The digital calibration processing circuit uses the correction factors to compensate for dc offset error, gain error and INL error in the operational digital data stream and outputs a corrected digital data stream.

Abstract: A method for adjusting a duration of an internal timing signal in an integrated circuit with a value close to a typical value of the duration may include activating the internal timing signal in the integrated circuit and sequentially sending calibration values to an input of the integrated circuit. The expiration of the internal timing signal may determine the last calibration value received or being received, and the calibration data may be applied to a device for adjusting the duration of the internal timing signal.

Abstract: An analytical method and apparatus using principal component analysis of nuclear magnetic resonance (NMR) data for rapid molecular structure/function pattern recognition. The presence of a molecular substructure in an organic compound is determined by comparing principal components calculated from chemical shift values of the substructure in selected compounds with those calculated from the chemical shift values of the organic compound. Alternatively, principal components are calculated from the intensities of NMR signals for a full spectrum, or selected regions thereof, to determine whether an organic compound belongs to or is excluded from a set of structurally related compounds. Also, the presence of a pharmacophore in an organic compound can be determined by comparing the principal components derived from data on a set of compounds known to bind to a particular receptor, or have a common biological effect, with the principal components of the data set of the organic compound.

Abstract: An unusual waveform detection circuit is a digital-type unusual waveform detection circuit that arbitrarily sets a threshold used for determining an unusual waveform and produces an unusual waveform determination signal by comparing an input signal with the threshold. In producing the unusual waveform determination signal, one of a configuration where a voltage at each of all sampling points is compared with a reference voltage and a configuration where a continuously changing gradient of signal waveform peaks is calculated and is compared with a reference gradient is selectively employed. The unusual waveform detection circuit can easily and accurately detect various unusual waveforms.

Abstract: Identifying data loss in a transmission system includes shifting one of a received waveform and a transmitted waveform, determining differences between the transmitted and received waveforms at various shift points, and identifying a smallest of the differences between the transmitted and received waveforms. A plot of the differences relative to the shift points may be generated. The smallest of the differences may be a low vertex point on the plot.

Abstract: A method and system for performing sequence time domain reflectometry over a communication channel to determine the location of line anomalies in the communication channel is disclosed. In one embodiment, the system generates a sequence signal and transmits the sequence signal over an optical channel. The system receives one or more reflection signals over the optical channel and performs reflection signal processing on the reflection signal. In one embodiment, the optical reflection is transformed to an electrical signal and correlated with the original sequence signal to generate a correlated signal. The time between the start of the reflection signal and a subsequent point of correlation and the rate of propagation reveals a line anomaly location. A circulator, beam splitter, or any other similar device may direct the reflection signal to the apparatus configured to perform reflection signal processing.

Abstract: One or more queues store data information such as packets or data flows for later transmission to downstream communication devices. A real-time clock tracks current time and an advancement of a moving time reference, which is displaced with respect to the current time of the clock by an offset value. Thus, as current time advances, the moving time reference also advances in time. Upon servicing a queue, a time stamp associated with the serviced queue is also advanced in time. To monitor a rate of outputting data from the one or more queues, a processor device at least occasionally adjusts the offset value so that the moving time reference and values of the time stamps advance in relation to each other. Consequently, by tracking a relative time difference between current time of the real-time clock and a relative advancement of time stamps, a rate of outputting data information from the queue is monitored over time.

Abstract: An eye diagram analyzer equips each SUT data and clock signal input channel with individually variable delays in their respective paths. For a range of signal delay of n-many SUT clock cycles, the SUT clock signal delay might be set at about n/2. For each data channel there is specified a point in time relative to an instance of the delayed clock signal (data signal delay) and a voltage threshold. The specified combination (data signal delay, threshold and which channel) is a location on an eye diagram, although the trace may or may not ever go through that location. A counter counts the number of SUT clock cycles used as instances of the reference for the eye diagram, and another counter counts the number of times the specified combination of conditions was met (“hits”).

Abstract: A method for calibration of memory circuits is provided that adjusts memory circuit output parameters based on data eye measurements. Data eye patterns from the memory circuit outputs are measured by the memory controller for different settings of the memory circuit output parameters. Memory circuit output parameters can be adjusted to settings that correspond to widest average data eye widths, highest average data eye heights, or other suitable criteria.

Abstract: A process data capture and reporting system captures process data values at sensors. A client computer appends absolute-value time stamps to the values to complete records, which are uploaded to a server. The server writes the records to a persistent database. At a later stage, the server retrieves selected records, and performs a very fast conversion of the time stamps to a calendar format with “granular” values for units such as day, month, or minute. The conversion is performed in an optimised manner with use of look-up tables in memory. This minimises processor overhead, and is thus very advantageous where data volumes are high and/or near real time reporting is required.

Abstract: Propagation time Tp of an ultrasound signal between two spaced-apart transducers constituting an emitter and a receiver is measured. The emitter transducer is subjected to an excitation signal of n successive pulses of period Te giving rise to an ultrasound signal being emitted towards the receiver transducer which receives the ultrasound signal generating and outputting a receive signal. A measurement of an intermediate propagation time Tint is started when the emitter transducer begins to be excited. The receive signal is detected and the oscillations in the receive signal are counted. Measurement of the intermediate propagation time Tint is stopped when an ith oscillation is detected. The propagation time Tp is determined by taking the difference Tint?i×Te. Advantageously, measurement of Tint is stopped for an ith oscillation of the receive signal that corresponds to the receive signal being at a maximum amplitude.

Abstract: An arc fault circuit interrupter (AFCI) detects arc faults by identifying the various signature patterns of arc fault noise while rejecting arc mimicking noise from normal load phenomena.

Abstract: A method and apparatus for real-time derivation of precise digital clock edges and synchronous logic samples from multi-bit analog samples.

Abstract: A sensor network controller (4) includes: a sensor interface (44) receiving sensing data transmitted from sensors (5); a data write section (150) writing the received sensing data and sensing time information indicating a sensing time of the sensing data in association with each other to a memory section (42); the memory section (42) storing the sensing data and the sensing time information; a first data processing section (144) generating sensing data which is at the timing designated by a client on the basis of the sensing data and the sensing time information stored in the memory section (42); and a data output section (148) outputting the generated sensing data to the client. The client is enabled to acquire sensing data in accordance with a request even if the scheme by which the sensors convey sensing data does not match with the scheme by which the client makes a request for sensing data.